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Commit 0bf34b20 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Added manual pulse triggering and other info 

Extra info added:
- updated and corrected pulse jitter information
- updated memory map
- updated pulse repetition mechanism figure to contain pulse counters
  and manual pulse triggering
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent b8f35c09
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doc/userguide/cern-title.tex
View file @ 0bf34b20
......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill January 28, 2013
\hfill January 31, 2013
\vspace*{3cm}
......
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doc/userguide/userguide-conv-ttl-blo.tex
View file @ 0bf34b20
......@@ -60,6 +60,7 @@
23-12-2013 & 1.05 & Added remote reprogramming support \\
10-01-2014 & 1.06 & Added SNMP access sub-section \\
28-01-2014 & 1.07 & Added Diagnostics section and moved remote resetting subsection to this section \\
31-01-2014 & 1.08 & Added manual pulse triggering sub-section \\
\hline
\end{tabular}
}
......@@ -122,6 +123,7 @@ pulses (see Section~\ref{sec:pulse-def}). The main features of the board are:
\item gateware version
\item state of on-board switches and RTM detection lines
\item input pulse counters
\item manual pulse triggering
\end{itemize}
\item Remote reprogramming over I$^2$C lines on VME P1 connector
\item Status LEDs
......@@ -247,7 +249,7 @@ more details can be found in Section~\ref{sec:pulse-rep}. If a TTL (TTL-BAR) pul
on a channel input, it is regenerated on the output of the same channel in TTL (TTL-BAR),
as well as the blocking outputs of the same channel on the rear panel, if a CONV-TTL-RTM
board with an attached CONV-TTL-RTM-BLO is present. Similarly, if a blocking pulse arrives
on the back panel, it is replicated on the TTL output channel.
on the rear panel, it is replicated on the TTL output channel.
\begin{figure}[htbp]
\centerline{\includegraphics[scale=.75]{fig/ttl-chan}}
......@@ -339,6 +341,10 @@ the used switches are also listed in Table~\ref{tbl:switches}.
Note that both switches in Table~\ref{tbl:switches} are board-wide switches; selecting
one position or the other yields a selection valid for all six pulse replication channels.
\textbf{\textit{It is recommended to not switch any of the switches while the board is plugged
into the crate, otherwise potential damage can be incurred to hardware components on the
board.}}
%======================================================================================
% SEC: Pulse replication
%======================================================================================
......@@ -386,7 +392,7 @@ pulses.
$V_{OL}$ & Output pulse low-level amplitude & & 0 & 0.7 & V \\
$t_{p,i}$& Input pulse width & 50 & & & ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 4.8 & & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 6 & & & ${\mu}s$ \\
$t_r$ & Rise time & 1 & 3.2 & 4.9 & ns \\
$t_f$ & Fall time & 2 & 4 & 5.6 & ns \\
\hline
......@@ -396,7 +402,8 @@ pulses.
\noindent Note 1: Pulse amplitude for which a $t_{p,o}$ pulse is replicated at the output. \\
\noindent Note 2: $V_{IH}$, $V_{IL}$ correspond to the thresholds of input Schmitt triggers. \\
\noindent Note 3: Max. pulse frequency dictated by blocking output max. frequency. \\
\noindent Note 3: Max. pulse frequency dictated by blocking output max. frequency and limited
by the FPGA gateware. \\
\pagebreak
\begin{table}[h]
......@@ -415,7 +422,7 @@ pulses.
$V_{OL}$ & Output pulse low-level amplitude (2) & & 0 & & V \\
$t_{p,i}$& Input pulse width & 50 & & 3900& ns \\
$t_{p,o}$& Output pulse width & & 1.2 & & ${\mu}s$ \\
$T_{min}$& Min. period of pulse signal & 4.8 & & & ${\mu}s$ \\
$T_{min}$& Period of pulse signal (3) & 6 & & & ${\mu}s$ \\
$t_r$ & Rise time & 75 & 140 & 225 & ns \\
$t_f$ & Fall time & 75 & 160 & 225 & ns \\
\hline
......@@ -425,6 +432,8 @@ pulses.
\noindent Note 1: Pulse amplitude for which a $t_{p,o}$ pulse is replicated at the output. \\
\noindent Note 2: Voltage amplitude between the differential signal lines. \\
\noindent Note 3: Max. pulse frequency dictated by blocking output max. frequency and limited
by the FPGA gateware. \\
%--------------------------------------------------------------------------------------
% SUBSEC: TTL vs TTL-BAR
......@@ -480,12 +489,13 @@ plugged into a channel.
The pulse generator (PG) block in the FPGA generates $t_{p,o}$ wide (Table~\ref{tbl:pulse-def-ttl})
TTL pulses at its output on the rising edge of its input. It therefore expects TTL pulses at
its input. The rest of the logic external to this block is used to accomodate for TTL-BAR
its input. The rest of the logic external to this block is used to accommodate for TTL-BAR
and blocking pulses.
First, the OR gate at the PG input indicates the condition for a pulse to
be regenerated. When a pulse arrives at either of the two inputs, TTL or TTL-BAR on the
front panel, or blocking on the rear panel, a pulse is generated on the output.
First, the OR gates at the PG input indicate the condition for a pulse to
be regenerated. The conditions for pulse generation are either that pulse is manually triggered
as described in Section~\ref{sec:diag-man-trig}, or that a pulse arrives on either of the inputs of a channel
(TTL or TTL-BAR on the front panel, or blocking on the rear panel).
On the blocking side, the voltage level of blocking pulses arriving on the RTM is adapted
to a voltage level suitable for the FPGA by on-board circuitry external to the FPGA.
......@@ -504,14 +514,32 @@ The \textit{no signal detect} block at the multiplexer input on the TTL-BAR side
detects the lack of a signal by checking for a continuous high level on the line.
This is important when the TTL selection switch is set to TTL-BAR, since no signal
would mean a DC high-level signal appears at the OR gate input and this signal would
inhibit pulses arriving from the blocking side.
inhibit pulses arriving from the blocking side. The \textit{no signal detect} block
checks if the line is high for more than 100~$\mu$s when the TTL selection switch is
set for TTL-BAR signals and disables the TTL input line to the PG, thus allowing for
blocking pulses arriving on the rear panel to be detected by the PG.
\textbf{\textit{Note that due to the nature of TTL-BAR signals (high when idle), when the cable is removed
from the connector, or when the pulse sending device upstream of the CONV-TTL-BLO is turned off,
the channel line goes high due to the Schmitt trigger at the input of the CONV-TTL-BLO, and
a pulse will be generated on the output.}}
One pulse counter is implemented for each channel. As can be seen in Figure~\ref{fig:pulse-rep},
this pulse counter increments when a rising edge is detected on the output of the OR gate
between the two inputs types. More details about the pulse counters can be found in
Section~\ref{sec:diag-pulse-cnt}.
%--------------------------------------------------------------------------------------
% SUBSEC: Rep details
% SUBSEC: Pulse jitter and delay
%--------------------------------------------------------------------------------------
\subsection{Pulse jitter and delay}
\label{sec:pulse-jit}
Figure~\ref{fig:tpd-jit} defines propagation delay from input to output and output
jitter and shows how propagation delay was measured per each signal type.
Table~\ref{tbl:pulse-tpd-jit} presents the characteristics measured on
the CONV-TTL-BLO.
The PG block incorporates a glitch filter that can prevent pulses being generated as a
result of a glitch occurring on input channels. The glitch filter can be enabled via
SW1.1 (Figure~\ref{fig:switches-ptype}).
......@@ -523,27 +551,10 @@ SW1.1 (Figure~\ref{fig:switches-ptype}).
\end{figure}
Placing SW1.1 in the \textbf{ON} position will enable the glitch filter inside the PG block.
The pulse signal is sampled with a 125~MHz on-board clock and passed through the
glitch filter which rejects any pulses narrower than 40~ns, but introduces an 8~ns jitter
on the leading edge of the output signal. Jitter appears in the form of pulses being triggered
either 8~ns before or 8~ns after the ideal edge, based on when the input pulse is sampled.
This is shown in Figure~\ref{fig:tpd-jit}.
When SW1.1 is in the \textbf{OFF} (default) position, the glitch filter is disabled and the
pulse signal is regenerated at the output without being sampled with an on-board clock. This
yields jitter-free pulses at the output, but a glitch on the input will lead to a pulse being
generated at the output.
The glitch filter internal to the PG block may be enabled when the environment where the
board operates is noisy. A noisy environment may lead to glitches induced on the
signal lines and thus unwanted pulses on the output of the CONV-TTL-BLO. When the
environment is not so noisy, or when the 8~ns jitter is deemed to be an issue, SW1.1
can be left in the \textbf{OFF} position.
Figure~\ref{fig:tpd-jit} defines propagation delay from input to output and output
jitter and shows how propagation delay was measured per each signal type.
Table~\ref{tbl:pulse-tpd-jit} presents the characteristics measured on
the CONV-TTL-BLO.
The pulse signal is sampled with a 20~MHz on-board clock and passed through the
glitch filter which rejects any pulses narrower than 50~ns, but introduces a 50~ns jitter
on the leading edge of the output signal. Jitter appears in the form of an uncertainty on when
a pulse is output.
\begin{figure}[h]
\centerline{\includegraphics[width=.6\textwidth,keepaspectratio]{fig/tpd-jit}}
......@@ -563,7 +574,7 @@ the CONV-TTL-BLO.
\hline
$t_j$ & Leading edge jitter & & \\
& \hspace{2mm} Without glitch filter & 0 & ns \\
& \hspace{2mm} With glitch filter & 8 & ns \\
& \hspace{2mm} With glitch filter & 50 & ns \\
$t_{PD}$ & Propagation delay (1) & & \\
& \hspace{2mm} TTL to TTL & 40 & ns \\
& \hspace{2mm} TTL to blocking & 80 & ns \\
......@@ -578,7 +589,27 @@ the CONV-TTL-BLO.
}
\end{table}
\noindent Note 1: If glitch filter is enabled, it adds an extra 56~ns delay to $t_{PD}$.
\noindent Note 1: If the glitch filter is enabled, it adds an extra 350~ns delay to $t_{PD}$.
\vspace*{11pt}
Since an input pulse is asynchronous to the sampling clock, it may arrive
before or after the sampling clock's rising edge. If it arrives before the sampling clock rising
edge, it is sampled on the current cycle. However, if the input pulse arrives after the rising edge,
it will get sampled on the next clock rising edge. The output pulse may therefore present
an uncertainty on when its leading edge arrives; this uncertainty (shown in Figure~\ref{fig:tpd-jit}),
which is the output jitter, is based on the 50~ns sampling clock.
When SW1.1 is in the \textbf{OFF} (default) position, the glitch filter is disabled and the
pulse signal is regenerated at the output without being sampled with an on-board clock. This
yields jitter-free pulses at the output, but a glitch on the input will lead to a pulse being
generated at the output.
The glitch filter internal to the PG block may be enabled when the environment where the
board operates is noisy. A noisy environment may lead to glitches induced on the
signal lines and thus unwanted pulses on the output of the CONV-TTL-BLO. When the
environment is not so noisy, or when the 50~ns jitter is deemed to be an issue, SW1.1
can be left in the \textbf{OFF} position.
%======================================================================================
% SEC: Communicating to the CONV-TTL-BLO
......@@ -893,6 +924,63 @@ iso.3.6.1.4.1.37968.1.1.8.2.2.1.2.3 = STRING: "2"
Note that the backslash in the command above is not needed, it is just added
here for formatting reasons and to keep to the rules of the Linux command-line.
%------------------------------------------------------------------------------
% SUBSEC: Manual trigger
%------------------------------------------------------------------------------
\subsection{Manual pulse triggering}
\label{sec:diag-man-trig}
It is possible to remotely trigger a pulse on a channel of choice. This feature
should only be used when debugging the connection between two CONV-TTL-BLO boards,
or between a CONV-TTL-BLO and another receiver. This is why manual pulse
triggering is "password" protected.
In order to manually trigger a pulse, a user should write a four-byte "magic sequence"
(the "password") to the MPT (manual pulse trigger) field in the board's control
register at address 0x004 (CR -- see Appendix~\ref{app:memmap-cr}). The MPT
field is dual-purpose, as shown in Figure~\ref{fig:cr-mpt}. As shown in
Table~\ref{tbl:man-trig-magic}, prior to sending a pulse, the MPT field should be written
with the magic sequence, followed by a channel number in the range \textbf{1..6}.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/cr-mpt}}
\caption{MPT field in the CR}
\label{fig:cr-mpt}
\end{figure}
\begin{table}[h]
\caption{Write sequence to initiate manual pulse triggering}
\label{tbl:man-trig-magic}
\centerline
{
\begin{tabular}{c c c c c}
\hline
\textbf{Byte 0} & \textbf{Byte 1} & \textbf{Byte 2} & \textbf{Byte 3} & \textbf{Byte 4}\\
\hline
0xde & 0xad & 0xbe & 0xef & Channel number in range \textbf{1..6} \\
\hline
\end{tabular}
}
\end{table}
Note that in order for a pulse to be triggered, five write cycles to the MPT must be
done. If the fifth cycle is a channel number in the range \textbf{1..6}, one and only
one pulse is generated on the channel outputs (both TTL and blocking). After that,
should it be desired to generate another pulse on the channel, the magic sequence
must be input again. If the channel number is not in the range \textbf{1..6}, no
pulse is generated on any channel and no error is reported.
Figure~\ref{fig:man-trig-fsm} shows the logic of the manual pulse triggering
mechanism. As can be seen from the figure, if one of the bytes of the magic
sequence is not as expected, the logic returns to waiting for the first byte
of the magic sequence.
\begin{figure}[h]
\centerline{\includegraphics[width=.6\textwidth]{fig/man-trig-fsm}}
\caption{Manual pulse triggering logic}
\label{fig:man-trig-fsm}
\end{figure}
%==============================================================================
% SEC: Remote reprog
%==============================================================================
......@@ -1206,7 +1294,7 @@ Blocking pulses arriving on CH1 then get replicated through the daisy chain from
By connecting all outputs of channels 1 through 4 on the rear panel, the desired pulse
conversion system can be obtained.
Each channel will add a 40~ns delay (96~ns with glitch filter), in addition to the 160~ns (272~ns
Each channel will add a 40~ns delay (390~ns with glitch filter), in addition to the 160~ns (410~ns
with glitch filters) of the CH1 and CH4 blocking conversions.
\begin{figure}[h]
......@@ -1362,7 +1450,8 @@ $reg. index = \frac{addr}{4} + 1$
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
0 & RST\_UNLOCK & R/W & 0 & Reset bit unlock \\
1 & RST & R/W & 0 & Reset bit \\
31..2 & \textit{Reserved} & -- & X & \\
9..2 & MPT & W/O & 0 & Manual Pulse Trigger \\
31..10 & \textit{Reserved} & -- & X & \\
\end{tabular}
\noindent
......@@ -1380,6 +1469,13 @@ $reg. index = \frac{addr}{4} + 1$
previous cycle. A write to this bit while RST\_UNLOCK = '0' has no effect. \newline
Writing this bit to 1 with RST\_UNLOCK = '1' will issue a system reset and
the communication to the board will be lost for approx. 100~ms \\
MPT & Control bits for manual pulse trigger sequence \newline
To trigger a pulse, write this sequence to the field: \newline
\textbf{0xde} -- Passbyte 1 \newline
\textbf{0xad} -- Passbyte 2 \newline
\textbf{0xbe} -- Passbyte 3 \newline
\textbf{0xef} -- Passbyte 4 \newline
Channel number in range 1..6 \\
\textit{Reserved} & Write as '0'; read undefined \\
\end{tabular}
}
......
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