|
|
# Project Description
|
|
|
# Conv-TTL-Blo
|
|
|
|
|
|
## Project Description
|
|
|
|
|
|
The TTL to blocking converter is a system designed to replicate TTL and
|
|
|
blocking pulses. An incoming TTL pulse is replicated simultaneously on
|
|
|
both the TTL and blocking channel on which it was received. The reverse
|
|
|
also holds true, i.e., a blocking pulse on an input channel gets
|
|
|
repeated on both the TTL and blocking outputs of the respective channel.
|
|
|
The system consists of two VME64x double height boards, the front module
|
|
|
and the rear transition module (RTM). The front module contains all the
|
|
|
active circuitry, whereas the RTM is passive and targeted for
|
|
|
connectivity.
|
|
|
both the TTL and blocking channel on which it was received. Similarly, a
|
|
|
blocking pulse on an input channel is replicated on both blocking and
|
|
|
TTL outputs of the respective channel. The system consists of two VME64x
|
|
|
double height boards, the front module and the rear transition module
|
|
|
(RTM). The front module contains all the active circuitry, whereas the
|
|
|
RTM is passive and targeted for connectivity.
|
|
|
|
|
|
fp-top-bot.png
|
|
|
|
|
|
## Main Features
|
|
|
|
|
|
- VME64x double-height form factor using Front and Rear Transition
|
|
|
Module
|
|
|
- VME64x double-height form factor using front and rear transition
|
|
|
module (RTM)
|
|
|
- The output pulse is a CERN level standard, [Standard
|
|
|
Blocking](https://www.ohwr.org/project/conv-ttl-blo/uploads/8ba57dff4f18540c947830f70e8c8ead/BlockingSpecification.pdf).
|
|
|
- 6 conversion channels. Every channel has:
|
... | ... | @@ -33,26 +34,23 @@ fp-top-bot.png |
|
|
- *Provisioned*: time-tagging via
|
|
|
[White-Rabbit](https://www.ohwr.org/project/white-rabbit);
|
|
|
- *Provisioned*: Remote upgrade of FPGA firmware via I2C protocol
|
|
|
- LEDs in panels:
|
|
|
- One LED for every channel, front and rear panels;
|
|
|
- LEDs:
|
|
|
- One pulse LED for every channel, front and rear panels;
|
|
|
- Various status LEDs on the front panel (White Rabbit, multicast,
|
|
|
power, error, etc.);
|
|
|
- [RTM Detection](RTM-board-detection)..
|
|
|
- [RTM Detection](RTM-board-detection).
|
|
|
|
|
|
-----
|
|
|
|
|
|
## Documents
|
|
|
## Project Information
|
|
|
|
|
|
- Production information:
|
|
|
- [EDA-02446](http://edms.cern.ch/nav/EDA-02446) CONV-TTL-BLO
|
|
|
Front module
|
|
|
- [EDA-02452](http://edms.cern.ch/nav/EDA-02452) CONV-TTL-RTM Rear
|
|
|
Transition module
|
|
|
front module
|
|
|
- [EDA-02452](http://edms.cern.ch/nav/EDA-02452) CONV-TTL-RTM rear
|
|
|
transition module
|
|
|
- [EDA-02453](http://edms.cern.ch/nav/EDA-02453) CONV-TTL-RTM-BLO
|
|
|
Piggyback on RTM with connectors
|
|
|
- CERN LHC Equipment names
|
|
|
- Pulse Repeater VME, front module:
|
|
|
[CTDAH](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCTDAH___:V0/TAB4)
|
|
|
- Rear transition module:
|
|
|
[CTARA](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCTARA___:V0/TAB4)
|
|
|
piggyback on RTM with connectors
|
|
|
- CERN BE-CO-HT Wikis:
|
|
|
- What is a [blocking oscillator](BlockingOscillator) and why is
|
|
|
it not longer used.
|
... | ... | @@ -72,7 +70,12 @@ fp-top-bot.png |
|
|
- Chapter 17 in [Commands Line Tools User
|
|
|
Guide](http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_2/devref.pdf)
|
|
|
offers more specific information about Xilinx's PROMGen.
|
|
|
- On the [selection of OS-CON and POSCAP](CondPoly) capacitors.
|
|
|
- [3U crates replacement
|
|
|
project](http://wikis/display/HT/3U+crates+replacement)
|
|
|
- 3U level adapter module
|
|
|
[LA-TTL-BLO](http://wikis/display/HT/LA-TTL-BLO+-+Level+adapter+TTL+to+BLO)
|
|
|
modules (CERN only)
|
|
|
- [Selecting OS-CON and POSCAP](CondPoly) capacitors.
|
|
|
- On ELMA crate:
|
|
|
- ELMA crates in EDMS:
|
|
|
- [ELMA 041-240 Index
|
... | ... | @@ -86,12 +89,9 @@ fp-top-bot.png |
|
|
- [System Monitor User's
|
|
|
Manual](https://www.ohwr.org/project/conv-ttl-blo/wikis/Documents/ELMA-SysMon-User-Manual)
|
|
|
|
|
|
## Project status
|
|
|
|
|
|
Currently we are working in the HDL code. For more information click on
|
|
|
the image below:
|
|
|
-----
|
|
|
|
|
|
HDLstatusIcon.png:/project/conv-ttl-blo/wikis/HDLStatus
|
|
|
## Status
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
... | ... | @@ -306,15 +306,8 @@ HDLstatusIcon.png:/project/conv-ttl-blo/wikis/HDLStatus |
|
|
</tbody>
|
|
|
</table>
|
|
|
|
|
|
## References
|
|
|
|
|
|
- [3U crates replacement
|
|
|
project](http://wikis/display/HT/3U+crates+replacement)
|
|
|
- 3U level adapter module
|
|
|
[LA-TTL-BLO](http://wikis/display/HT/LA-TTL-BLO+-+Level+adapter+TTL+to+BLO)
|
|
|
modules (CERN only)
|
|
|
|
|
|
-----
|
|
|
|
|
|
Carlos Gil Soriano, Thedi Stana, Erik van der Bij - 27 March 2013
|
|
|
Carlos Gil Soriano, Theodor-Adrian Stana, Erik van der Bij - 03 June
|
|
|
2013
|
|
|
|