|
# TTL to/from Blocking level converter
|
|
# TTL to/from Blocking level converter
|
|
|
|
|
|
|
|
The Blocking converter is a system which converts TTL pulses to Blocking
|
|
|
|
ones and it is able to replicate the later ones. The system consists of
|
|
|
|
two VME64x double height boards: a front one and a rear one. The front
|
|
|
|
board holds all the active circuitry, whereas the rear board is passive
|
|
|
|
and targeted for connectivity. By dividing the functionality of each
|
|
|
|
board in this way, an improvement can be achieved in terms of ease of
|
|
|
|
maintenance.
|
|
|
|
|
|
|
|
A block diagram with the main functionalities carried out by the pulse
|
|
|
|
converter system is shown below.
|
|
|
|
|
|
|
|
BLOschema.png
|
|
|
|
|
|
|
|
## How does it work?
|
|
|
|
|
|
|
|
When a pulse is received either in the front panel (TTL level) or the
|
|
|
|
rear one (Blocking level), the event is time-tagged in the FPGA and a
|
|
|
|
Blocking pulse is outputted in the rear panel. Then, the information
|
|
|
|
about the events received in the FPGA can be accessed through the I2C
|
|
|
|
pins in the VME64x J1 connector.
|
|
|
|
|
|
## Features
|
|
## Features
|
|
|
|
|
|
- VME64x form factor using Front and Rear Transition Module
|
|
- VME64x form factor using Front and Rear Transition Module
|
|
- 6 channels with 1 selectable TTL/TTL-bar/Blocking-level input, two
|
|
|
|
Blocking level outputs and one "daisy-chain ready" output.
|
|
|
|
- The output pulse is a CERN level standard, "Standard Blocking".
|
|
- The output pulse is a CERN level standard, "Standard Blocking".
|
|
- LEMO 00 connectors
|
|
- 6 conversion channels. Every channel has:
|
|
|
|
- A TTL input in the front panel.
|
|
See also [Review of architecture](Review200711) and [Second Review of
|
|
- A Blocking input in the rear panel.
|
|
architecture](Review201011)
|
|
- Three Blocking outputs in the rear panel.
|
|
|
|
- LEMO 00 connectors in both front and rear panels.
|
|
|
|
- Galvanic isolation for inputs and outputs.
|
|
|
|
- Input protection against high-current and high-voltage transients.
|
|
|
|
- FPGA firmware can be remotely upgradeable.
|
|
|
|
|
|
## Documents
|
|
## Documents
|
|
|
|
|
|
- Production information: EDA-
|
|
- Production information: EDA-
|
|
- CERN LHC Equipment names
|
|
- CERN LHC Equipment names
|
|
- Pulse Repeater VME:
|
|
- Pulse Repeater VME, front module:
|
|
[CTDAH](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCTDAH___:V0/TAB4)
|
|
[CTDAH](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCTDAH___:V0/TAB4)
|
|
- Rear transition module:
|
|
- Rear transition module:
|
|
[CTARA](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCTARA___:V0/TAB4)
|
|
[CTARA](https://edms.cern.ch/nav/P:CERN-0000077383:V0/I:HCCTARA___:V0/TAB4)
|
|
- CERN BE-CO-HT Wikis:
|
|
- CERN BE-CO-HT Wikis:
|
|
- A monostable [blocking oscillator](BlockingOscillator) pulsed
|
|
- What is a [blocking oscillator](BlockingOscillator) and why is
|
|
output
|
|
not longer used.
|
|
- Design guidelines, simulation, and measures of a [Flyback
|
|
- [Design guidelines](https://www.ohwr.org/documents/110) and
|
|
circuit](Flyback-Design-Guidelines) prototype that outputs a
|
|
[Blocking driver measurements](BlockingMeasures).
|
|
Standard Blocking pulse.
|
|
- Reviews of architecture:
|
|
|
|
- [Review of architecture](Review200711)
|
|
|
|
- [Second Review of architecture](Review201011)
|
|
|
|
|
|
## Project status
|
|
## Project status
|
|
|
|
|
... | @@ -108,7 +133,7 @@ architecture](Review201011) |
... | @@ -108,7 +133,7 @@ architecture](Review201011) |
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
<td>21-11-2011</td>
|
|
<td>21-11-2011</td>
|
|
<td>[Files for Schematics Revision C](https://www.ohwr.org/872).</td>
|
|
<td>[Files for Schematics Revision C](https://www.ohwr.org/873).</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td>30-11-2011</td>
|
|
<td>30-11-2011</td>
|
... | | ... | |