Commit d0298087 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag

Generated htm and tex files for current register map of pts

parent 5988404a
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<HEAD>
<TITLE>pts_regs</TITLE>
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</HEAD>
<BODY>
<h1 class="heading">pts_regs</h1>
<h3>PTS control and status registers</h3>
<p></p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">BIDR</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">CSR</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">LSR</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#BIDR">BIDR</a>
</td>
<td class="td_code">
pts_bidr
</td>
<td class="td_code">
BIDR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#CSR">CSR</a>
</td>
<td class="td_code">
pts_csr
</td>
<td class="td_code">
CSR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#LSR">LSR</a>
</td>
<td class="td_code">
pts_lsr
</td>
<td class="td_code">
LSR
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>BIDR:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_bidr_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[1:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>CSR:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_chledt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_stledt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rledt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_ttlpt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rearpt_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_hwvers_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_unlock_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_unlock_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_unlock_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rst_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_switch_i[7:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_rtm_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_err_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_err_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_err_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_wdto_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_wdto_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_csr_i2c_wdto_load_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>LSR:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_lsr_front_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_lsr_frontinv_i[3:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
pts_lsr_rear_i[5:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="BIDR"></a>
<h3><a name="sect_3_1">3.1. BIDR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
pts_bidr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
BIDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
Board ID Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BIDR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BIDR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BIDR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
BIDR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
BIDR
</b>[<i>read-only</i>]: ID register bits
</ul>
<a name="CSR"></a>
<h3><a name="sect_3_2">3.2. CSR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
pts_csr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CSR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
Control and Status Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
I2C_WDTO
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
I2C_ERR
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
RTM[5:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
SWITCH[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RST
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RST_UNLOCK
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
HWVERS[5:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
REARPT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
TTLPT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
RLEDT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
STLEDT
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
CHLEDT
</td>
</tr>
</table>
<ul>
<li><b>
CHLEDT
</b>[<i>read/write</i>]: Channel pulse LED enable
<br>1 -- Enable channel LED sequencing <br> 0 -- No effect
<li><b>
STLEDT
</b>[<i>read/write</i>]: Status LED enable
<br>1 -- Enable front panel bicolor LED sequencing <br> 0 -- No effect
<li><b>
RLEDT
</b>[<i>read/write</i>]: Rear pulse LED line
<br>1 -- Set LED lines high <br> 0 -- No effect
<li><b>
TTLPT
</b>[<i>read/write</i>]: TTL test enable
<br>1 -- Enable pulse generation from CH1 <br> 0 -- No effect
<li><b>
REARPT
</b>[<i>read/write</i>]: Rear pulse enable
<br>1 -- Enable rear panel pulse generation <br> 0 -- No effect
<li><b>
HWVERS
</b>[<i>read-only</i>]: PCB version number
<br>6 bits representing HW/PCB version number <br> 4 MSB represent HW version number <br> 2 LSB represent number of execution <br> Eg: value 010010 represents PCB version 4.2
<li><b>
RST_UNLOCK
</b>[<i>read/write</i>]: Reset unlock bit
<br>1 -- Reset bit unlocked <br> 0 -- Reset bit locked
<li><b>
RST
</b>[<i>read/write</i>]: Reset bit -- active only if RST_UNLOCK is 1
<br>1 -- initiate logic reset <br> 0 -- no reset
<li><b>
SWITCH
</b>[<i>read-only</i>]: switches
<br>1 - switch is ON <br> 0 - switch is OFF
<li><b>
RTM
</b>[<i>read-only</i>]: RTM detection lines
<br>1 - line active <br> 0 - line inactive
<li><b>
I2C_ERR
</b>[<i>read/write</i>]: I2C communication error
<br>1 -- attempted to address non-existing address <br> 0 -- idle <br> This bit can be cleared by writing a '1' to it
<li><b>
I2C_WDTO
</b>[<i>read/write</i>]: I2C communication watchdog timeout error
<br>1 -- timeout occured <br> 0 -- no timeout <br> This bit can be cleared by writing a '1' to it
</ul>
<a name="LSR"></a>
<h3><a name="sect_3_3">3.3. LSR</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
pts_lsr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
LSR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<p>
Line Status Register
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=6 class="td_field">
REAR[5:0]
</td>
<td style="border: solid 1px black;" colspan=2 class="td_field">
FRONTINV[3:2]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=2 class="td_field">
FRONTINV[1:0]
</td>
<td style="border: solid 1px black;" colspan=6 class="td_field">
FRONT[5:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FRONT
</b>[<i>read-only</i>]: Front panel channel input state
<br>Line state at board input<br> Bit 0 -- channel 1<br> Bit 1 -- channel 2<br> etc.
<li><b>
FRONTINV
</b>[<i>read-only</i>]: Front panel INV-TTL input state
<br>Line state at board input<br> Bit 0 -- channel 1<br> Bit 1 -- channel 2<br> etc.
<li><b>
REAR
</b>[<i>read-only</i>]: Rear panel input state
<br>Line state at board input<br> Bit 0 -- channel 1<br> Bit 1 -- channel 2<br> etc.
</ul>
</BODY>
</HTML>
\subsection{PTS control and status registers}
\label{subsec:wbgen:pts}
\subsubsection{Memory map summary}
\rowcolors{2}{gray!25}{white}
\resizebox{\textwidth}{!}{
\begin{tabular}{|l|l|l|l|l|}
\rowcolor{RoyalPurple}
\color{white} SW Offset & \color{white} Type & \color{white} Name &
\color{white} HW prefix & \color{white} C prefix\\
0x0& REG & BIDR & pts\_bidr & BIDR\\
0x4& REG & CSR & pts\_csr & CSR\\
0x8& REG & LSR & pts\_lsr & LSR\\
\hline
\end{tabular}
}
\subsubsection{Register description}
\paragraph*{BIDR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_bidr\\
{\bf HW address:} & 0x0\\
{\bf SW prefix:} & BIDR\\
{\bf SW offset:} & 0x0\\
\end{tabular}
\vspace{12pt}
Board ID Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[31:24]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[23:16]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[15:8]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}BIDR[7:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
BIDR
} [\emph{read-only}]: ID register bits
\end{small}
\end{itemize}
\paragraph*{CSR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_csr\\
{\bf HW address:} & 0x1\\
{\bf SW prefix:} & CSR\\
{\bf SW offset:} & 0x4\\
\end{tabular}
\vspace{12pt}
Control and Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_WDTO} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}I2C\_ERR} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}RTM[5:0]}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{8}{|c|}{\cellcolor{RoyalPurple!25}SWITCH[7:0]}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RST\_UNLOCK} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}HWVERS[5:0]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{1}{|c}{-} & - & - & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}REARPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}TTLPT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}RLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}STLEDT} & \multicolumn{1}{|c|}{\cellcolor{RoyalPurple!25}CHLEDT}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
CHLEDT
} [\emph{read/write}]: Channel pulse LED enable
\\
1 -- Enable channel LED sequencing \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
STLEDT
} [\emph{read/write}]: Status LED enable
\\
1 -- Enable front panel bicolor LED sequencing \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
RLEDT
} [\emph{read/write}]: Rear pulse LED line
\\
1 -- Set LED lines high \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
TTLPT
} [\emph{read/write}]: TTL test enable
\\
1 -- Enable pulse generation from CH1 \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
REARPT
} [\emph{read/write}]: Rear pulse enable
\\
1 -- Enable rear panel pulse generation \\ 0 -- No effect
\end{small}
\item \begin{small}
{\bf
HWVERS
} [\emph{read-only}]: PCB version number
\\
6 bits representing HW/PCB version number \\ 4 MSB represent HW version number \\ 2 LSB represent number of execution \\ Eg: value 010010 represents PCB version 4.2
\end{small}
\item \begin{small}
{\bf
RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit
\\
1 -- Reset bit unlocked \\ 0 -- Reset bit locked
\end{small}
\item \begin{small}
{\bf
RST
} [\emph{read/write}]: Reset bit -- active only if RST_UNLOCK is 1
\\
1 -- initiate logic reset \\ 0 -- no reset
\end{small}
\item \begin{small}
{\bf
SWITCH
} [\emph{read-only}]: switches
\\
1 - switch is ON \\ 0 - switch is OFF
\end{small}
\item \begin{small}
{\bf
RTM
} [\emph{read-only}]: RTM detection lines
\\
1 - line active \\ 0 - line inactive
\end{small}
\item \begin{small}
{\bf
I2C\_ERR
} [\emph{read/write}]: I2C communication error
\\
1 -- attempted to address non-existing address \\ 0 -- idle \\ This bit can be cleared by writing a '1' to it
\end{small}
\item \begin{small}
{\bf
I2C\_WDTO
} [\emph{read/write}]: I2C communication watchdog timeout error
\\
1 -- timeout occured \\ 0 -- no timeout \\ This bit can be cleared by writing a '1' to it
\end{small}
\end{itemize}
\paragraph*{LSR}\vspace{12pt}
\rowcolors{1}{white}{white}
\begin{tabular}{l l }
{\bf HW prefix:} & pts\_lsr\\
{\bf HW address:} & 0x2\\
{\bf SW prefix:} & LSR\\
{\bf SW offset:} & 0x8\\
\end{tabular}
\vspace{12pt}
Line Status Register
\vspace{12pt}
\noindent
\resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline
\multicolumn{1}{|c}{-} & - & - & - & - & - & - & \multicolumn{1}{c|}{-}\\
\hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline
\multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}REAR[5:0]} & \multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[3:2]}\\
\hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline
\multicolumn{2}{|c|}{\cellcolor{RoyalPurple!25}FRONTINV[1:0]} & \multicolumn{6}{|c|}{\cellcolor{RoyalPurple!25}FRONT[5:0]}\\
\hline
\end{tabular}
}
\begin{itemize}
\item \begin{small}
{\bf
FRONT
} [\emph{read-only}]: Front panel channel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
FRONTINV
} [\emph{read-only}]: Front panel INV-TTL input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\item \begin{small}
{\bf
REAR
} [\emph{read-only}]: Rear panel input state
\\
Line state at board input\\ Bit 0 -- channel 1\\ Bit 1 -- channel 2\\ etc.
\end{small}
\end{itemize}
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