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Conv TTL Blocking - Testing
Commit 933d74ac authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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rtm-hdl: Updated top-level file and ISE proj file according to latest changes 

See last two commits for why this had to be done.
parent 8cf44222
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Showing with 119 additions and 264 deletions
rtm/hdl/syn/Makefile
View file @ 933d74ac
...@@ -22,163 +22,3 @@ clean: ...@@ -22,163 +22,3 @@ clean:
mrproper: mrproper:
rm -f *.bit *.bin *.mcs rm -f *.bit *.bin *.mcs
USER:=$(HDLMAKE_USER)#take the value from the environment
SERVER:=$(HDLMAKE_SERVER)#take the value from the environment
R_NAME:=pts_conv_ttl_blo_rtm
__test_for_remote_synthesis_variables:
ifeq (x$(USER),x)
@echo "Remote synthesis user is not set. You can set it by editing variable USER in the makefile." && false
endif
ifeq (x$(SERVER),x)
@echo "Remote synthesis server is not set. You can set it by editing variable SERVER in the makefile." && false
endif
CWD := $(shell pwd)
FILES := ../top/pts_conv_ttl_blo_rtm.vhd \
../top/pts_conv_ttl_blo_rtm.ucf \
../modules/pulse_gen_gp.vhd \
../modules/reset_gen.vhd \
../modules/rtm_detector.vhd \
../modules/pts_regs.vhd \
../modules/pulse_cnt_wb.vhd \
../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../ip_cores/general-cores/modules/common/gc_reset.vhd \
../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd \
../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd \
../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd \
../ip_cores/general-cores/modules/common/gc_word_packer.vhd \
../ip_cores/general-cores/modules/common/gc_i2c_slave.vhd \
../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd \
../ip_cores/general-cores/modules/common/gc_big_adder.vhd \
../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd \
../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd \
../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd \
../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd \
../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd \
../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd \
../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd \
../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd \
../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd \
../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd \
../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd \
../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd \
../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v \
../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v \
../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd \
../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd \
../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd \
../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd \
../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd \
../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd \
../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd \
../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd \
../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd \
../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd \
../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd \
../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd \
../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd \
../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd \
../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v \
../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v \
../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v \
run.tcl \
pts_conv_ttl_blo_rtm.xise
#target for running simulation in the remote location
remote: __test_for_remote_synthesis_variables __send __do_synthesis __send_back
__send_back: __do_synthesis
__do_synthesis: __send
__send: __test_for_remote_synthesis_variables
__send:
ssh $(USER)@$(SERVER) 'mkdir -p $(R_NAME)'
rsync -Rav $(foreach file, $(FILES), $(shell readlink -f $(file))) $(USER)@$(SERVER):$(R_NAME)
__do_synthesis:
ssh $(USER)@$(SERVER) 'cd $(R_NAME)$(CWD) && xtclsh run.tcl'
__send_back:
cd .. && rsync -av $(USER)@$(SERVER):$(R_NAME)$(CWD) . && cd $(CWD)
#target for removing stuff from the remote location
cleanremote:
ssh $(USER)@$(SERVER) 'rm -rf $(R_NAME)'
rtm/hdl/syn/pts_conv_ttl_blo_rtm.xise
View file @ 933d74ac
...@@ -340,7 +340,7 @@ ...@@ -340,7 +340,7 @@
<file xil_pn:name="../top/pts_conv_ttl_blo_rtm.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="../top/pts_conv_ttl_blo_rtm.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="../top/pts_conv_ttl_blo_rtm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="../modules/pulse_gen_gp.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../modules/pulse_gen_gp.vhd" xil_pn:type="FILE_VHDL">
...@@ -412,291 +412,294 @@ ...@@ -412,291 +412,294 @@
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/> <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dyn_glitch_filt.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/> <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_fsm_watchdog.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/> <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/> <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../top/pts_conv_ttl_blo_rtm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/> <association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/> <association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/> <association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/> <association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/> <association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/common/gc_big_adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/> <association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/> <association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/> <association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/> <association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/> <association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/> <association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/> <association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/> <association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/> <association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/> <association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/> <association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/> <association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/> <association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/> <association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/> <association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/> <association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/> <association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/> <association xil_pn:name="Implementation" xil_pn:seqID="52"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/> <association xil_pn:name="Implementation" xil_pn:seqID="53"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/> <association xil_pn:name="Implementation" xil_pn:seqID="54"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/> <association xil_pn:name="Implementation" xil_pn:seqID="55"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/> <association xil_pn:name="Implementation" xil_pn:seqID="56"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/> <association xil_pn:name="Implementation" xil_pn:seqID="57"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/> <association xil_pn:name="Implementation" xil_pn:seqID="58"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/> <association xil_pn:name="Implementation" xil_pn:seqID="59"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/> <association xil_pn:name="Implementation" xil_pn:seqID="60"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/> <association xil_pn:name="Implementation" xil_pn:seqID="61"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/> <association xil_pn:name="Implementation" xil_pn:seqID="62"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/> <association xil_pn:name="Implementation" xil_pn:seqID="63"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/> <association xil_pn:name="Implementation" xil_pn:seqID="64"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/> <association xil_pn:name="Implementation" xil_pn:seqID="65"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/> <association xil_pn:name="Implementation" xil_pn:seqID="66"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/> <association xil_pn:name="Implementation" xil_pn:seqID="67"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/> <association xil_pn:name="Implementation" xil_pn:seqID="68"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/> <association xil_pn:name="Implementation" xil_pn:seqID="69"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/> <association xil_pn:name="Implementation" xil_pn:seqID="70"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/> <association xil_pn:name="Implementation" xil_pn:seqID="71"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/> <association xil_pn:name="Implementation" xil_pn:seqID="72"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/> <association xil_pn:name="Implementation" xil_pn:seqID="73"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/> <association xil_pn:name="Implementation" xil_pn:seqID="74"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/> <association xil_pn:name="Implementation" xil_pn:seqID="75"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/> <association xil_pn:name="Implementation" xil_pn:seqID="76"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/> <association xil_pn:name="Implementation" xil_pn:seqID="77"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/> <association xil_pn:name="Implementation" xil_pn:seqID="78"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_register_link.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/> <association xil_pn:name="Implementation" xil_pn:seqID="79"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/> <association xil_pn:name="Implementation" xil_pn:seqID="80"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/irqm_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/> <association xil_pn:name="Implementation" xil_pn:seqID="81"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/> <association xil_pn:name="Implementation" xil_pn:seqID="82"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_slave.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/> <association xil_pn:name="Implementation" xil_pn:seqID="83"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/> <association xil_pn:name="Implementation" xil_pn:seqID="84"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_irq/wb_irq_timer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/> <association xil_pn:name="Implementation" xil_pn:seqID="85"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/> <association xil_pn:name="Implementation" xil_pn:seqID="86"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/> <association xil_pn:name="Implementation" xil_pn:seqID="87"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/> <association xil_pn:name="Implementation" xil_pn:seqID="88"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/> <association xil_pn:name="Implementation" xil_pn:seqID="89"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/> <association xil_pn:name="Implementation" xil_pn:seqID="90"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/> <association xil_pn:name="Implementation" xil_pn:seqID="91"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/> <association xil_pn:name="Implementation" xil_pn:seqID="92"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/> <association xil_pn:name="Implementation" xil_pn:seqID="93"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/> <association xil_pn:name="Implementation" xil_pn:seqID="94"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/> <association xil_pn:name="Implementation" xil_pn:seqID="95"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/> <association xil_pn:name="Implementation" xil_pn:seqID="96"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/> <association xil_pn:name="Implementation" xil_pn:seqID="97"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/> <association xil_pn:name="Implementation" xil_pn:seqID="98"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/> <association xil_pn:name="Implementation" xil_pn:seqID="99"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/> <association xil_pn:name="Implementation" xil_pn:seqID="100"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_streamer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/> <association xil_pn:name="Implementation" xil_pn:seqID="101"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_serial_lcd/wb_serial_lcd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/> <association xil_pn:name="Implementation" xil_pn:seqID="102"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi_flash/wb_spi_flash.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/> <association xil_pn:name="Implementation" xil_pn:seqID="103"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="104"/> <association xil_pn:name="Implementation" xil_pn:seqID="104"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/simple_pwm_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="105"/> <association xil_pn:name="Implementation" xil_pn:seqID="105"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/wb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="106"/> <association xil_pn:name="Implementation" xil_pn:seqID="106"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_pwm/xwb_simple_pwm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="107"/> <association xil_pn:name="Implementation" xil_pn:seqID="107"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_bridge/wb_i2c_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="108"/> <association xil_pn:name="Implementation" xil_pn:seqID="108"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="109"/> <association xil_pn:name="Implementation" xil_pn:seqID="109"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="110"/> <association xil_pn:name="Implementation" xil_pn:seqID="110"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="111"/> <association xil_pn:name="Implementation" xil_pn:seqID="111"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="112"/> <association xil_pn:name="Implementation" xil_pn:seqID="112"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="113"/> <association xil_pn:name="Implementation" xil_pn:seqID="113"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="114"/> <association xil_pn:name="Implementation" xil_pn:seqID="114"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="115"/> <association xil_pn:name="Implementation" xil_pn:seqID="115"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="116"/> <association xil_pn:name="Implementation" xil_pn:seqID="116"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="117"/> <association xil_pn:name="Implementation" xil_pn:seqID="117"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/spi_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="118"/> <association xil_pn:name="Implementation" xil_pn:seqID="118"/>
</file> </file>
<file xil_pn:name="../modules/bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_fsm.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="119"/> <association xil_pn:name="Implementation" xil_pn:seqID="119"/>
</file> </file>
<file xil_pn:name="../modules/bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="120"/> <association xil_pn:name="Implementation" xil_pn:seqID="120"/>
</file> </file>
<file xil_pn:name="../ip_cores/general-cores/platform/xilinx/wb_xil_multiboot/wb_xil_multiboot.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="121"/>
</file>
</files> </files>
<bindings/> <bindings/>
......
rtm/hdl/top/pts_conv_ttl_blo_rtm.vhd
View file @ 933d74ac
...@@ -43,7 +43,6 @@ use ieee.std_logic_1164.all; ...@@ -43,7 +43,6 @@ use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use unisim.vcomponents.all; use unisim.vcomponents.all;
use work.bicolor_led_ctrl_pkg.all;
use work.genram_pkg.all; use work.genram_pkg.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
use work.wishbone_pkg.all; use work.wishbone_pkg.all;
...@@ -197,12 +196,12 @@ architecture behav of pts_conv_ttl_blo_rtm is ...@@ -197,12 +196,12 @@ architecture behav of pts_conv_ttl_blo_rtm is
c_slv_pulse_cntrs => c_mask_pulse_cntrs c_slv_pulse_cntrs => c_mask_pulse_cntrs
); );
-- Delay, pulse width and frequency constants for the pulse_gen_gp component -- Delay, pulse width and period constants for the pulse_gen_gp component
constant c_del_ch_1_4 : std_logic_vector(31 downto 0) := x"00000000"; constant c_del_ch_1_4 : std_logic_vector(31 downto 0) := x"00000000";
constant c_del_ch_2_5 : std_logic_vector(31 downto 0) := x"001e8480"; constant c_del_ch_2_5 : std_logic_vector(31 downto 0) := x"001e8480";
constant c_del_ch_3_6 : std_logic_vector(31 downto 0) := x"003d0900"; constant c_del_ch_3_6 : std_logic_vector(31 downto 0) := x"003d0900";
constant c_pw : std_logic_vector(31 downto 0) := x"00000018"; constant c_pw : std_logic_vector(31 downto 0) := x"00000018";
constant c_freq : std_logic_vector(31 downto 0) := x"001e8480"; constant c_per : std_logic_vector(31 downto 0) := x"001e8480";
--============================================================================ --============================================================================
-- Component declarations -- Component declarations
...@@ -286,10 +285,10 @@ architecture behav of pts_conv_ttl_blo_rtm is ...@@ -286,10 +285,10 @@ architecture behav of pts_conv_ttl_blo_rtm is
-- Active high enable signal -- Active high enable signal
en_i : in std_logic; en_i : in std_logic;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles -- Delay, pulse width and period inputs, in number of clk_i cycles
delay_i : in std_logic_vector(31 downto 0); delay_i : in std_logic_vector(31 downto 0);
pwidth_i : in std_logic_vector(31 downto 0); pwidth_i : in std_logic_vector(31 downto 0);
freq_i : in std_logic_vector(31 downto 0); per_i : in std_logic_vector(31 downto 0);
-- Output pulse signal -- Output pulse signal
pulse_o : out std_logic pulse_o : out std_logic
...@@ -434,7 +433,20 @@ begin ...@@ -434,7 +433,20 @@ begin
--============================================================================ --============================================================================
i2c_addr <= "10" & fpga_ga_i; i2c_addr <= "10" & fpga_ga_i;
-- Instantiate I2C bridge component
--
-- FSM watchdog timeout timer:
-- * consider bit period of 30 us
-- * 10 bits / byte transfer => 300 us
-- * 40 bytes in one transfer => 12000 us
-- * clk_i period = 50 ns => g_fsm_wdt = 12000 us / 50 ns = 240000
-- * multiply by two for extra safety => g_fsm_wdt = 480000
-- * Time to watchdog timeout: 480000 * 50ns = 24 ms
cmp_i2c_bridge : wb_i2c_bridge cmp_i2c_bridge : wb_i2c_bridge
generic map
(
g_fsm_wdt => 480000
)
port map port map
( (
-- Clock, reset -- Clock, reset
...@@ -643,10 +655,10 @@ begin ...@@ -643,10 +655,10 @@ begin
-- Active high enable signal -- Active high enable signal
en_i => pulse_en(i), en_i => pulse_en(i),
-- Delay, pulse width and frequency inputs, in number of clk_i cycles -- Delay, pulse width and period inputs, in number of clk_i cycles
delay_i => (others => '0'), delay_i => (others => '0'),
pwidth_i => c_pw, pwidth_i => c_pw,
freq_i => c_freq, per_i => c_per,
-- Output pulse signal -- Output pulse signal
pulse_o => pout(i) pulse_o => pout(i)
...@@ -893,7 +905,7 @@ begin ...@@ -893,7 +905,7 @@ begin
-- MULTICAST 3 -- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF; bicolor_led_state(23 downto 22) <= c_LED_OFF;
cmp_bicolor_led_ctrl : bicolor_led_ctrl cmp_bicolor_led_ctrl : gc_bicolor_led_ctrl
generic map generic map
( (
g_NB_COLUMN => 6, g_NB_COLUMN => 6,
......
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