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Conv TTL Blocking - Hardware
Commit 015fb145 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Updated hardware guide

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doc/hwg/cern-title.tex
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......@@ -9,7 +9,7 @@
\noindent \rule{\textwidth}{.1cm}
\hfill October 16, 2014
\hfill January 21, 2015
\vspace*{3cm}
......
doc/hwg/hwg-conv-ttl-blo.bib
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......@@ -33,18 +33,12 @@
@misc{rtmm-sch,
title = {{RTM Motherboard Schematics}},
howpublished = {\url{https://edms.cern.ch/file/1281435/1/EDA-02452-V2-0_sch.pdf}}
howpublished = {\url{https://edms.cern.ch/file/1318265/1/EDA-02452-V3-0_sch.pdf}}
}
@misc{rtmp-sch,
title = {{RTM Piggyback Schematics}},
howpublished = {\url{https://edms.cern.ch/file/1178456/1/EDA-02453-V1-0_sch.pdf}}
}
@misc{blo-ps-datasheet,
author = {{Texas Instruments}},
title = {{TPS40210, TPS40211, 4.5~V to 52~V Input Current Mode Boost Controller}},
howpublished = {\url{http://www.ohwr.org/documents/227}}
howpublished = {\url{https://edms.cern.ch/file/1405205/1/EDA-02453-V2-0_sch.pdf}}
}
@misc{spec,
......@@ -76,13 +70,13 @@
note = {\url{http://www.avagotech.com/docs/AV02-0940EN}}
}
@misc{nxp-an11158,
@misc{an10273,
author = {{NXP Semiconductor}},
title = {{Understanding power MOSFET datasheet parameters}},
day = 7,
month = January,
year = 2013,
note = {\url{http://www.nxp.com/documents/application_note/AN11158.pdf}}
title = {{Power MOSFET single-shot/repetitive avalanche ruggedness rating}},
day = 27,
month = March,
year = 2009,
note = {\url{http://www.nxp.com/documents/application_note/AN10273.pdf}}
}
@misc{ctb-proj,
......@@ -96,3 +90,11 @@
howpublished = {\url{http://www.ohwr.org/documents/335}}
}
@misc{bsh103,
author = {{Philips Semiconductor}},
title = {{BSH103 N-channel enhancement mode MOS transistor}},
day = 11,
month = February,
year = 1998,
note = {\url{http://www.nxp.com/documents/data_sheet/BSH103.pdf}}
}
doc/hwg/hwg-conv-ttl-blo.tex
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......@@ -2,13 +2,23 @@
% Document header
%==============================================================================
\documentclass[a4paper,11pt]{article}
\usepackage[pdfborder= 0 0 0 1]{hyperref}
\usepackage{graphicx}
\usepackage{multirow}
\usepackage{amsmath}
\usepackage{color}
% Hyperrefs
\usepackage[
colorlinks = true,
linkcolor = black,
citecolor = black,
urlcolor = blue,
]{hyperref}
% Color package
\usepackage[usenames,dvipsnames,table]{xcolor}
% Appendices
\usepackage[toc,page]{appendix}
% Header and footer customization
......@@ -53,13 +63,14 @@ work, see \\
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l c p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Date}} & \multicolumn{1}{c}{\textbf{Version}} & \multicolumn{1}{c}{\textbf{Change}} \\
\hline
04-07-2013 & 0.1 & First draft \\
26-07-2013 & 0.2 & Second draft \\
16-10-2014 & 1.0 & First release, adding blocking output max. pulse width calculation and several extra information
21-01-2015 & 1.0 & First release, adding blocking output max. pulse duty cycle calculation and several extra information
about the blocking output stage \\
\hline
\end{tabular}
......@@ -71,28 +82,34 @@ work, see \\
\pdfbookmark[1]{\contentsname}{toc}
\tableofcontents
\pagebreak
\listoffigures
\listoftables
%------------------------------------------------------------------------------
% List of abbreviations
%------------------------------------------------------------------------------
\pagebreak
\section*{List of Abbreviations}
\begin{tabular}{l l}
FPGA & Field-Programmable Gate Array \\
RTM & Rear-Transition Module \\
IC & Integrated Circuit \\
I$^2$C & Inter-Integrated Circuit (bus) \\
PLL & Phase-Locked Loop \\
RTM & Rear Transition Module \\
SFP & Small-Form-factor Pluggable (transceiver) \\
TVS & Transient Voltage Suppressor (diode) \\
SVEC & Simple VME FMC Carrier \\
SPEC & Simple PCIe FMC Carrier \\
VME & Versa Module Eurocard \\
\end{tabular}
\pagebreak
\pagenumbering{arabic}
\setcounter{page}{1}
\addcontentsline{toc}{section}{List of abbreviations}
%==============================================================================
% SEC: Intro
%==============================================================================
\pagebreak
\section{Introduction}
\label{sec:intro}
......@@ -219,6 +236,7 @@ in some way from the 3.3~V, 5~V and 12~V VME power supplies.
\caption{Voltage levels on CONV-TTL-BLO}
\label{tbl:voltage-levels}
\centerline{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l p{.5\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Level}} & \multicolumn{1}{c}{\textbf{Description}} \\
......@@ -242,7 +260,7 @@ This circuit can be found in page 2 of the schematics.
Finally, the 24~V blocking power supply (schematics page 3) uses a Texas Instruments
TPS40210DGQR boost converter. The values various components around the converter were calculated
using the first design example in the datasheet of the device~\cite{blo-ps-datasheet}.
using the first design example in the datasheet of the device.
%------------------------------------------------------------------------------
% SUBSEC: Clocks
......@@ -269,6 +287,7 @@ to output dedicated 125~MHz dedicated clocks to the SFP and FPGA transceiver.
\label{tbl:clocks}
\centerline
{
\rowcolors{2}{white}{gray!25}
\begin{tabular}{l r l}
\hline
\multicolumn{1}{c}{\textbf{Clock}} & \multicolumn{1}{c}{\textbf{Frequency}} & \multicolumn{1}{c}{\textbf{Description}} \\
......@@ -476,7 +495,7 @@ the pull-up resistor.
\label{fig:blo-outp-tristate}
\end{figure}
The maximum pulse frequency that can be sustained without damaging the MOSFET
The maximum pulse duty cycle that can be sustained without damaging the MOSFET
considering nominal blocking pulse widths~\cite{blo-std} of 1.2~$\mu$s, is approximately 4160~Hz
(see Appendix~\ref{app:blo-max-freq}).
......@@ -764,8 +783,6 @@ I_{LED,RMS} = I_{LED} \sqrt{\delta}
\delta \cong 0.81
\end{equation}
\end{appendices}
%==============================================================================
% APP: Block outp stage calc
%==============================================================================
......@@ -777,7 +794,7 @@ Figure~\ref{fig:blo-outp} shows the blocking output stage, as a reference for th
calculations below.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/blo-outp}}
\centerline{\includegraphics[width=.98\textwidth]{fig/blo-outp}}
\caption{Blocking output stage}
\label{fig:blo-outp}
\end{figure}
......@@ -785,64 +802,164 @@ calculations below.
%------------------------------------------------------------------------------
% SUBSEC: max. pulse freq
%------------------------------------------------------------------------------
\subsection{Maximum blocking pulse frequency}
\subsection{Maximum blocking pulse duty cycle}
\label{app:blo-max-freq}
The maximum blocking pulse frequency is dictated by the output stage, which contains
a BSH103 transistor that has been found to be the failing component after the pulse frequency
reaches a certain threshold. The maximum pulse frequency will be calculated in this section,
considering the nominal (1.2~$\mu$s) blocking pulse widths \cite{blo-std}. All calculations
presented here are for operation starting at 25~$^\circ$C.
The maximum blocking pulse duty cycle is dictated by the output stage, which contains
a BSH103 transistor~\cite{bsh103} that has been found to be the failing component when the pulse frequency becomes too high.
The maximum duty cycle will be calculated in this section, considering the nominal (1.2~$\mu$s)
blocking pulse widths \cite{blo-std}. All calculations presented here are for operation starting at
25~$^\circ$C.
Due to the presence of the transformer in the blocking output stage, the MOSFET will enter
into avalanche mode at the falling edge of the pulse, since the current which was increasing
through the transformer primary during the pulse will still be present at the end of the pulse.
Since at the falling edge of the pulse the transistor is turned off and there is still a current
at its gate, the voltage at the transistor drain will rise sharply and the transistor will go
into avalanche mode.
NXP application note AN10273~\cite{an10273} details MOSFET avalanche rugedness and a method to
calculate whether a MOSFET will be capable to withstand repeated avalanche events at specific
frequencies. In summary, due to the fact current is still present in the circuit after transistor
turn-off, the power dissipated on the transistor leads to a rise in the transistor's temperature.
To make sure that the transistor withstands the avalanche event, one must make sure its temperature
does not rise above a threshold of 170$^\circ$C~\cite{an10273}.
The calculation presented here will follow the example in section 6 of NXP AN10273~\cite{an10273}
on the blocking output stage in Figure~\ref{fig:blo-outp}, in some way abstracting the effects the secondary
has on the primary.
To start, the avalanche current, which is the current at the end of the 1.2~$\mu$s pulse~\cite{blo-std},
can be calculated from the current rise through the RL circuit formed by the 100~$\mu$H transformer primary
and the 0.5~$\Omega$ $R_{ds(ON)}$ of the BSH103 MOSFET~\cite{bsh103},
\begin{align}
I_{AS} & = \frac{V_{BLO\_24V}}{R_{ds(ON)}}\left(1 - e^{-\frac{R_{ds(ON)}}{L}}t\right) \nonumber\\
& = \frac{27}{0.5} \left( 1 - e^{-1.2{\mu} \frac{0.5}{100{\mu}}} \right) \nonumber \\
& = 323 mA
\end{align}
To account for possible effects that the secondary might have on the primary, the value
of the avalanche current will be rounded off to,
\begin{equation}
I_{AS} = 400 mA
\end{equation}
At the end of the pulse, the voltage across the inductor will be
\begin{equation}
V_{BR} - V_{BLO\_24V} = L\frac{dI_{AS}}{dt}
\end{equation}
\noindent where $V_{BR}$ is the breakdown voltage of the MOSFET~\cite{an10273},
\begin{equation}
V_{BR} = 1.3 \times V_{DS(max.)} \nonumber \\
\end{equation}
In the case of the BSH103~\cite{bsh103},
\begin{equation}
V_{BR} = 39V \\
\end{equation}
Power MOSFETs can withstand high currents on their inputs as long as these currents
arrive as short pulses. What is important is for the MOSFET's temperature to not
increase above 175~$^\circ$C. The MOSFET temperature rise is \cite{nxp-an11158}
The time in which the avalanche current decays to zero is the avalanche time, due to the
fact that this is the time for which the voltage at the drain of the transistor will be
$V_{BR}$, and can be calculated based on the voltage across the inductor as,
\begin{equation}
T_{j(rise)max} = P_{av} * Z_{th}
dt_{AV} = \frac{L}{V_{BR} - V_{BLO\_24V}}dI_{AS}
\end{equation}
\noindent where $Z_{th}$ is the thermal impedance of the MOSFET. The thermal impedance
varies depending on duty cycle, with a maximum of 140~K/W in the case of the BSH103
present on the CONV-TTL-BLO. The thermal impedance curve based on duty cycle can be found
in the BSH103 datasheet \textcolor{red}{\textbf{cite datasheet}}.
Integrating this equation yields
\begin{align}
t_{AV} & = \frac{L}{V_{BR} - V_{BLO\_24V}}I_{AS} \nonumber \\
& = \frac{100{\mu}H}{39V - 27V} \times 400 \times 10^{-3} \nonumber \\
& = 3.33{\mu}s \label{av-time}
\end{align}
When the MOSFET is turned on, it introduces its R$_{DS(on)}$ resistance into the
circuit. Together with the transformer primary, this forms an RL circuit through which
after 1.2~$\mu$s will pass a current of
With this, the single-shot avalanche energy can be calculated based on the peak power avalanche dissipation,
which occurs at the start of the avalanche period, and the avalanche time~\cite{an10273},
\begin{align}
I_D & = \frac{V_{BLO}}{R_{DS(on)}} \left(( 1 - e^{-t\frac{R}{L}} \right) \nonumber \\
& = \frac{24}{0.5} \left( 1 - e^{-1.2{\mu} \frac{0.5}{100{\mu}}} \right) \nonumber \\
& \cong 0.3 A
E_{AS} & = \frac{P_{AV(pk)} \times t_{AV}}{2} = \frac{I_{AV} \times V_{BR} \times t_{AV}}{2} \nonumber \\
& = \frac{400mA \times 39V \times 3.33{\mu}s}{2} \nonumber \\
& = 25.97{\mu}J
\end{align}
After the same time, the voltage across the inductor will be
Once the single-shot avalanche energy is known, the repetitive avalanche power dissipation
can be calculated taking into account the pulse frequency~\cite{an10273},
\begin{equation}
P_{AV(R)} = E_{AS} \times f
\end{equation}
Knowing the repetitive avalanche event power dissipation helps in finding the
temperature rise~\cite{an10273},
\begin{equation}
{\Delta}T_j = P_{AV(R)} \times R_{th(j-amb)}
\end{equation}
\noindent where $R_{th(j-amb)}$ is the junction-to-ambient thermal resistance of the package,
140~K/W in the case of the BSH103~\cite{bsh103}.
In the case at hand, knowing that the temperature starts at 25~$^{\circ}$C and has to rise
to no more than 170~$^{\circ}$C, the temperature rise is
\begin{center}
${\Delta}T_j = 145^{\circ}C$, or ${\Delta}T_j = 145K$
\end{center}
Using these three previous equations, the maximum pulse frequency can be calculated from
\begin{align}
V_L &= V_{BLO} \times e^{-\frac{R}{L}} \nonumber \\
&= 24 \times e^{-\frac{0.5}{100{\mu}}} \nonumber \\
&= 23.85 V
f_{max} & = \frac{{\Delta}T_j}{E_{AS} \times R_{th(j-amb)}} \nonumber \\
& = \frac{145K}{25.97{\mu}J \times 140K/W} \nonumber \\
& = 39.88 kHz
\end{align}
\noindent and so, the drain-to-source voltage of the MOSFET
The minimum pulse period can be calculated from this to be
\begin{equation}
T_{p(min)} = \frac{1}{f_{max}} \cong 25{\mu}s
\end{equation}
and the maximum duty cycle
\begin{equation}
{\delta}_{max} = \frac{T_{pulse}}{T_{p(min)}} = \frac{1.2{\mu}s}{25{\mu}s} = 0.048
\end{equation}
To reach the final maximum duty cycle for the blocking pulses, the possibility
of other channels operating at high frequencies around a particular transistor
has been taken into account. Other channels operating around the transistor would
mean the board temperature would increase the starting operating temperature for
the transistor. This in turn means that the power dissipation needs to be derated.
To account for this power derating, the final maximum duty cycle is obtained as the maximum
duty cycle divided by 10,
\begin{equation}
V_{DS} = V_{BLO} - V_L = 0.15 V
{\delta}_{max, final} = \frac{{\delta}_{max}}{10} \cong 0.005
\end{equation}
With this, the power of the pulse can be calculated
This yields to the final minimum period stated in the CONV-TTL-BLO User Guide \cite{ctb-ug},
\begin{equation}
P = I_D \times V_{DS} = 0.045 W
T_{min, final} = \frac{T_{pulse}}{{\delta}_{max, final}} = \frac{1.2{\mu}s}{0.005} = 240{\mu}s
\end{equation}
In order for the MOSFET to function properly, its temperature must not be more
than 175~$^\circ$C. The temperature rise on the MOSFET is
\noindent and the maximum pulse frequency,
\noindent which in our case, starting from 25~$^\circ$C, is 150~$^\circ$C.
\begin{equation}
f_{max, final} = \frac{1}{T_{min, final}} = 4.166kHz
\end{equation}
To calculate the maximum pulse frequency, the pulse duty cycle which corresponds
%==============================================================================
\end{appendices}
%==============================================================================
%==============================================================================
......@@ -851,5 +968,6 @@ To calculate the maximum pulse frequency, the pulse duty cycle which corresponds
\pagebreak
\bibliographystyle{ieeetr}
\bibliography{hwg-conv-ttl-blo}
\addcontentsline{toc}{section}{References}
\end{document}
\ No newline at end of file
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