I2C communication test gateware
Release notes
- I2C bridge
- 1024*32-bit RAM
- Control for communication and power bicolor LEDs
Note*: There is no status register implemented in this gateware, so the gateware version cannot be read.
Binary files
Sources
- relevant folders in the master branch of the main
repository
top/regtest/
syn/regtest/
Documentation
The block diagram of this test gateware can be seen below. The RAM is accessible in read-write mode starting at address 0x00.
Theodor-Adrian Stana, Jan. 2014