Pulse repetition test gateware
Release notes
- General-purpose pulse generator on channel outputs
- one per each channel
- pulse width, frequency and delay configurable via I2C
- Counters on channel inputs and outputs
- one counter per channel input and one per channel output
- counter values can be read via I2C
- I2C bridge to control pulse generator
- Status register at address 0x04 reads gateware version 0xff
- xil-multiboot module for remote reprogramming
Binary files
- Binary files for remote reprogramming:
- Binary files with golden bitstream for direct programming into the flash:
Sources
- relevant folders in the master branch of the main
repository
modules/pulsetest/
top/pulsetest/
syn/pulsetest/
Documentation
Block diagram
The gateware for the pulse test contains the following components.
- channel logic
- pulse generator (pulse_gen_gp) with configurable pulse width, frequency and delay (via Wishbone registers)
- input counter
- output counter
- pulse LED control (not show in diagram), flashes LED when pulse is generated on the output
- one I2C bridge for translating the I2C protocol defined together with ELMA to Wishbone
- registers (see memory map)
- board ID, gateware version
- control pulse width, frequency and delay
- input and output pulse counter value readout
- sending a new bitstream and issue remote reprogramming command
- xil-multiboot module to control remote reprogramming (not shown in block diagram below for simplification)
A simplified block diagram of the logic can be seen below:
Memory map
* Address * | * Access * | * Name * | Details |
0x000 | R | ID | Returns TBLO string in ASCII (0x54424c4f) |
0x004 | R | SR | Status register, least significant 8 bits return 0xff |
0x100 | R | CH1I | Channel 1 input counter |
0x104 | R | CH1O | Channel 1 output counter |
0x108 | R | CH2I | Channel 2 input counter |
0x10C | R | CH2O | Channel 2 output counter |
0x110 | R | CH3I | Channel 3 input counter |
0x114 | R | CH3O | Channel 3 output counter |
0x118 | R | CH4I | Channel 4 input counter |
0x11C | R | CH4O | Channel 4 output counter |
0x120 | R | CH5I | Channel 5 input counter |
0x124 | R | CH5O | Channel 5 output counter |
0x128 | R | CH6I | Channel 6 input counter |
0x12C | R | CH6O | Channel 6 output counter |
0x130 | R/W | CNTRST | Counter reset, writing bit 0 to 1 resets the counters. No self-reset, must re-write bit 0 to 0 in order to reuse the counters. |
0x200 | R/W | CHEN | Channel enable ('1' - channel enabled, '0' - channel disabled) bit 0 - channel 1 bit 1 - channel 2 bit 2 - channel 3 bit 3 - channel 4 bit 4 - channel 5 bit 5 - channel 6 |
0x204 | R/W | C1D | Channel 1 delay control |
0x208 | R/W | C2D | Channel 2 delay control |
0x20C | R/W | C3D | Channel 3 delay control |
0x210 | R/W | C4D | Channel 4 delay control |
0x214 | R/W | C5D | Channel 5 delay control |
0x218 | R/W | C6D | Channel 6 delay control |
0x21C | R/W | C1PW | Channel 1 pulse width control |
0x220 | R/W | C2PW | Channel 2 pulse width control |
0x224 | R/W | C3PW | Channel 3 pulse width control |
0x228 | R/W | C4PW | Channel 4 pulse width control |
0x22C | R/W | C5PW | Channel 5 pulse width control |
0x230 | R/W | C6PW | Channel 6 pulse width control |
0x234 | R/W | C1F | Channel 1 frequency control |
0x238 | R/W | C2F | Channel 2 frequency control |
0x23C | R/W | C3F | Channel 3 frequency control |
0x240 | R/W | C4F | Channel 4 frequency control |
0x244 | R/W | C5F | Channel 5 frequency control |
0x248 | R/W | C6F | Channel 6 frequency control |
0x300 | R/W | CR | MultiBoot Control Register |
0x304 | R | SR | MultiBoot Status Register |
0x308 | R/W | GBBAR | MultiBoot Golden Bitstream Base Address Register |
0x30C | R | MBBAR | MultiBoot MultiBoot Bitstream Base Address Register |
0x310 | R | FAR | MultiBoot Flash Access Register |
Setting the frequency, pulse width and delay
Pulses are generated on the output channels based on internal counters clocked by the clock signal input to the pulse_gen_gp block. The following formulae show how to set the values of the frequency, delay and pulse width registers on a channel:
f = 1 / (freq_reg * clk_per)
freq_reg = 1 / (f * clk_per)
pw = pw_reg * clk_per
pw_reg = pw / clk_per
delay = delay_reg * clk_per
delay_reg = delay / clk_per
Notes:*
- If you want to change the value of delay registers should be set with the pulse generator disabled (the corresponding bit in the CHEN register cleared)
- For generating a single pulse, set the frequency register to a smaller value than the pulse width register
- For generating multiple pulses with the desired frequency, the value of the frequency register should be higher than that of the pulse width register
As an example, let's set up the first two channels to generate pulses based on a 125 MHz clock signal input to the pulse_gen_gp blocks:
- channel 1
- f = 100kHz
- d = 0
- pw = 1.2us
- channel 2
- f = 50kHz
- d = 1us
- pw = 1us
The setup is the following:
* channel 1 frequency
f1 = 100 kHz
c1f = 1 / (100 kHz * 8 ns)
c1f = 1250
c1f = 0x4e2
* channel 1 pulse width
pw1 = 1.2 us = 150 * 8ns
c1pw = 150
c1pw = 0x96
* channel 1 delay
c1d = 0
* channel 2 frequency
f2 = 50 kHz
c2f = 1 / (50 kHz * 8 ns)
c2f = 675
c2f = 0x271
* channel 2 pulse width
pw2 = 1 us = 125 * 8ns
c2pw = 125
c2pw = 0x7d
* channel 2 delay
d2 = 1us = 125 * 8ns
c2d = 125
c2d = 0x7d
Operating the pulse generators
For predictable operation of the pulse generators, the following sequence should be used:
- Write the delay register for the channel (CxD)
- Write the pulse width register for the channel (CxPW)
- Enable the channel (write 1 to corresponding bit in CHEN register)
- Control the frequency of pulse generation as required via the CxF register
- Disable the channel (write 0 to corresponding bit in CHEN register)
Theodor-Adrian Stana, Jan. 2014