Gateware for CONV-TTL-BLO boards
Project description
Gateware implemented in VHDL for the Xilinx Spartan-6 FPGA ensures most of the functionalities for the CONV-TTL-BLO board:
- Pulse regeneration based on input trigger for each of the six input channels
- Communication via I2C and ELMA
protocol
- Retrieve board status and gateware version
- Remote reprogramming
- Diagnostics
- Converter board ID
- Gateware version
- On-board switches and RTM lines status (RTM detection)
- Input pulse counters
- Time-tagging of last 128 input pulses
- Remote reset
- Manual pulse triggering
- System errors
- Controlling pulse and system status LEDs
Releases
Documentation
Status
Date | Event |
31-07-2013 | Separate gateware project created |
07-01-2014 | Golden gateware released |
07-01-2014 | Gateware v1.0 released |
10-03-2014 | Gateware v2.0 released |
09-04-2014 | Gateware v2.1 released |
15-04-2014 | Gateware v2.2 released |
25-04-2014 | Golden gateware v0.1 released |
Theodor-Adrian Stana, Erik van der Bij, Apr. 2014