CONV-TTL-BLO golden gateware version 0.3
Release notes
-
CHANGES IN MEMORY MAP FROM PREVIOUS VERSIONS
- Uses same conv-common-gw submodule as the one used for v4.0 and later.
- Error bits are moved from SR to a dedicated register ERR
- Added hardware version bits & changed WRPRES bit location in SR
- Added failsafe state bits to LSR
- Separate counters for TTL & blocking
- New registers:
- OSWR (Other switch)
- UIDLR & UIDHR (Thermometer UID)
- TEMPR (Board Temperature Register)
- Does not support burst mode and fixes pulse width to 1.2us with maximum 4150 Hz frequency
- Backward-compatible with v3 boards and earlier, while bringing in some additional features.
Features available in all hardware versions of the board:*
* PCB version recognition available at the FPGA as 6 bits (4 bits for the version number and 2 bits for the revision) and for diagnostics via the status register SR. For older boards (v3 and below), SR register will indicate 0, as there are no resistors to indicate the PCB version.
* One-wire thermometer no longer accessible via one-wire master, instead:
* Temperature is available in single register as 16-bit value. Temperature = 0d(TEMPR)/16.
** One-wire chip unique 64-bit ID stored in two 32-bit registers, readable from registers UIDLR and UIDHR.
- Separate pulse counters for TTL and for BLOCKING inputs, therefore two pulse counters per channel, CHxTTLPCR and CHxBLOPCR.
Binary files
- Binary files for remote reprogramming
- To create a complete bitstream (golden + release) for direct download to the flash, see here
Sources
- Golden tag v0.3 in repository, inside folder ./top/Golden/
Denia Bouhired, August 23rd, 2014