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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
Commits
f362dfd4
Commit
f362dfd4
authored
Sep 18, 2013
by
Theodor-Adrian Stana
Browse files
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improved behavior of pulse test fw
parent
8762bfef
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14 changed files
with
808 additions
and
133 deletions
+808
-133
pulse_gen_gp.vhd
hdl/pulse_gen_gp/rtl/pulse_gen_gp.vhd
+4
-4
run.do
hdl/pulse_gen_gp/sim/run.do
+13
-0
testbench.vhd
hdl/pulse_gen_gp/sim/testbench.vhd
+184
-0
transcript
hdl/pulse_gen_gp/sim/transcript
+151
-0
wave.do
hdl/pulse_gen_gp/sim/wave.do
+30
-0
Manifest.py
hdl/test_pulse/rtl/Manifest.py
+1
-0
conv_regs.vhd
hdl/test_pulse/rtl/conv_regs.vhd
+174
-0
pulse_cnt_regs.vhd
hdl/test_pulse/rtl/pulse_cnt_regs.vhd
+46
-2
pulse_cnt_regs.wb
hdl/test_pulse/rtl/pulse_cnt_regs.wb
+9
-0
Makefile
hdl/test_pulse/syn/Makefile
+1
-0
conv_ttl_blo.bit
hdl/test_pulse/syn/conv_ttl_blo.bit
+0
-0
conv_ttl_blo.gise
hdl/test_pulse/syn/conv_ttl_blo.gise
+14
-14
conv_ttl_blo.xise
hdl/test_pulse/syn/conv_ttl_blo.xise
+100
-97
conv_ttl_blo.vhd
hdl/test_pulse/top/conv_ttl_blo.vhd
+81
-16
No files found.
hdl/pulse_gen_gp/rtl/pulse_gen_gp.vhd
View file @
f362dfd4
...
...
@@ -124,12 +124,12 @@ begin
if
(
rst_n_i
=
'0'
)
or
(
en_i
=
'0'
)
then
delay_en
<=
'1'
;
delay_cnt
<=
(
others
=>
'0'
);
els
if
(
en_i
=
'1'
)
then
els
e
if
(
inp_delay
=
(
inp_delay
'range
=>
'0'
))
then
delay_en
<=
'0'
;
elsif
(
delay_en
=
'1'
)
then
delay_cnt
<=
delay_cnt
+
1
;
if
(
delay_cnt
=
inp_delay
-1
)
then
if
(
delay_cnt
=
inp_delay
)
then
delay_en
<=
'0'
;
delay_cnt
<=
(
others
=>
'0'
);
end
if
;
...
...
@@ -144,10 +144,10 @@ begin
p_gen_pulse
:
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
(
rst_n_i
=
'0'
)
then
if
(
rst_n_i
=
'0'
)
or
(
en_i
=
'0'
)
then
freq_cnt
<=
(
others
=>
'0'
);
pulse_o
<=
'0'
;
elsif
(
en_i
=
'1'
)
and
(
delay_en
=
'0'
)
then
elsif
(
delay_en
=
'0'
)
then
freq_cnt
<=
freq_cnt
+
1
;
pulse_o
<=
'0'
;
if
(
freq_cnt
<
inp_pwidth
)
then
...
...
hdl/pulse_gen_gp/sim/run.do
0 → 100644
View file @
f362dfd4
vlib work
vcom -explicit -93 "../rtl/pulse_gen_gp.vhd"
vcom -explicit -93 "testbench.vhd"
vsim -t 1ps -voptargs="+acc" -lib work work.testbench
radix -hexadecimal
#add wave *
do wave.do
run 2 ms
wave zoomfull
hdl/pulse_gen_gp/sim/testbench.vhd
0 → 100644
View file @
f362dfd4
--==============================================================================
-- CERN (BE-CO-HT)
-- Testbench
--==============================================================================
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2013-09-17
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
-- references:
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 2013-09-17 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
--==============================================================================
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
testbench
is
end
entity
testbench
;
architecture
arch
of
testbench
is
--============================================================================
-- Type declarations
--============================================================================
--============================================================================
-- Constant declarations
--============================================================================
constant
c_clk_per
:
time
:
=
8
ns
;
--============================================================================
-- Component declarations
--============================================================================
component
pulse_gen_gp
is
port
(
-- Input clock and active-low reset
clk_i
:
in
std_logic
;
rst_n_i
:
in
std_logic
;
-- Active high enable signal
en_i
:
in
std_logic
;
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i
:
in
std_logic_vector
(
31
downto
0
);
pwidth_i
:
in
std_logic_vector
(
31
downto
0
);
freq_i
:
in
std_logic_vector
(
31
downto
0
);
-- Output pulse signal
pulse_o
:
out
std_logic
);
end
component
pulse_gen_gp
;
--============================================================================
-- Signal declarations
--============================================================================
signal
clk
,
rst_n
,
en
:
std_logic
:
=
'0'
;
signal
del
,
del1
,
pw
,
f
:
std_logic_vector
(
31
downto
0
);
signal
pulse
,
pulse1
:
std_logic
;
--==============================================================================
-- architecture begin
--==============================================================================
begin
UUT
:
pulse_gen_gp
port
map
(
-- Input clock and active-low reset
clk_i
=>
clk
,
rst_n_i
=>
rst_n
,
-- Active high enable signal
en_i
=>
en
,
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i
=>
del
,
pwidth_i
=>
pw
,
freq_i
=>
f
,
-- Output pulse signal
pulse_o
=>
pulse
);
UUT1
:
pulse_gen_gp
port
map
(
-- Input clock and active-low reset
clk_i
=>
clk
,
rst_n_i
=>
rst_n
,
-- Active high enable signal
en_i
=>
en
,
-- Delay, pulse width and frequency inputs, in number of clk_i cycles
delay_i
=>
del1
,
pwidth_i
=>
pw
,
freq_i
=>
f
,
-- Output pulse signal
pulse_o
=>
pulse1
);
p_clk
:
process
is
begin
clk
<=
not
clk
;
wait
for
c_clk_per
/
2
;
end
process
p_clk
;
p_rst
:
process
is
begin
rst_n
<=
'0'
;
wait
for
120
ns
;
rst_n
<=
'1'
;
wait
;
end
process
;
p_stim
:
process
is
begin
en
<=
'0'
;
pw
<=
(
others
=>
'0'
);
del
<=
(
others
=>
'0'
);
f
<=
(
others
=>
'0'
);
wait
until
rst_n
=
'1'
;
pw
<=
x"00000096"
;
del
<=
(
others
=>
'0'
);
del1
<=
x"0000007d"
;
f
<=
x"000004e2"
;
wait
for
31
ns
;
en
<=
'1'
;
wait
for
200
us
;
f
<=
x"000009c4"
;
--en <= '0';
wait
for
100
us
;
f
<=
x"00001388"
;
--en <= '1';
wait
for
200
us
;
en
<=
'0'
;
wait
for
10
us
;
f
<=
x"000009c4"
;
en
<=
'1'
;
wait
for
100
us
;
f
<=
x"000004e2"
;
wait
for
1
us
;
en
<=
'0'
;
wait
for
100
us
;
en
<=
'1'
;
wait
for
100
us
;
en
<=
'0'
;
wait
;
end
process
p_stim
;
end
architecture
arch
;
--==============================================================================
-- architecture end
--==============================================================================
hdl/pulse_gen_gp/sim/transcript
0 → 100644
View file @
f362dfd4
# // ModelSim SE 10.1 Dec 5 2011 Linux 3.2.0-53-generic-pae
# //
# // Copyright 1991-2011 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
#
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen_gp
# -- Compiling architecture behav of pulse_gen_gp
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture arch of testbench
# ** Warning: [4] testbench.vhd(157): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(arch)#1
# Loading work.pulse_gen_gp(behav)#1
# hexadecimal
# 0 ps
# 2100 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen_gp
# -- Compiling architecture behav of pulse_gen_gp
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture arch of testbench
# ** Warning: [4] testbench.vhd(157): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(arch)#1
# Loading work.pulse_gen_gp(behav)#1
# hexadecimal
# 0 ps
# 2100 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen_gp
# -- Compiling architecture behav of pulse_gen_gp
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture arch of testbench
# ** Warning: [4] testbench.vhd(157): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(arch)#1
# Loading work.pulse_gen_gp(behav)#1
# hexadecimal
# 0 ps
# 2100 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen_gp
# -- Compiling architecture behav of pulse_gen_gp
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture arch of testbench
# ** Warning: [4] testbench.vhd(157): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(arch)#1
# Loading work.pulse_gen_gp(behav)#1
# hexadecimal
# 0 ps
# 2100 us
do run.do
# ** Warning: (vlib-34) Library already exists at "work".
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity pulse_gen_gp
# -- Compiling architecture behav of pulse_gen_gp
# Model Technology ModelSim SE vcom 10.1 Compiler 2011.12 Dec 5 2011
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity testbench
# -- Compiling architecture arch of testbench
# ** Warning: [4] testbench.vhd(157): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# vsim -lib work -voptargs=\"+acc\" -t 1ps work.testbench
# ** Note: (vsim-3813) Design is being optimized due to module recompilation...
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.numeric_std(body)
# Loading work.testbench(arch)#1
# Loading work.pulse_gen_gp(behav)#1
# hexadecimal
# 0 ps
# 2100 us
q
hdl/pulse_gen_gp/sim/wave.do
0 → 100644
View file @
f362dfd4
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/clk
add wave -noupdate /testbench/rst_n
add wave -noupdate /testbench/en
add wave -noupdate /testbench/del
add wave -noupdate /testbench/pw
add wave -noupdate /testbench/f
add wave -noupdate /testbench/pulse
add wave -noupdate /testbench/pulse1
add wave -noupdate -divider UUT
add wave -noupdate /testbench/UUT/freq_cnt
add wave -noupdate /testbench/UUT/delay_cnt
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1999669826 ps} 0} {{Cursor 2} {300152000 ps} 0}
configure wave -namecolwidth 194
configure wave -valuecolwidth 72
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {2100 us}
hdl/test_pulse/rtl/Manifest.py
View file @
f362dfd4
files
=
[
"conv_regs.vhd"
,
"pulse_cnt_regs.vhd"
,
"pgen_ctrl_regs.vhd"
]
hdl/test_pulse/rtl/conv_regs.vhd
0 → 100644
View file @
f362dfd4
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Converter board registers
---------------------------------------------------------------------------------------
-- File : conv_regs.vhd
-- Author : auto-generated by wbgen2 from conv_regs.wb
-- Created : Fri Aug 2 16:02:13 2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE conv_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
entity
conv_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i
:
in
std_logic_vector
(
15
downto
0
);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o
:
out
std_logic
;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o
:
out
std_logic
);
end
conv_regs
;
architecture
syn
of
conv_regs
is
signal
conv_regs_id_bits_int
:
std_logic_vector
(
31
downto
0
);
signal
conv_regs_cr_rst_unlock_int
:
std_logic
;
signal
conv_regs_cr_rst_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
signal
bwsel_reg
:
std_logic_vector
(
3
downto
0
);
signal
rwaddr_reg
:
std_logic_vector
(
1
downto
0
);
signal
ack_in_progress
:
std_logic
;
signal
wr_int
:
std_logic
;
signal
rd_int
:
std_logic
;
signal
allones
:
std_logic_vector
(
31
downto
0
);
signal
allzeros
:
std_logic_vector
(
31
downto
0
);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg
<=
wb_dat_i
;
bwsel_reg
<=
wb_sel_i
;
rd_int
<=
wb_cyc_i
and
(
wb_stb_i
and
(
not
wb_we_i
));
wr_int
<=
wb_cyc_i
and
(
wb_stb_i
and
wb_we_i
);
allones
<=
(
others
=>
'1'
);
allzeros
<=
(
others
=>
'0'
);
--
-- Main register bank access process.
process
(
clk_sys_i
,
rst_n_i
)
begin
if
(
rst_n_i
=
'0'
)
then
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
conv_regs_id_bits_int
<=
x"424c4f32"
;
conv_regs_cr_rst_unlock_int
<=
'0'
;
conv_regs_cr_rst_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
ack_sreg
(
9
)
<=
'0'
;
if
(
ack_in_progress
=
'1'
)
then
if
(
ack_sreg
(
0
)
=
'1'
)
then
ack_in_progress
<=
'0'
;
else
end
if
;
else
if
((
wb_cyc_i
=
'1'
)
and
(
wb_stb_i
=
'1'
))
then
case
rwaddr_reg
(
1
downto
0
)
is
when
"00"
=>
if
(
wb_we_i
=
'1'
)
then
conv_regs_id_bits_int
<=
wrdata_reg
(
31
downto
0
);
end
if
;
rddata_reg
(
31
downto
0
)
<=
conv_regs_id_bits_int
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"01"
=>
if
(
wb_we_i
=
'1'
)
then
end
if
;
rddata_reg
(
15
downto
0
)
<=
conv_regs_sr_fwvers_i
;
rddata_reg
(
23
downto
16
)
<=
conv_regs_sr_switches_i
;
rddata_reg
(
29
downto
24
)
<=
conv_regs_sr_rtm_i
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"10"
=>
if
(
wb_we_i
=
'1'
)
then
conv_regs_cr_rst_unlock_int
<=
wrdata_reg
(
0
);
conv_regs_cr_rst_int
<=
wrdata_reg
(
31
);
end
if
;
rddata_reg
(
0
)
<=
conv_regs_cr_rst_unlock_int
;
rddata_reg
(
31
)
<=
conv_regs_cr_rst_int
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
ack_sreg
(
0
)
<=
'1'
;
end
case
;
end
if
;
end
if
;
end
if
;
end
process
;
-- Drive the data output bus
wb_dat_o
<=
rddata_reg
;
-- bits
conv_regs_id_bits_o
<=
conv_regs_id_bits_int
;
-- fwvers
-- switches
-- RTM detection
-- Reset unlock bit
conv_regs_cr_rst_unlock_o
<=
conv_regs_cr_rst_unlock_int
;
-- Reset bit
conv_regs_cr_rst_o
<=
conv_regs_cr_rst_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o
<=
ack_sreg
(
0
);
end
syn
;
hdl/test_pulse/rtl/pulse_cnt_regs.vhd
View file @
f362dfd4
...
...
@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : pulse_cnt_regs.vhd
-- Author : auto-generated by wbgen2 from pulse_cnt_regs.wb
-- Created :
Fri Aug 16 10:41:12
2013
-- Created :
Mon Sep 16 18:23:47
2013
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE pulse_cnt_regs.wb
...
...
@@ -50,12 +50,15 @@ entity pulse_cnt_regs is
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i
:
in
std_logic_vector
(
31
downto
0
)
pulse_cnt_ch6o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for BIT field: 'reset' in reg: 'Counter reset'
pulse_cnt_rst_bit_o
:
out
std_logic
);
end
pulse_cnt_regs
;
architecture
syn
of
pulse_cnt_regs
is
signal
pulse_cnt_rst_bit_int
:
std_logic
;
signal
ack_sreg
:
std_logic_vector
(
9
downto
0
);
signal
rddata_reg
:
std_logic_vector
(
31
downto
0
);
signal
wrdata_reg
:
std_logic_vector
(
31
downto
0
);
...
...
@@ -83,6 +86,7 @@ begin
ack_sreg
<=
"0000000000"
;
ack_in_progress
<=
'0'
;
rddata_reg
<=
"00000000000000000000000000000000"
;
pulse_cnt_rst_bit_int
<=
'0'
;
elsif
rising_edge
(
clk_sys_i
)
then
-- advance the ACK generator shift register
ack_sreg
(
8
downto
0
)
<=
ack_sreg
(
9
downto
1
);
...
...
@@ -167,6 +171,44 @@ begin
rddata_reg
(
31
downto
0
)
<=
pulse_cnt_ch6o_val_i
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
"1100"
=>
if
(
wb_we_i
=
'1'
)
then
pulse_cnt_rst_bit_int
<=
wrdata_reg
(
0
);
end
if
;
rddata_reg
(
0
)
<=
pulse_cnt_rst_bit_int
;
rddata_reg
(
1
)
<=
'X'
;
rddata_reg
(
2
)
<=
'X'
;
rddata_reg
(
3
)
<=
'X'
;
rddata_reg
(
4
)
<=
'X'
;
rddata_reg
(
5
)
<=
'X'
;
rddata_reg
(
6
)
<=
'X'
;
rddata_reg
(
7
)
<=
'X'
;
rddata_reg
(
8
)
<=
'X'
;
rddata_reg
(
9
)
<=
'X'
;
rddata_reg
(
10
)
<=
'X'
;
rddata_reg
(
11
)
<=
'X'
;
rddata_reg
(
12
)
<=
'X'
;
rddata_reg
(
13
)
<=
'X'
;
rddata_reg
(
14
)
<=
'X'
;
rddata_reg
(
15
)
<=
'X'
;
rddata_reg
(
16
)
<=
'X'
;
rddata_reg
(
17
)
<=
'X'
;
rddata_reg
(
18
)
<=
'X'
;
rddata_reg
(
19
)
<=
'X'
;
rddata_reg
(
20
)
<=
'X'
;
rddata_reg
(
21
)
<=
'X'
;
rddata_reg
(
22
)
<=
'X'
;
rddata_reg
(
23
)
<=
'X'
;
rddata_reg
(
24
)
<=
'X'
;
rddata_reg
(
25
)
<=
'X'
;
rddata_reg
(
26
)
<=
'X'
;
rddata_reg
(
27
)
<=
'X'
;
rddata_reg
(
28
)
<=
'X'
;
rddata_reg
(
29
)
<=
'X'
;
rddata_reg
(
30
)
<=
'X'
;
rddata_reg
(
31
)
<=
'X'
;
ack_sreg
(
0
)
<=
'1'
;
ack_in_progress
<=
'1'
;
when
others
=>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress
<=
'1'
;
...
...
@@ -192,6 +234,8 @@ begin
-- number of pulses
-- number of pulses
-- number of pulses
-- reset
pulse_cnt_rst_bit_o
<=
pulse_cnt_rst_bit_int
;
rwaddr_reg
<=
wb_adr_i
;
wb_stall_o
<=
(
not
ack_sreg
(
0
))
and
(
wb_stb_i
and
wb_cyc_i
);
-- ACK signal generation. Just pass the LSB of ACK counter.
...
...
hdl/test_pulse/rtl/pulse_cnt_regs.wb
View file @
f362dfd4
...
...
@@ -154,4 +154,13 @@ peripheral {
};
};
reg {
name = "Counter reset";
prefix = "rst";
field {
name = "reset";
prefix = "bit";
type = BIT;
};
};
};
hdl/test_pulse/syn/Makefile
View file @
f362dfd4
...
...
@@ -40,6 +40,7 @@ FILES := ../top/conv_ttl_blo.ucf \
../top/conv_ttl_blo.vhd
\
../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd
\
../../bicolor_led_ctrl/bicolor_led_ctrl.vhd
\
../rtl/conv_regs.vhd
\
../rtl/pulse_cnt_regs.vhd
\
../rtl/pgen_ctrl_regs.vhd
\
../../reset_gen/rtl/reset_gen.vhd
\
...
...
hdl/test_pulse/syn/conv_ttl_blo.bit
View file @
f362dfd4
No preview for this file type
hdl/test_pulse/syn/conv_ttl_blo.gise
View file @
f362dfd4
...
...
@@ -72,35 +72,35 @@
</files>
<transforms
xmlns=
"http://www.xilinx.com/XMLSchema"
>
<transform
xil_pn:end_ts=
"137
6671447"
xil_pn:name=
"TRAN_copyInitialToXSTAbstractSynthesis"
xil_pn:start_ts=
"1376671447
"
>
<transform
xil_pn:end_ts=
"137
9409214"
xil_pn:name=
"TRAN_copyInitialToXSTAbstractSynthesis"
xil_pn:start_ts=
"1379409214
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671447"
xil_pn:name=
"TRAN_schematicsToHdl"
xil_pn:prop_ck=
"-1700432985017783241"
xil_pn:start_ts=
"1376671447
"
>
<transform
xil_pn:end_ts=
"137
9409214"
xil_pn:name=
"TRAN_schematicsToHdl"
xil_pn:prop_ck=
"-1700432985017783241"
xil_pn:start_ts=
"1379409214
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671447"
xil_pn:name=
"TRAN_regenerateCores"
xil_pn:prop_ck=
"-5050901284947628582"
xil_pn:start_ts=
"1376671447
"
>
<transform
xil_pn:end_ts=
"137
9409214"
xil_pn:name=
"TRAN_regenerateCores"
xil_pn:prop_ck=
"-5050901284947628582"
xil_pn:start_ts=
"1379409214
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671447"
xil_pn:name=
"TRAN_SubProjectAbstractToPreProxy"
xil_pn:start_ts=
"1376671447
"
>
<transform
xil_pn:end_ts=
"137
9409214"
xil_pn:name=
"TRAN_SubProjectAbstractToPreProxy"
xil_pn:start_ts=
"1379409214
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671447"
xil_pn:name=
"TRAN_xawsTohdl"
xil_pn:prop_ck=
"-2180482239361632071"
xil_pn:start_ts=
"1376671447
"
>
<transform
xil_pn:end_ts=
"137
9409214"
xil_pn:name=
"TRAN_xawsTohdl"
xil_pn:prop_ck=
"-2180482239361632071"
xil_pn:start_ts=
"1379409214
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671447"
xil_pn:name=
"TRAN_SubProjectPreToStructuralProxy"
xil_pn:prop_ck=
"-3972139311098429560"
xil_pn:start_ts=
"1376671447
"
>
<transform
xil_pn:end_ts=
"137
9409214"
xil_pn:name=
"TRAN_SubProjectPreToStructuralProxy"
xil_pn:prop_ck=
"-3972139311098429560"
xil_pn:start_ts=
"1379409214
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671447"
xil_pn:name=
"TRAN_platgen"
xil_pn:prop_ck=
"-6206634123545964380"
xil_pn:start_ts=
"1376671447
"
>
<transform
xil_pn:end_ts=
"137
9409214"
xil_pn:name=
"TRAN_platgen"
xil_pn:prop_ck=
"-6206634123545964380"
xil_pn:start_ts=
"1379409214
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671470"
xil_pn:in_ck=
"1634203216251964596"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"8267614965335338665"
xil_pn:start_ts=
"1376671447
"
>
<transform
xil_pn:end_ts=
"137
9409237"
xil_pn:in_ck=
"946591740309691062"
xil_pn:name=
"TRANEXT_xstsynthesize_spartan6"
xil_pn:prop_ck=
"8267614965335338665"
xil_pn:start_ts=
"1379409214
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"WarningsGenerated"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
...
...
@@ -118,11 +118,11 @@
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
<outfile
xil_pn:name=
"xst"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671470"
xil_pn:in_ck=
"3498961748663175870"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"-3953035127305197084"
xil_pn:start_ts=
"1376671470
"
>
<transform
xil_pn:end_ts=
"137
9409237"
xil_pn:in_ck=
"3498961748663175870"
xil_pn:name=
"TRAN_compileBCD2"
xil_pn:prop_ck=
"-3953035127305197084"
xil_pn:start_ts=
"1379409237
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671480"
xil_pn:in_ck=
"4600148398000832553"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"-7879307074684351365"
xil_pn:start_ts=
"1376671470
"
>
<transform
xil_pn:end_ts=
"137
9409247"
xil_pn:in_ck=
"4600148398000832553"
xil_pn:name=
"TRANEXT_ngdbuild_FPGA"
xil_pn:prop_ck=
"-7879307074684351365"
xil_pn:start_ts=
"1379409237
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_ngo"
/>
...
...
@@ -131,7 +131,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo.ngd"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_ngdbuild.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671548"
xil_pn:in_ck=
"4600148398000832554"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1376671480
"
>
<transform
xil_pn:end_ts=
"137
9409344"
xil_pn:in_ck=
"4600148398000832554"
xil_pn:name=
"TRANEXT_map_spartan6"
xil_pn:prop_ck=
"2503688751298223818"
xil_pn:start_ts=
"1379409247
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/map.xmsgs"
/>
...
...
@@ -144,7 +144,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo_summary.xml"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_usage.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671618"
xil_pn:in_ck=
"-9057307156948659133"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1376671548
"
>
<transform
xil_pn:end_ts=
"137
9409414"
xil_pn:in_ck=
"-9057307156948659133"
xil_pn:name=
"TRANEXT_par_spartan6"
xil_pn:prop_ck=
"3214117756270688487"
xil_pn:start_ts=
"1379409344
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/par.xmsgs"
/>
...
...
@@ -158,7 +158,7 @@
<outfile
xil_pn:name=
"conv_ttl_blo_pad.txt"
/>
<outfile
xil_pn:name=
"conv_ttl_blo_par.xrpt"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671658"
xil_pn:in_ck=
"-336926714118358808"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"396117104113915555"
xil_pn:start_ts=
"1376671618
"
>
<transform
xil_pn:end_ts=
"137
9409454"
xil_pn:in_ck=
"-336926714118358808"
xil_pn:name=
"TRANEXT_bitFile_spartan6"
xil_pn:prop_ck=
"396117104113915555"
xil_pn:start_ts=
"1379409414
"
>
<status
xil_pn:value=
"SuccessfullyRun"
/>
<status
xil_pn:value=
"ReadyToRun"
/>
<outfile
xil_pn:name=
"_xmsgs/bitgen.xmsgs"
/>
...
...
@@ -169,7 +169,7 @@
<outfile
xil_pn:name=
"webtalk.log"
/>
<outfile
xil_pn:name=
"webtalk_pn.xml"
/>
</transform>
<transform
xil_pn:end_ts=
"137
6671618"
xil_pn:in_ck=
"4600148398000832422"
xil_pn:name=
"TRAN_postRouteTrce"
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...
...
hdl/test_pulse/syn/conv_ttl_blo.xise
View file @
f362dfd4
...
...
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"../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/x
wb_xilinx_fpga_loader
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"93"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_
wb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_
registers_pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"94"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wb_
clock_crossing/xwb_clock_crossing
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wb_
xilinx_fpga_loader/xloader_wb
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"95"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wb_
dma/xwb_dma
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wb_
clock_crossing/xwb_clock_crossing
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"96"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wb
gen2/wbgen2_dpssram
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wb
_dma/xwb_dma
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"97"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_
eic
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_
dpssram
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"98"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_
fifo_asyn
c.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_
ei
c.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"99"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_
a
sync.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"100"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_
pkg
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_
fifo_sync
.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"101"
/>
</file>
<file
xil_pn:name=
"../../../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd"
xil_pn:type=
"FILE_VHDL"
>
<association
xil_pn:name=
"Implementation"
xil_pn:seqID=
"102"
/>
</file>
</files>
<bindings/>
...
...
hdl/test_pulse/top/conv_ttl_blo.vhd
View file @
f362dfd4
...
...
@@ -118,9 +118,12 @@ architecture behav of conv_ttl_blo is
--============================================================================
-- Constant declarations
--============================================================================
-- Firmware version
constant
c_fwvers
:
std_logic_vector
(
15
downto
0
)
:
=
x"9999"
;
-- Number of Wishbone masters and slaves, for wb_crossbar
constant
c_nr_masters
:
natural
:
=
1
;
constant
c_nr_slaves
:
natural
:
=
2
;
constant
c_nr_slaves
:
natural
:
=
3
;
-----------------------------------------
-- Memory map
...
...
@@ -130,33 +133,38 @@ architecture behav of conv_ttl_blo is
-- MEM [000-FFF]
-----------------------------------------
-- slave order definitions
constant
c_slv_
pgen_ctrl
:
natural
:
=
0
;
constant
c_slv_
conv_regs
:
natural
:
=
0
;
constant
c_slv_pulse_cnt
:
natural
:
=
1
;
constant
c_slv_pgen_ctrl
:
natural
:
=
2
;
-- constant c_slv_mem : natural := 2;
-- base address definitions
constant
c_addr_pgen_ctrl
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_addr_pulse_cnt
:
t_wishbone_address
:
=
x"00000080"
;
constant
c_addr_conv_regs
:
t_wishbone_address
:
=
x"00000000"
;
constant
c_addr_pulse_cnt
:
t_wishbone_address
:
=
x"00000100"
;
constant
c_addr_pgen_ctrl
:
t_wishbone_address
:
=
x"00000200"
;
-- constant c_addr_mem : t_wishbone_address := x"00000100";
-- address mask definitions
constant
c_mask_pgen_ctrl
:
t_wishbone_address
:
=
x"00000F80"
;
constant
c_mask_pulse_cnt
:
t_wishbone_address
:
=
x"00000F80"
;
constant
c_mask_conv_regs
:
t_wishbone_address
:
=
x"00000F00"
;
constant
c_mask_pulse_cnt
:
t_wishbone_address
:
=
x"00000F00"
;
constant
c_mask_pgen_ctrl
:
t_wishbone_address
:
=
x"00000F00"
;
-- constant c_mask_mem : t_wishbone_address := x"00000F00";
-- addresses constant for Wishbone crossbar
constant
c_addresses
:
t_wishbone_address_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_pgen_ctrl
=>
c_addr_pgen_ctrl
,
c_slv_pulse_cnt
=>
c_addr_pulse_cnt
c_slv_conv_regs
=>
c_addr_conv_regs
,
c_slv_pulse_cnt
=>
c_addr_pulse_cnt
,
c_slv_pgen_ctrl
=>
c_addr_pgen_ctrl
-- c_slv_mem => c_addr_mem
);
-- masks constant for Wishbone crossbar
constant
c_masks
:
t_wishbone_address_array
(
c_nr_slaves
-1
downto
0
)
:
=
(
c_slv_pgen_ctrl
=>
c_mask_pgen_ctrl
,
c_slv_pulse_cnt
=>
c_mask_pulse_cnt
c_slv_conv_regs
=>
c_mask_conv_regs
,
c_slv_pulse_cnt
=>
c_mask_pulse_cnt
,
c_slv_pgen_ctrl
=>
c_mask_pgen_ctrl
--c_slv_mem => c_mask_mem
);
...
...
@@ -215,6 +223,36 @@ architecture behav of conv_ttl_blo is
);
end
component
vbcp_wb
;
-- Converter registers
-- (use: ID, firmware version)
component
conv_regs
is
port
(
rst_n_i
:
in
std_logic
;
clk_sys_i
:
in
std_logic
;
wb_adr_i
:
in
std_logic_vector
(
1
downto
0
);
wb_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_cyc_i
:
in
std_logic
;
wb_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_stb_i
:
in
std_logic
;
wb_we_i
:
in
std_logic
;
wb_ack_o
:
out
std_logic
;
wb_stall_o
:
out
std_logic
;
-- Port for std_logic_vector field: 'bits' in reg: 'Board ID register'
conv_regs_id_bits_o
:
out
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'fwvers' in reg: 'Status register'
conv_regs_sr_fwvers_i
:
in
std_logic_vector
(
15
downto
0
);
-- Port for std_logic_vector field: 'switches' in reg: 'Status register'
conv_regs_sr_switches_i
:
in
std_logic_vector
(
7
downto
0
);
-- Port for std_logic_vector field: 'RTM detection' in reg: 'Status register'
conv_regs_sr_rtm_i
:
in
std_logic_vector
(
5
downto
0
);
-- Port for BIT field: 'Reset unlock bit' in reg: 'Control register'
conv_regs_cr_rst_unlock_o
:
out
std_logic
;
-- Port for BIT field: 'Reset bit' in reg: 'Control register'
conv_regs_cr_rst_o
:
out
std_logic
);
end
component
conv_regs
;
-- General-purpose pulse generator component
-- (usage: generate pulses on each channel output)
component
pulse_gen_gp
is
...
...
@@ -324,7 +362,9 @@ architecture behav of conv_ttl_blo is
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 input'
pulse_cnt_ch6i_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for std_logic_vector field: 'number of pulses' in reg: 'CH6 output'
pulse_cnt_ch6o_val_i
:
in
std_logic_vector
(
31
downto
0
)
pulse_cnt_ch6o_val_i
:
in
std_logic_vector
(
31
downto
0
);
-- Port for BIT field: 'reset' in reg: 'Counter reset'
pulse_cnt_rst_bit_o
:
out
std_logic
);
end
component
pulse_cnt_regs
;
...
...
@@ -380,6 +420,7 @@ architecture behav of conv_ttl_blo is
-- Pulse generator and counter register signals
signal
cnt_in
,
cnt_out
:
t_pulse_counter
;
signal
cntrst
:
std_logic
;
signal
delay_reg
:
t_pgen_ctrl_reg
;
signal
pwidth_reg
:
t_pgen_ctrl_reg
;
signal
freq_reg
:
t_pgen_ctrl_reg
;
...
...
@@ -540,6 +581,28 @@ begin
master_o
=>
xbar_master_out
);
cmp_conv_regs
:
conv_regs
port
map
(
rst_n_i
=>
rst_n
,
clk_sys_i
=>
clk125
,
wb_adr_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
adr
(
3
downto
2
),
wb_dat_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
dat
,
wb_dat_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
dat
,
wb_cyc_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
cyc
,
wb_sel_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
sel
,
wb_stb_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
stb
,
wb_we_i
=>
xbar_master_out
(
c_slv_conv_regs
)
.
we
,
wb_ack_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
ack
,
wb_stall_o
=>
xbar_master_in
(
c_slv_conv_regs
)
.
stall
,
conv_regs_id_bits_o
=>
open
,
conv_regs_sr_fwvers_i
=>
c_fwvers
,
conv_regs_sr_switches_i
=>
(
others
=>
'0'
),
conv_regs_sr_rtm_i
=>
(
others
=>
'0'
),
conv_regs_cr_rst_unlock_o
=>
open
,
conv_regs_cr_rst_o
=>
open
);
----============================================================================
---- Instantiate single-port RAM
----============================================================================
...
...
@@ -642,7 +705,7 @@ begin
end
process
p_oe
;
fpga_oe_o
<=
oe
;
fpga_blo_oe_o
<=
'0'
;
fpga_blo_oe_o
<=
blo_oe
;
--
'0';
fpga_trig_ttl_oe_o
<=
ttl_oe
;
fpga_inv_oe_o
<=
inv_oe
;
...
...
@@ -703,7 +766,7 @@ begin
p_cnt_pulses
:
process
(
clk125
)
is
begin
if
rising_edge
(
clk125
)
then
if
(
rst_n
=
'0'
)
then
if
(
rst_n
=
'0'
)
or
(
cntrst
=
'1'
)
then
cnt_in
(
i
)
<=
(
others
=>
'0'
);
cnt_out
(
i
)
<=
(
others
=>
'0'
);
else
...
...
@@ -745,16 +808,17 @@ begin
-- Set the pulse status LED for the channel
pulse_front_led_n_o
(
i
)
<=
(
not
pulse_leds
(
i
))
when
(
ch_en
(
i
)
=
'1'
)
else
'1'
;
pulse_rear_led_n_o
(
i
)
<=
(
not
pulse_leds
(
i
))
when
(
ch_en
(
i
)
=
'1'
)
else
'1'
;
end
generate
gen_chan_logic
;
-- Pulse outputs assignment
fpga_out_ttl_o
<=
pulse
when
(
ttl_switch_n_i
=
'0'
)
else
not
pulse
;
fpga_trig_blo_o
<=
(
others
=>
'0'
);
fpga_trig_blo_o
<=
pulse
;
--
(others => '0');
-- Pulse status LED output assignments
pulse_rear_led_n_o
<=
(
others
=>
'1'
);
--
pulse_rear_led_n_o <= (others => '1');
--============================================================================
-- Pulse counter registers instantiation
...
...
@@ -784,7 +848,8 @@ begin
pulse_cnt_ch5i_val_i
=>
std_logic_vector
(
cnt_in
(
5
)),
pulse_cnt_ch5o_val_i
=>
std_logic_vector
(
cnt_out
(
5
)),
pulse_cnt_ch6i_val_i
=>
std_logic_vector
(
cnt_in
(
6
)),
pulse_cnt_ch6o_val_i
=>
std_logic_vector
(
cnt_out
(
6
))
pulse_cnt_ch6o_val_i
=>
std_logic_vector
(
cnt_out
(
6
)),
pulse_cnt_rst_bit_o
=>
cntrst
);
--============================================================================
...
...
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