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Conv TTL Blocking - Gateware
Commit d6f11be5 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Merge branch 'proposed-master'

parents fbf25571 a485a730
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Showing with 1877 additions and 91 deletions
conv-common-gw @ a381f447
Subproject commit 1fbe6c0a88be2a99efa363465e69cafed9f5c2ec
Subproject commit a381f44777f923edd813b0068742ccbcf694ea71
syn/Golden/conv_ttl_blo.xise 0 → 100644
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syn/Release/conv_ttl_blo.xise
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......@@ -115,7 +115,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -123,11 +123,11 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../ip_cores/conv-common-gw/ip_cores/general-cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
......@@ -513,7 +513,7 @@
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/wf_decr_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/top/conv_common_gw.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="36"/>
......@@ -541,10 +541,7 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="37"/>
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../ip_cores/conv-common-gw/modules/fastevent_counter.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../sim/Release/fastevent_counter_tb.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="chipscope_ila.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -649,9 +646,9 @@
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -692,7 +689,7 @@
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -779,10 +776,11 @@
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -821,8 +819,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/conv_burst_ctrl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.conv_burst_ctrl" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -833,7 +831,7 @@
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
......@@ -845,7 +843,7 @@
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.conv_burst_ctrl" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.testbench" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......
top/Golden/Manifest.py 0 → 100644
View file @ d6f11be5
files = [
"conv_ttl_blo.ucf",
"conv_ttl_blo.vhd"
]
modules = {
"local" : [
"../../ip_cores/conv-common-gw"
]
}
top/Golden/conv_ttl_blo.ucf 0 → 100644
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This diff is collapsed.
top/Golden/conv_ttl_blo.vhd 0 → 100644
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This diff is collapsed.
top/Release/conv_ttl_blo.vhd
View file @ d6f11be5
......@@ -3,15 +3,8 @@
-- Top level entity of CONV-TTL-BLO
-- http://www.ohwr.org/projects/conv-ttl-blo
--==============================================================================
-- description: RELEASE FIRMWARE
--
-- author: Theodor Stana (t.stana@cern.ch)
-- Carlos-Gil-Soriano
--
-- version: 1.0
--
-- This is the top-level file for the CONV-TTL-BLO board. It instantiates all
-- components needed in the design and generates the necessary logic for
-- pulse conversion to occur on each channel.
......@@ -21,11 +14,14 @@
--
-- dependencies:
-- general-cores repository [1]
-- conv-common-gw repository [2]
--
-- references:
-- [1] Platform-independent core collection on OHWR,
-- http://www.ohwr.org/projects/general-cores/repository
-- [2] ELMA, Access to board data using SNMP and I2C
-- [2] Converter common gateware
-- https://www.ohwr.org/projects/conv-common-gw/repository
-- [3] ELMA, Access to board data using SNMP and I2C
-- http://www.ohwr.org/documents/227
--
--==============================================================================
......@@ -41,14 +37,6 @@
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--==============================================================================
-- last changes:
-- 26-11-2013 Theodor Stana Changed file header
-- 05-08-2013 Denia Bouhired Moved processing of inv ttl signals to common gateware module
-- and added output ports for inv pulse LEDs
--==============================================================================
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
......@@ -94,18 +82,18 @@ entity conv_ttl_blo is
blo_oen_o : out std_logic;
-- Front panel channels
ttl_n_i : in std_logic_vector(5 downto 0);--
ttl_o : out std_logic_vector(5 downto 0);--
ttl_n_i : in std_logic_vector(5 downto 0);
ttl_o : out std_logic_vector(5 downto 0);
inv_n_i : in std_logic_vector(3 downto 0);
inv_o : out std_logic_vector(3 downto 0);
-- Rear panel channels
blo_i : in std_logic_vector(5 downto 0);--
blo_o : out std_logic_vector(5 downto 0);--
blo_i : in std_logic_vector(5 downto 0);
blo_o : out std_logic_vector(5 downto 0);
-- Channel leds
led_front_n_o : out std_logic_vector(5 downto 0);--
led_front_n_o : out std_logic_vector(5 downto 0);
led_front_inv_n_o : out std_logic_vector(3 downto 0);
led_rear_n_o : out std_logic_vector(5 downto 0);
......@@ -233,8 +221,6 @@ architecture arch of conv_ttl_blo is
signal led_rear : std_logic_vector(c_nr_chans-1 downto 0);
-- I2C LEDs
signal led_i2c : std_logic;
-- System error LED
......@@ -263,7 +249,8 @@ begin
-- the input to the TTL side MUX and the OR gate.
--
-- The counter is disabled if the switch is set for TTL signals, to avoid
-- unnecessary power consumption by the counter.
-- unnecessary power consumption by the counter
p_ttlbar_nosig : process(clk_20_i)
begin
if rising_edge(clk_20_i) then
......@@ -299,7 +286,7 @@ begin
inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then -- and and_reduce(ttl_n_i)='1') then
if (inhibit_cnt = 1999) then
inhibit_first_pulse <= '0';
end if;
end if;
......@@ -326,27 +313,24 @@ begin
-- Line inputs for reflection in status register
line_ttl <= not ttl_n_i;
line_invttl <= not inv_n_i;
line_blo <= blo_i;
-- Switch inputs for reflection in status register
sw_gp <= not sw_gp_n_i;
--Burst mode functionality is enabled for versions 4 and above
-- Burst mode functionality is enabled for versions 4 and above
-- when version is below 4 then disable burst functionality
burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
--**************************************************************************
--**************************************************************************
--This change code is only used as a hack for v3 boards, which are physically able to
-- support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--**************************************************************************
--**************************************************************************
--*******************************************************************************
--*******************************************************************************
-- This change code is only used as a hack for v3 boards, which are physically
-- able to support v4 functionality, but do not have built-in pcb version support
-- burst_en_n <= '0' when sw_gp_n_i(6)= '0'
-- else '1';
--*******************************************************************************
--*******************************************************************************
--============================================================================
-- Instantiate common generic gateware for converter boards
......@@ -354,8 +338,6 @@ begin
cmp_conv_common : conv_common_gw
generic map
(
g_nr_chans => 6,
g_nr_inv_chans => 4,
g_board_id => c_board_id,
......@@ -364,9 +346,9 @@ begin
g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5,
g_pgen_pperiod_cont => 4800,
-- Minimum period supported for 1.2us pulse ~ max freq 104kHz
-- Maximum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg => 191,
-- Minimum period supported for 250ns pulse ~ max freq 2MHz
-- Maximum period supported for 250ns pulse ~ max freq 2MHz
g_pgen_pperiod_sh => 9,
g_pgen_gf_len => 1,
g_temp_decre_step_lg => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125),
......@@ -429,7 +411,7 @@ begin
-- inverted channel leds
led_inv_pulse_o => led_inv_pulse,
-- I2C LED signals -- conect to a bicolor LED of choice
-- I2C LED signals -- connect to a bicolor LED of choice
-- led_i2c_o pulses four times on I2C transfer
led_i2c_o => led_i2c,
......
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