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Conv TTL Blocking - Gateware
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Conv TTL Blocking - Gateware
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89f1378b
Commit
89f1378b
authored
Jan 13, 2017
by
Denia Bouhired-Ferrag
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Small modifications to testbench file for burst control mode
parent
b7bd40e1
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burst_ctrl_tb.vhd
sim/Release/burst_ctrl_tb.vhd
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sim/Release/burst_ctrl_tb.vhd
View file @
89f1378b
...
...
@@ -168,6 +168,7 @@ architecture behav of testbench is
(
g_pwidth
=>
5
,
g_1_pulse_temp_rise
=>
x"1388"
,
--g_1_pulse_temp_rise => x"7A125",
--g_max_temp => x"00000F4240" --10^6
g_max_temp
=>
x"02540BE400"
--10^10
...
...
@@ -249,7 +250,7 @@ end process p_ran_gen;
interval
:
=
250
ns
;
end
if
;
else
interval
:
=
50
0
ns
;
interval
:
=
25
0
ns
;
end
if
;
burst_train
<=
'0'
;
wait
for
interval
;
...
...
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