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Conv TTL Blocking - Gateware
Commit 722c523e authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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I2C bridge started working, the top two bytes of sending are masked.

parent 8c7ba3fa
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.gitignore
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captures/ captures/
*.bak
hdl/IMAGES/image1/project/image1.gise
View file @ 722c523e
...@@ -22,8 +22,7 @@ ...@@ -22,8 +22,7 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="image1.xise"/> <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="image1.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"> <files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_CMD" xil_pn:name="_impact.cmd"/> <file xil_pn:fileType="FILE_LOG" xil_pn:name="_impactbatch.log"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="_impact.log"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
...@@ -31,7 +30,6 @@ ...@@ -31,7 +30,6 @@
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/> <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="i2c_slave_core.fdo"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="image1_top.bgn" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="image1_top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="image1_top.bit" xil_pn:subbranch="FPGAConfiguration"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="image1_top.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="image1_top.bld"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="image1_top.bld"/>
...@@ -66,176 +64,45 @@ ...@@ -66,176 +64,45 @@
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="image1_top_pad.txt" xil_pn:subbranch="Par"/> <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="image1_top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_par.xrpt"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_par.xrpt"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="image1_top_summary.xml"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="image1_top_summary.xml"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_CMD" xil_pn:name="image1_top_tb.fdo"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="image1_top_usage.xml"/> <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="image1_top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/> <file xil_pn:fileType="FILE_XRPT" xil_pn:name="image1_top_xst.xrpt"/>
<file xil_pn:branch="BehavioralSim" xil_pn:fileType="FILE_MODELSIM_LOG" xil_pn:name="vsim.wlf"/> <file xil_pn:fileType="FILE_CMD" xil_pn:name="ise_impact.cmd"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/> <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/> <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="work"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/> <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files> </files>
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
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<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
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<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
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<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/test/i2c_tb_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd"/>
<outfile xil_pn:name="../../../m25p32/rtl/m25p32_top.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_core.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd"/>
<outfile xil_pn:name="../../../multiboot/rtl/multiboot_top.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd"/>
<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd"/>
<outfile xil_pn:name="../rtl/image1_core.vhd"/>
<outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
<outfile xil_pn:name="../top/image1_top.vhd"/>
</transform>
<transform xil_pn:end_ts="1360832192" xil_pn:name="TRAN_xawsToSimhdl" xil_pn:prop_ck="239257099518693425" xil_pn:start_ts="1360832192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1360832192" xil_pn:name="TRAN_schematicsToHdlSim" xil_pn:prop_ck="-3020523367752079697" xil_pn:start_ts="1360832192">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="InputChanged"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd"/>
<outfile xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd"/>
<outfile xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd"/>
<outfile xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_clk_divider.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd"/>
<outfile xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd"/>
<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd"/>
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<outfile xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd"/>
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<outfile xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_core.vhd"/>
<outfile xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd"/>
<outfile xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd"/>
<outfile xil_pn:name="../rtl/image1_core.vhd"/>
<outfile xil_pn:name="../rtl/image1_led_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_pkg.vhd"/>
<outfile xil_pn:name="../rtl/image1_wrappers_pkg.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb.vhd"/>
<outfile xil_pn:name="../test/image1_top_tb_pkg.vhd"/>
<outfile xil_pn:name="../top/image1_top.vhd"/>
</transform>
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<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutputChanged"/>
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<outfile xil_pn:name="vsim.wlf"/>
<outfile xil_pn:name="work"/>
</transform> </transform>
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
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</transform> </transform>
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -253,11 +120,11 @@ ...@@ -253,11 +120,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
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<transform xil_pn:end_ts="1360858969" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1360858962"> <transform xil_pn:end_ts="1361295893" xil_pn:in_ck="-662876564851204570" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-883419811469213931" xil_pn:start_ts="1361295887">
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...@@ -267,9 +134,11 @@ ...@@ -267,9 +134,11 @@
<outfile xil_pn:name="image1_top.ngd"/> <outfile xil_pn:name="image1_top.ngd"/>
<outfile xil_pn:name="image1_top_ngdbuild.xrpt"/> <outfile xil_pn:name="image1_top_ngdbuild.xrpt"/>
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<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
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<outfile xil_pn:name="image1_top_map.map"/> <outfile xil_pn:name="image1_top_map.map"/>
...@@ -280,7 +149,7 @@ ...@@ -280,7 +149,7 @@
<outfile xil_pn:name="image1_top_summary.xml"/> <outfile xil_pn:name="image1_top_summary.xml"/>
<outfile xil_pn:name="image1_top_usage.xml"/> <outfile xil_pn:name="image1_top_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1360859028" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1360858996"> <transform xil_pn:end_ts="1361295960" xil_pn:in_ck="7206782387671427264" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="3214117756270688487" xil_pn:start_ts="1361295927">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
...@@ -295,7 +164,7 @@ ...@@ -295,7 +164,7 @@
<outfile xil_pn:name="image1_top_pad.txt"/> <outfile xil_pn:name="image1_top_pad.txt"/>
<outfile xil_pn:name="image1_top_par.xrpt"/> <outfile xil_pn:name="image1_top_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1360859047" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1360859028"> <transform xil_pn:end_ts="1361295979" xil_pn:in_ck="7803888278084704457" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="396117104113915555" xil_pn:start_ts="1361295960">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
...@@ -306,21 +175,15 @@ ...@@ -306,21 +175,15 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1360847409" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1360847409"> <transform xil_pn:end_ts="1361295980" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="4629081730735892968" xil_pn:start_ts="1361295979">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/>
<status xil_pn:value="InputChanged"/>
</transform>
<transform xil_pn:end_ts="1360855287" xil_pn:in_ck="7803888278084691603" xil_pn:name="TRAN_configureTargetDevice" xil_pn:prop_ck="8482462020707587906" xil_pn:start_ts="1360855283">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForInputs"/> <status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="InputChanged"/> <status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_impact.cmd"/> <outfile xil_pn:name="_impactbatch.log"/>
<outfile xil_pn:name="_impact.log"/> <outfile xil_pn:name="ise_impact.cmd"/>
</transform> </transform>
<transform xil_pn:end_ts="1360859028" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1360859020"> <transform xil_pn:end_ts="1361295960" xil_pn:in_ck="-662876564851204701" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1361295953">
<status xil_pn:value="FailedRun"/> <status xil_pn:value="FailedRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
......
hdl/IMAGES/image1/project/image1.xise
View file @ 722c523e
...@@ -17,75 +17,75 @@ ...@@ -17,75 +17,75 @@
<files> <files>
<file xil_pn:name="../rtl/image1_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/image1_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="28"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/> <association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file> </file>
<file xil_pn:name="../rtl/image1_led_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/image1_led_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/> <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file> </file>
<file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/image1_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/> <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file> </file>
<file xil_pn:name="../rtl/image1_wrappers_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../rtl/image1_wrappers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/> <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file> </file>
<file xil_pn:name="../top/image1_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../top/image1_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="30"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/> <association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file> </file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/> <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file> </file>
<file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../basic_trigger/rtl/basic_trigger_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="27"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/> <association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file> </file>
<file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../ctdah_lib/rtl/ctdah_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../ctdah_lib/rtl/gc_ff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../ctdah_lib/rtl/gc_debouncer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file> </file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../ctdah_lib/rtl/gc_simple_monostable.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file> </file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_bit.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file> </file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_debounce.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file> </file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file> </file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../i2c_slave_wb_master/rtl/i2c_slave_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file> </file>
<file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../ctdah_lib/rtl/gc_counter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file> </file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../m25p32/rtl/m25p32_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -93,7 +93,7 @@ ...@@ -93,7 +93,7 @@
</file> </file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../m25p32/rtl/m25p32_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/> <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file> </file>
<file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../m25p32/rtl/m25p32_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -109,7 +109,7 @@ ...@@ -109,7 +109,7 @@
</file> </file>
<file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../spi_master_multifield/rtl/spi_master_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file> </file>
<file xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../ctdah_lib/rtl/FIFO_dispatcher.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -125,7 +125,7 @@ ...@@ -125,7 +125,7 @@
</file> </file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../multiboot/rtl/multiboot_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/> <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file> </file>
<file xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../multiboot/rtl/multiboot_regs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
...@@ -137,31 +137,31 @@ ...@@ -137,31 +137,31 @@
</file> </file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/> <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file> </file>
<file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../bicolor_led_ctrl/bicolor_led_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/> <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file> </file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../rtm_detector/rtl/rtm_detector_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/> <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file> </file>
<file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../rtm_detector/rtl/rtm_detector.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/> <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/> <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file> </file>
<file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="../test/image1_top_tb_pkg.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../test/image1_top_tb_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="31"/>
...@@ -170,7 +170,7 @@ ...@@ -170,7 +170,7 @@
<file xil_pn:name="../test/image1_top_tb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../test/image1_top_tb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="33"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="39"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="39"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="39"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="39"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="39"/>
</file> </file>
<file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../i2c_slave_wb_master/test/i2c_master_driver.vhd" xil_pn:type="FILE_VHDL">
...@@ -186,7 +186,7 @@ ...@@ -186,7 +186,7 @@
</file> </file>
<file xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="../../../test_trigleds_wb/test_trigleds_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file> </file>
</files> </files>
...@@ -302,7 +302,7 @@ ...@@ -302,7 +302,7 @@
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/> <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/> <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="i2c_driver" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -321,10 +321,10 @@ ...@@ -321,10 +321,10 @@
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/> <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Keep Hierarchy" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Language" xil_pn:value="All" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/> <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/> <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
...@@ -343,8 +343,8 @@ ...@@ -343,8 +343,8 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/> <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="i2c_driver" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="" xil_pn:valueState="non-default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
...@@ -398,14 +398,14 @@ ...@@ -398,14 +398,14 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="image1_top_map.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="image1_top_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="image1_top_timesim.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="image1_top_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="image1_top_synthesis.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="image1_top_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="image1_top_translate.vhd" xil_pn:valueState="default"/> <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="image1_top_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Process window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
...@@ -424,7 +424,7 @@ ...@@ -424,7 +424,7 @@
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="image1_top" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
...@@ -445,39 +445,39 @@ ...@@ -445,39 +445,39 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/uut/inst_image1_core/inst_bicolor_led_ctrl" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/image1_top_tb/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.bicolor_led_ctrl" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="i2c_driver" xil_pn:valueState="non-default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/> <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1ns" xil_pn:valueState="non-default"/> <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1ns" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/> <property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.bicolor_led_ctrl" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.i2c_slave_core" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="work.image1_top_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/> <property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE Mixed" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
...@@ -528,6 +528,7 @@ ...@@ -528,6 +528,7 @@
<property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="impact.ipf" xil_pn:valueState="non-default"/>
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
...@@ -537,7 +538,7 @@ ...@@ -537,7 +538,7 @@
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|image1_top_tb|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
......
hdl/IMAGES/image1/rtl/image1_core.vhd
View file @ 722c523e
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
-- unit name: image1_core.vhd -- unit name: image1_core.vhd
-- --
-- author: Carlos Gil Soriano (gilsoriano@gmail.com) -- author: Carlos Gil Soriano (gilsoriano@gmail.com)
-- Theodor-Adrian Stana (t.stana@cern.ch)
-- --
-- date: 01-12-2012 -- date: 01-12-2012
-- --
...@@ -143,6 +144,12 @@ architecture Behavioral of image1_core is ...@@ -143,6 +144,12 @@ architecture Behavioral of image1_core is
signal s_leds_array_image1 : t_leds_array; signal s_leds_array_image1 : t_leds_array;
signal s_led_state_array : t_led_state_array( signal s_led_state_array : t_led_state_array(
c_NB_ARRAY_LEDS - 1 downto 0); c_NB_ARRAY_LEDS - 1 downto 0);
signal i2c_rd_done : std_logic;
signal i2c_wr_done : std_logic;
signal i2c_up : std_logic;
-- --
-- --
...@@ -152,7 +159,9 @@ architecture Behavioral of image1_core is ...@@ -152,7 +159,9 @@ architecture Behavioral of image1_core is
-- --
signal trigleds : std_logic_vector(5 downto 0); signal trigleds : std_logic_vector(5 downto 0);
signal leds_from_trig : std_logic_vector(5 downto 0); signal leds_from_trig : std_logic_vector(5 downto 0);
signal sda_dummy : std_logic;
signal sda_dummy_n : std_logic;
-- signal s_check_cfg : BOOLEAN; -- signal s_check_cfg : BOOLEAN;
begin begin
...@@ -176,12 +185,12 @@ begin ...@@ -176,12 +185,12 @@ begin
BANDWIDTH => "OPTIMIZED", BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT", CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS", COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => c_CLKFBOUT_MULT, DIVCLK_DIVIDE => 1, CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000, CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => c_CLKOUTA_DIVIDE, CLKOUT0_PHASE => 0.000, CLKOUT0_DIVIDE => 20, CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => c_CLKOUTB_DIVIDE, CLKOUT1_PHASE => 0.000, CLKOUT1_DIVIDE => 5, CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500, CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => c_CLKIN_PERIOD, CLKIN_PERIOD => c_CLKIN_PERIOD,
REF_JITTER => 0.010) REF_JITTER => 0.010)
port map ( port map (
...@@ -265,8 +274,8 @@ begin ...@@ -265,8 +274,8 @@ begin
-- !!!!! -- !!!!!
led_front_n <= "111000"; -- led_front_n <= "111000";
-- led_front_n <= not trigleds; led_front_n <= not trigleds;
...@@ -299,7 +308,7 @@ begin ...@@ -299,7 +308,7 @@ begin
led_o_rear => led_rear_n, led_o_rear => open, --led_rear_n,
inv_i => inv_i_n, inv_i => inv_i_n,
inv_o => inv_o); inv_o => inv_o);
...@@ -324,45 +333,61 @@ begin ...@@ -324,45 +333,61 @@ begin
-- s_slave_i(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0'); s_slave_i(c_MASTER_I2C_SLAVE).adr(31 downto 16) <= (others => '0');
-- i2c_slave_o.sda_o <= sda_dummy;
-- inst_i2c_slave: i2c_slave_top sda_dummy_n <= not sda_dummy;
-- port map(sda_oen => i2c_slave_o.SDA_OE, led_rear_n <= (others => sda_dummy_n);
-- sda_i => i2c_slave_i.SDA_I, inst_i2c_slave: i2c_slave_top
-- sda_o => i2c_slave_o.SDA_O, port map(sda_oen => i2c_slave_o.SDA_OE,
-- scl_oen => i2c_slave_o.SCL_OE, sda_i => i2c_slave_i.SDA_I,
-- scl_i => i2c_slave_i.SCL_I, sda_o => sda_dummy, -- i2c_slave_o.SDA_O,
-- scl_o => i2c_slave_o.SCL_O, scl_oen => i2c_slave_o.SCL_OE,
-- wb_clk_i => s_clk.SYS_A, scl_i => i2c_slave_i.SCL_I,
-- wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1), scl_o => i2c_slave_o.SCL_O,
-- wb_master_stb_o => s_slave_i(c_MASTER_I2C_SLAVE).stb, wb_clk_i => s_clk.SYS_A,
-- wb_master_cyc_o => s_slave_i(c_MASTER_I2C_SLAVE).cyc, wb_rst_i => s_rst.SYS_A(c_RST_A_CLKS - 1),
-- wb_master_sel_o => s_slave_i(c_MASTER_I2C_SLAVE).sel, wb_master_stb_o => s_slave_i(c_MASTER_I2C_SLAVE).stb,
-- wb_master_we_o => s_slave_i(c_MASTER_I2C_SLAVE).we, wb_master_cyc_o => s_slave_i(c_MASTER_I2C_SLAVE).cyc,
-- wb_master_data_i => s_slave_o(c_MASTER_I2C_SLAVE).dat, wb_master_sel_o => s_slave_i(c_MASTER_I2C_SLAVE).sel,
-- wb_master_data_o => s_slave_i(c_MASTER_I2C_SLAVE).dat, wb_master_we_o => s_slave_i(c_MASTER_I2C_SLAVE).we,
-- wb_master_addr_o => s_slave_i(c_MASTER_I2C_SLAVE).adr(15 downto 0), wb_master_data_i => s_slave_o(c_MASTER_I2C_SLAVE).dat,
-- wb_master_ack_i => s_slave_o(c_MASTER_I2C_SLAVE).ack, wb_master_data_o => s_slave_i(c_MASTER_I2C_SLAVE).dat,
-- wb_master_rty_i => s_slave_o(c_MASTER_I2C_SLAVE).rty, wb_master_addr_o => s_slave_i(c_MASTER_I2C_SLAVE).adr(15 downto 0),
-- wb_master_err_i => s_slave_o(c_MASTER_I2C_SLAVE).err, wb_master_ack_i => s_slave_o(c_MASTER_I2C_SLAVE).ack,
-- wb_slave_stb_i => s_master_o(c_SLAVE_I2C_SLAVE).stb, wb_master_rty_i => s_slave_o(c_MASTER_I2C_SLAVE).rty,
-- wb_slave_cyc_i => s_master_o(c_SLAVE_I2C_SLAVE).cyc, wb_master_err_i => s_slave_o(c_MASTER_I2C_SLAVE).err,
-- wb_slave_sel_i => s_master_o(c_SLAVE_I2C_SLAVE).sel, wb_slave_stb_i => s_master_o(c_SLAVE_I2C_SLAVE).stb,
-- wb_slave_we_i => s_master_o(c_SLAVE_I2C_SLAVE).we, wb_slave_cyc_i => s_master_o(c_SLAVE_I2C_SLAVE).cyc,
-- wb_slave_data_i => s_master_o(c_SLAVE_I2C_SLAVE).dat, wb_slave_sel_i => s_master_o(c_SLAVE_I2C_SLAVE).sel,
-- wb_slave_data_o => s_master_i(c_SLAVE_I2C_SLAVE).dat, wb_slave_we_i => s_master_o(c_SLAVE_I2C_SLAVE).we,
-- wb_slave_addr_i => s_master_o(c_SLAVE_I2C_SLAVE).adr( 5 downto 2), wb_slave_data_i => s_master_o(c_SLAVE_I2C_SLAVE).dat,
-- wb_slave_ack_o => s_master_i(c_SLAVE_I2C_SLAVE).ack, wb_slave_data_o => s_master_i(c_SLAVE_I2C_SLAVE).dat,
-- wb_slave_rty_o => s_master_i(c_SLAVE_I2C_SLAVE).rty, wb_slave_addr_i => s_master_o(c_SLAVE_I2C_SLAVE).adr( 5 downto 2),
-- wb_slave_err_o => s_master_i(c_SLAVE_I2C_SLAVE).err, wb_slave_ack_o => s_master_i(c_SLAVE_I2C_SLAVE).ack,
-- pf_wb_addr_o => open, wb_slave_rty_o => s_master_i(c_SLAVE_I2C_SLAVE).rty,
-- rd_done_o => open, wb_slave_err_o => s_master_i(c_SLAVE_I2C_SLAVE).err,
-- wr_done_o => open, pf_wb_addr_o => open,
-- i2c_addr_i => s_i2c_addr rd_done_o => i2c_rd_done,
-- ); wr_done_o => i2c_wr_done,
i2c_addr_i => s_i2c_addr
);
-- Process to set the I2C_UP signal for display on the front panel
-- of the front module. The I2C_UP signal is permanently set once an
-- I2C transfer has successfully completed, as signaled by the RD_DONE
-- and WR_DONE outputs of the I2C slave.
p_i2c_up: process (s_clk.sys_a) is
begin
if rising_edge(s_clk.sys_a) then
if (s_rst_n = '0') then
i2c_up <= '0';
elsif (i2c_rd_done = '1') or (i2c_wr_done = '1') then
i2c_up <= '1';
end if;
end if;
end process p_i2c_up;
...@@ -409,47 +434,47 @@ begin ...@@ -409,47 +434,47 @@ begin
-- s_master_i(c_SLAVE_I2C_SLAVE).stall <= '0'; s_master_i(c_SLAVE_I2C_SLAVE).stall <= '0';
-- s_master_i(c_SLAVE_I2C_SLAVE).int <= '0'; s_master_i(c_SLAVE_I2C_SLAVE).int <= '0';
-- s_master_i(c_slave_trigleds_wb).int <= '0'; s_master_i(c_slave_trigleds_wb).int <= '0';
--
--
---- s_master_i(c_SLAVE_M25P32).stall <= '0'; -- s_master_i(c_SLAVE_M25P32).stall <= '0';
---- s_master_i(c_SLAVE_M25P32).int <= '0'; -- s_master_i(c_SLAVE_M25P32).int <= '0';
---- s_master_i(c_SLAVE_MULTIBOOT).stall <= '0'; -- s_master_i(c_SLAVE_MULTIBOOT).stall <= '0';
---- s_master_i(c_SLAVE_MULTIBOOT).int <= '0'; -- s_master_i(c_SLAVE_MULTIBOOT).int <= '0';
--
-- inst_wb_crossbar: xwb_crossbar inst_wb_crossbar: xwb_crossbar
-- generic map(g_num_masters => c_NUM_MASTERS, generic map(g_num_masters => c_NUM_MASTERS,
-- g_num_slaves => c_NUM_SLAVES, g_num_slaves => c_NUM_SLAVES,
-- g_registered => false, g_registered => false,
-- -- Address of the slaves connected -- Address of the slaves connected
-- --! It should be noted that the default address length is 32 --! It should be noted that the default address length is 32
-- --! In our project only 16 bits are addressable --! In our project only 16 bits are addressable
-- g_address => c_addresses, g_address => c_addresses,
-- g_mask => c_masks) g_mask => c_masks)
-- port map(clk_sys_i => s_clk.SYS_A, port map(clk_sys_i => s_clk.SYS_A,
-- rst_n_i => s_rst_n, rst_n_i => s_rst_n,
-- slave_i => s_slave_i , slave_i => s_slave_i ,
-- slave_o => s_slave_o , slave_o => s_slave_o ,
-- master_i => s_master_i, master_i => s_master_i,
-- master_o => s_master_o); master_o => s_master_o);
--
-- cmp_test_trigleds: test_trigleds_wb cmp_test_trigleds: test_trigleds_wb
-- port map ( port map (
-- rst_n_i => s_rst_n, rst_n_i => s_rst_n,
-- clk_sys_i => s_clk.sys_a, clk_sys_i => s_clk.sys_a,
-- wb_dat_i => s_master_o(c_slave_trigleds_wb).dat, wb_dat_i => s_master_o(c_slave_trigleds_wb).dat,
-- wb_dat_o => s_master_i(c_slave_trigleds_wb).dat, wb_dat_o => s_master_i(c_slave_trigleds_wb).dat,
-- wb_cyc_i => s_master_o(c_slave_trigleds_wb).cyc, wb_cyc_i => s_master_o(c_slave_trigleds_wb).cyc,
-- wb_sel_i => s_master_o(c_slave_trigleds_wb).sel, wb_sel_i => s_master_o(c_slave_trigleds_wb).sel,
-- wb_stb_i => s_master_o(c_slave_trigleds_wb).stb, wb_stb_i => s_master_o(c_slave_trigleds_wb).stb,
-- wb_we_i => s_master_o(c_slave_trigleds_wb).we, wb_we_i => s_master_o(c_slave_trigleds_wb).we,
-- wb_ack_o => s_master_i(c_slave_trigleds_wb).ack, wb_ack_o => s_master_i(c_slave_trigleds_wb).ack,
-- wb_stall_o => s_master_i(c_slave_trigleds_wb).stall, wb_stall_o => s_master_i(c_slave_trigleds_wb).stall,
-- -- Port for std_logic_vector field: 'Bits' in reg: 'LED' -- Port for std_logic_vector field: 'Bits' in reg: 'LED'
-- trigleds_reg_bits_o => trigleds trigleds_reg_bits_o => trigleds
-- ); );
...@@ -471,7 +496,7 @@ begin ...@@ -471,7 +496,7 @@ begin
when s_leds_array_image1.top.TTL_N = '1' when s_leds_array_image1.top.TTL_N = '1'
else f_LED_STATE(c_LED_OFF); else f_LED_STATE(c_LED_OFF);
s_led_state_array(c_LED_NB_I2C) <= f_LED_STATE(c_LED_COLOR_I2C) s_led_state_array(c_LED_NB_I2C) <= f_LED_STATE(c_LED_COLOR_I2C)
when s_leds_array_image1.top.I2C = '1' when i2c_up = '1'
else f_LED_STATE(c_LED_RED); else f_LED_STATE(c_LED_RED);
s_led_state_array(c_LED_NB_WR_OK) <= f_LED_STATE(c_LED_COLOR_WR_OK) s_led_state_array(c_LED_NB_WR_OK) <= f_LED_STATE(c_LED_COLOR_WR_OK)
when s_leds_array_image1.middle.WR_OK = '1' when s_leds_array_image1.middle.WR_OK = '1'
......
hdl/IMAGES/image1/test/image1_top_tb.vhd
View file @ 722c523e
library IEEE; library IEEE;
library work;
library modelsim_lib; library modelsim_lib;
use modelsim_lib.util.ALL; use modelsim_lib.util.ALL;
use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALl; use IEEE.NUMERIC_STD.ALl;
use std.textio.ALL; use std.textio.ALL;
...@@ -24,6 +22,7 @@ architecture behavior of image1_top_tb is ...@@ -24,6 +22,7 @@ architecture behavior of image1_top_tb is
constant c_CLK20M : TIME := 50 ns; constant c_CLK20M : TIME := 50 ns;
constant c_wb_clk_per : time := 20 ns;
--! ======================================================================== --! ========================================================================
--! Signals for the image1_top module --! Signals for the image1_top module
--! ======================================================================== --! ========================================================================
...@@ -75,7 +74,7 @@ architecture behavior of image1_top_tb is ...@@ -75,7 +74,7 @@ architecture behavior of image1_top_tb is
:= c_I2C_master_driver_ctrl_default; := c_I2C_master_driver_ctrl_default;
signal s_I2C_driver_ctrl_done : I2C_master_driver_ctrl; signal s_I2C_driver_ctrl_done : I2C_master_driver_ctrl;
signal wb_clk : STD_LOGIC; signal wb_clk : STD_LOGIC := '0';
signal s_rst_SYS_A : STD_LOGIC_VECTOR(c_RST_A_CLKS - 1 downto 0); signal s_rst_SYS_A : STD_LOGIC_VECTOR(c_RST_A_CLKS - 1 downto 0);
signal s_rst : STD_LOGIC; signal s_rst : STD_LOGIC;
...@@ -91,6 +90,9 @@ architecture behavior of image1_top_tb is ...@@ -91,6 +90,9 @@ architecture behavior of image1_top_tb is
signal s_test : STD_LOGIC; signal s_test : STD_LOGIC;
signal tb_state : t_tb_state; signal tb_state : t_tb_state;
signal gsr : std_logic;
begin begin
s_MULTIBOOT_regs_slv <= f_STD_LOGIC_VECTOR(s_MULTIBOOT_regs); s_MULTIBOOT_regs_slv <= f_STD_LOGIC_VECTOR(s_MULTIBOOT_regs);
...@@ -122,46 +124,69 @@ begin ...@@ -122,46 +124,69 @@ begin
wait for c_PLL_IN_PERIOD/2; wait for c_PLL_IN_PERIOD/2;
end process; end process;
p_gsr: process
--! @brief Process to bypass internal signals requiered for correct
--! use of i2c_master_driver
p_sig_spy : process is
begin begin
init_signal_spy("/uut/s_clk_125MHz", "s_test", 1); gsr <= '1';
init_signal_spy("/uut/inst_image1_core/s_clk.SYS_A", "wb_clk", 1); wait for 200 ns;
init_signal_spy("/uut/inst_image1_core/s_rst.SYS_A", "s_rst_SYS_A", 1); gsr <= '0';
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_regs/s_CTR0", wait;
"s_I2C_regs.CTR0", 1); end process p_gsr;
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_regs/s_LT",
"s_I2C_regs.LT", 1); p_rst: process
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRXA_slv", begin
"s_I2C_regs.DRXA", 1); s_rst_n <= '0';
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRXB_slv", wait until gsr = '0';
"s_I2C_regs.DRXB", 1); wait for 5 us;
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_regs/s_DTX", s_rst_n <= '1';
"s_I2C_regs.DTX", 1); wait;
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_CTR0", end process p_rst;
"s_MULTIBOOT_regs.CTR0", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_CTR1", p_wbclk: process
"s_MULTIBOOT_regs.CTR1", 1); begin
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_STAT", wb_clk <= not wb_clk;
"s_MULTIBOOT_regs.STAT", 1); wait for c_wb_clk_per;
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA", end process p_wbclk;
"s_MULTIBOOT_regs.MBA", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_GBA",
"s_MULTIBOOT_regs.GBA", 1); --! @brief Process to bypass internal signals requiered for correct
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA", --! use of i2c_master_driver
"s_MULTIBOOT_regs.MBA", 1); p_sig_spy : process is
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_GBA_ICAP", begin
"s_MULTIBOOT_regs.GBA_ICAP", 1); init_signal_spy("/uut/s_clk_125MHz", "s_test", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA_ICAP", init_signal_spy("/uut/inst_image1_core/s_clk.SYS_A", "wb_clk", 1);
"s_MULTIBOOT_regs.MBA_ICAP", 1); init_signal_spy("/uut/inst_image1_core/s_rst.SYS_A", "s_rst_SYS_A", 1);
init_signal_spy("/uut/inst_image1_core/inst_m25p32/inst_m25p32_regs/s_FMI", init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_regs/s_CTR0",
"s_M25P32_regs.FMI", 1); "s_I2C_regs.CTR0", 1);
init_signal_spy("/uut/inst_image1_core/inst_m25p32/inst_m25p32_regs/s_SR_m25p32", init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_regs/s_LT",
"s_M25P32_regs.SR_m25p32", 1); "s_I2C_regs.LT", 1);
wait; init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRXA_slv",
end process p_sig_spy; "s_I2C_regs.DRXA", 1);
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_core/s_DRXB_slv",
"s_I2C_regs.DRXB", 1);
init_signal_spy("/uut/inst_image1_core/inst_i2c_slave/inst_i2c_slave_regs/s_DTX",
"s_I2C_regs.DTX", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_CTR0",
"s_MULTIBOOT_regs.CTR0", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_CTR1",
"s_MULTIBOOT_regs.CTR1", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_STAT",
"s_MULTIBOOT_regs.STAT", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA",
"s_MULTIBOOT_regs.MBA", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_GBA",
"s_MULTIBOOT_regs.GBA", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA",
"s_MULTIBOOT_regs.MBA", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_GBA_ICAP",
"s_MULTIBOOT_regs.GBA_ICAP", 1);
init_signal_spy("/uut/inst_image1_core/inst_multiboot/multiboot_regs_inst/s_MBA_ICAP",
"s_MULTIBOOT_regs.MBA_ICAP", 1);
init_signal_spy("/uut/inst_image1_core/inst_m25p32/inst_m25p32_regs/s_FMI",
"s_M25P32_regs.FMI", 1);
init_signal_spy("/uut/inst_image1_core/inst_m25p32/inst_m25p32_regs/s_SR_m25p32",
"s_M25P32_regs.SR_m25p32", 1);
wait;
end process p_sig_spy;
-- Instantiate the Unit Under Test (UUT) -- Instantiate the Unit Under Test (UUT)
...@@ -170,6 +195,7 @@ begin ...@@ -170,6 +195,7 @@ begin
generic map(g_SCL_PERIOD => c_SCL_I2C_DRIVER_PERIOD, generic map(g_SCL_PERIOD => c_SCL_I2C_DRIVER_PERIOD,
g_LOG_PATH => "../test/log/i2c_master_driver.txt") g_LOG_PATH => "../test/log/i2c_master_driver.txt")
port map(tb_clk => wb_clk, port map(tb_clk => wb_clk,
rst_n => s_rst_n,
sda_master_i => s_I2C_master_i.SDA, sda_master_i => s_I2C_master_i.SDA,
sda_master_o => s_I2C_master_o.SDA, sda_master_o => s_I2C_master_o.SDA,
...@@ -190,7 +216,7 @@ begin ...@@ -190,7 +216,7 @@ begin
read_done_o => s_i2c_driver_ctrl_done.READ); read_done_o => s_i2c_driver_ctrl_done.READ);
uut: image1_top uut: image1_top
generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS) -- generic map(g_NUMBER_OF_CHANNELS => work.image1_top_tb_pkg.c_NUMBER_OF_CHANNELS)
port map(RST_N => s_RST_N, port map(RST_N => s_RST_N,
CLK20_VCXO => s_CLK20_VCXO, CLK20_VCXO => s_CLK20_VCXO,
FPGA_CLK_P => s_FPGA_CLK_P, FPGA_CLK_P => s_FPGA_CLK_P,
...@@ -250,6 +276,7 @@ begin ...@@ -250,6 +276,7 @@ begin
procedure start_I2C is procedure start_I2C is
begin begin
s_I2C_driver_ctrl.START <= '1'; s_I2C_driver_ctrl.START <= '1';
assert false report "start condition to master" severity note;
wait until rising_edge(s_I2C_driver_ctrl_done.START); wait until rising_edge(s_I2C_driver_ctrl_done.START);
wait until rising_edge(wb_clk); wait until rising_edge(wb_clk);
s_I2C_driver_ctrl.START <= '0'; s_I2C_driver_ctrl.START <= '0';
...@@ -301,9 +328,10 @@ begin ...@@ -301,9 +328,10 @@ begin
begin begin
tb_state <= ST_INIT; tb_state <= ST_INIT;
wait until rising_edge(s_rst_n);
initial_inputs; initial_inputs;
wait until falling_edge(s_rst); -- wait until falling_edge(s_rst);
wait for work.image1_pkg.c_WB_CLK_PERIOD*25; wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
--! First we place a write --! First we place a write
...@@ -312,26 +340,29 @@ begin ...@@ -312,26 +340,29 @@ begin
--! write the register into I2C to the master --! write the register into I2C to the master
--! Please check in the wave.do file the internal register --! Please check in the wave.do file the internal register
--! against the s_DTX register in the i2c_master_driver! --! against the s_DTX register in the i2c_master_driver!
--! [0] Reading I2C registers --! [0] Reading I2C registers
tb_state <= ST_READ_CTR0; tb_state <= ST_READ_CTR0;
start_I2C; start_I2C;
assert false report "-------read ctr0" severity note;
read_I2C(s_FPGA_GA, c_I2C_CTR0_addr); read_I2C(s_FPGA_GA, c_I2C_CTR0_addr);
assert false report "-------done!" severity note;
assert false report "Read I2C CTR0" severity note; assert false report "Read I2C CTR0" severity note;
assert f_STD_LOGIC_VECTOR(s_I2C_regs.CTR0) assert f_STD_LOGIC_VECTOR(s_I2C_regs.CTR0)
= s_rd_data report "Mismatch in I2C CTR0 readback" = s_rd_data report "Mismatch in I2C CTR0 readback"
severity Error; severity Error;
wait for work.image1_pkg.c_WB_CLK_PERIOD*25; wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
-- tb_state <= ST_WRITE_LED; tb_state <= ST_WRITE_LED;
--
-- start_i2c; start_i2c;
-- assert false report "-------writing" severity note; assert false report "-------writing" severity note;
-- write_i2c(s_fpga_ga, x"0080", x"00000055"); write_i2c(s_fpga_ga, x"0080", x"00000055");
-- assert false report "-------done!" severity note; assert false report "-------done!" severity note;
--
-- wait for work.image1_pkg.c_WB_CLK_PERIOD*25; wait for work.image1_pkg.c_WB_CLK_PERIOD*25;
tb_state <= ST_READ_LED; tb_state <= ST_READ_LED;
......
hdl/IMAGES/image1/test/image1_top_tb_pkg.vhd
View file @ 722c523e
...@@ -20,7 +20,7 @@ package image1_top_tb_pkg is ...@@ -20,7 +20,7 @@ package image1_top_tb_pkg is
:= work.image1_pkg.c_NUMBER_OF_CHANNELS; := work.image1_pkg.c_NUMBER_OF_CHANNELS;
component image1_top component image1_top
generic(g_NUMBER_OF_CHANNELS : NATURAL := 6); -- generic(g_NUMBER_OF_CHANNELS : NATURAL := 6);
port (RST_N : in STD_LOGIC; port (RST_N : in STD_LOGIC;
CLK20_VCXO : in STD_LOGIC; CLK20_VCXO : in STD_LOGIC;
FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock FPGA_CLK_P : in STD_LOGIC; --Using the 125MHz clock
...@@ -37,12 +37,12 @@ package image1_top_tb_pkg is ...@@ -37,12 +37,12 @@ package image1_top_tb_pkg is
LED_WR_OK_SYSPW : out STD_LOGIC; LED_WR_OK_SYSPW : out STD_LOGIC;
LED_WR_OWNADDR_I2C : out STD_LOGIC; LED_WR_OWNADDR_I2C : out STD_LOGIC;
--! I/Os for pulses --! I/Os for pulses
PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); PULSE_FRONT_LED_N : out STD_LOGIC_VECTOR(6 downto 1);
PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); PULSE_REAR_LED_N : out STD_LOGIC_VECTOR(6 downto 1);
FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); FPGA_INPUT_TTL_N : in STD_LOGIC_VECTOR(6 downto 1);
FPGA_OUT_TTL : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); FPGA_OUT_TTL : out STD_LOGIC_VECTOR(6 downto 1);
FPGA_BLO_IN : in STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); FPGA_BLO_IN : in STD_LOGIC_VECTOR(6 downto 1);
FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(g_NUMBER_OF_CHANNELS downto 1); FPGA_TRIG_BLO : out STD_LOGIC_VECTOR(6 downto 1);
INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1); INV_IN_N : in STD_LOGIC_VECTOR(4 downto 1);
INV_OUT : out STD_LOGIC_VECTOR(4 downto 1); INV_OUT : out STD_LOGIC_VECTOR(4 downto 1);
--! Lines for the i2c_slave --! Lines for the i2c_slave
......
hdl/IMAGES/image1/test/log/i2c_master_driver.txt
View file @ 722c523e
...@@ -2,7 +2,14 @@ ...@@ -2,7 +2,14 @@
1 OK READ WISHBONE HIGH 1 OK READ WISHBONE HIGH
1 OK READ WISHBONE LOW 1 OK READ WISHBONE LOW
1 OK READ [ADDRESS|0] 1 OK READ [ADDRESS|0]
2 OK READ [ADDRESS|0] 2 OK WRITE [ADDRESS|0]
2 OK READ WISHBONE HIGH 2 OK WRITE WISHBONE HIGH
2 OK READ WISHBONE LOW 2 OK WRITE WISHBONE LOW
2 OK READ [ADDRESS|0] 2 OK WRITE READ DATA 0
2 OK WRITE READ DATA 1
2 OK WRITE READ DATA 2
2 OK WRITE READ DATA 3
3 OK READ [ADDRESS|0]
3 OK READ WISHBONE HIGH
3 OK READ WISHBONE LOW
3 OK READ [ADDRESS|0]
hdl/i2c_slave_wb_master/rtl/i2c_regs.vhd
View file @ 722c523e
...@@ -99,15 +99,19 @@ signal s_wb_master_we_o : STD_LOGIC; ...@@ -99,15 +99,19 @@ signal s_wb_master_we_o : STD_LOGIC;
signal s_wb_master_ack_retries : STD_LOGIC_VECTOR(c_RETRY_LENGTH - 1 downto 0) signal s_wb_master_ack_retries : STD_LOGIC_VECTOR(c_RETRY_LENGTH - 1 downto 0)
:= (others => '0'); := (others => '0');
signal s_wb_addr_rd : STD_LOGIC_VECTOR(15 downto 0) := (others => '0');
signal s_wb_addr_rd : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); attribute keep : string;
signal wbm_dat_out : std_logic_vector(31 downto 0);
attribute keep of wbm_dat_out : signal is "true";
begin begin
wb_master_we_o <= s_wb_master_we_o; wb_master_we_o <= s_wb_master_we_o;
s_wb_slave_addr <= UNSIGNED(wb_slave_addr_i); s_wb_slave_addr <= UNSIGNED(wb_slave_addr_i);
s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0); s_CTR0_slv <= f_STD_LOGIC_VECTOR(s_CTR0);
s_LT <= f_LT(LT_i); s_LT <= f_LT(LT_i);
wb_master_data_o <= wbm_dat_out;
wb_slave_ack_o <= s_wb_slave_ack; wb_slave_ack_o <= s_wb_slave_ack;
wb_slave_rty_o <= s_wb_slave_rty; wb_slave_rty_o <= s_wb_slave_rty;
...@@ -161,7 +165,7 @@ begin ...@@ -161,7 +165,7 @@ begin
wb_master_stb_o <= '0'; wb_master_stb_o <= '0';
wb_master_cyc_o <= '0'; wb_master_cyc_o <= '0';
wb_master_sel_o <= (others => '0'); wb_master_sel_o <= (others => '0');
wb_master_data_o <= (others => '0'); wbm_dat_out <= (others => '0');
wb_master_addr_o <= (others => '0'); wb_master_addr_o <= (others => '0');
s_dtx <= (others => '0'); s_dtx <= (others => '0');
else else
...@@ -191,14 +195,14 @@ begin ...@@ -191,14 +195,14 @@ begin
wb_master_stb_o <= '1'; wb_master_stb_o <= '1';
s_wb_master_we_o <= '1'; s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F"; wb_master_sel_o <= X"F";
wb_master_data_o <= f_ch_endian(DRXA_i); wbm_dat_out <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0); wb_master_addr_o <= DRXB_i(15 downto 0);
when S2N_WB_NOOP => when S2N_WB_NOOP =>
wb_master_cyc_o <= '1'; wb_master_cyc_o <= '1';
wb_master_stb_o <= '1'; wb_master_stb_o <= '1';
s_wb_master_we_o <= '1'; s_wb_master_we_o <= '1';
wb_master_sel_o <= X"F"; wb_master_sel_o <= X"F";
wb_master_data_o <= f_ch_endian(DRXA_i); wbm_dat_out <= f_ch_endian(DRXA_i);
wb_master_addr_o <= DRXB_i(15 downto 0); wb_master_addr_o <= DRXB_i(15 downto 0);
when S3_WB_ACK => when S3_WB_ACK =>
-- null; -- null;
......
hdl/i2c_slave_wb_master/rtl/i2c_slave_core.vhd
View file @ 722c523e
---------------------------------------------------------------------------------- ----------------------------------------------------------------------------------
-- Company: CERN, BE-CO-HT -- Company: CERN, BE-CO-HT
-- Engineer: Carlos Gil Soriano -- Engineers: Carlos Gil Soriano
-- Theodor-Adrian Stana
-- --
-- Create Date: 11:29:56 10/25/2011 -- Create Date: 11:29:56 10/25/2011
-- Design Name: I2C Slave to Wishbone bridge -- Design Name: I2C Slave to Wishbone bridge
...@@ -170,15 +171,10 @@ signal s_watchdog_cnt_rst : STD_LOGIC; ...@@ -170,15 +171,10 @@ signal s_watchdog_cnt_rst : STD_LOGIC;
signal s_watchdog_cnt_slv : STD_LOGIC_VECTOR(c_WATCHDOG_WIDTH - 1 downto 0); signal s_watchdog_cnt_slv : STD_LOGIC_VECTOR(c_WATCHDOG_WIDTH - 1 downto 0);
signal s_watchdog_cnt : NATURAL; signal s_watchdog_cnt : NATURAL;
attribute keep : string; signal txsr : std_logic_vector(31 downto 0);
signal s_dummy : std_logic_vector(0 to 31);
attribute keep of s_dummy : signal is "true";
begin begin
s_dummy(0 to 31) <= f_ch_endian(s_pf_wb_data(31 downto 0));
s_CTR0 <= f_CTR0(CTR0_i); s_CTR0 <= f_CTR0(CTR0_i);
LT_o <= f_STD_LOGIC_VECTOR(s_LT); LT_o <= f_STD_LOGIC_VECTOR(s_LT);
s_pf_wb_data <= pf_wb_data_i; s_pf_wb_data <= pf_wb_data_i;
...@@ -228,8 +224,22 @@ begin ...@@ -228,8 +224,22 @@ begin
sda_o <= s_sda_o; sda_o <= s_sda_o;
p_sda_o: process(i2c_SLA_fsm, -- Process to control the TX shift register
s_bit_cnt_slv(0)) -- p_txsr: process (clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if (rst_i = '1') then
-- txsr <= (others => '0');
-- elsif (i2c_sla_fsm = S5W1A_I2C_ADDR_ACK) then
-- txsr <= f_ch_endian(pf_wb_data_i);
-- elsif (i2c_sla_fsm = S5W2_WRITE_SDA) then
-- txsr <= txsr(30 downto 0) & '0';
-- end if;
-- end if;
-- end process p_txsr;
p_sda_o: process(i2c_SLA_fsm, txsr)
-- variable v_bit_inv : UNSIGNED(2 downto 0); -- variable v_bit_inv : UNSIGNED(2 downto 0);
-- variable v_bit_order : NATURAL; -- variable v_bit_order : NATURAL;
variable v_bit_un : UNSIGNED(2 downto 0); variable v_bit_un : UNSIGNED(2 downto 0);
...@@ -253,9 +263,11 @@ begin ...@@ -253,9 +263,11 @@ begin
v_pf_wb_data(0 to 31) := s_pf_wb_data(31 downto 0); -- f_ch_endian(s_pf_wb_data(31 downto 0)); -- v_pf_wb_data(0 to 31) := f_ch_endian(s_pf_wb_data(31 downto 0));
-- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data); -- -- v_pf_wb_data := s_pf_wb_data; -- f_ch_endian(s_pf_wb_data);
s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8)); -- s_sda_o <= v_pf_wb_data(s_byte_cnt*8 + (s_bit_cnt mod 8));
s_sda_o <= txsr(31);
when others => when others =>
s_sda_o <= '1'; s_sda_o <= '1';
end case; end case;
...@@ -553,6 +565,7 @@ begin ...@@ -553,6 +565,7 @@ begin
if rst_i = '1' if rst_i = '1'
or s_watchdog_cnt >= c_WATCHDOG_END_VALUE then or s_watchdog_cnt >= c_WATCHDOG_END_VALUE then
i2c_SLA_fsm <= R0_RESET; i2c_SLA_fsm <= R0_RESET;
txsr <= (others => '0');
else else
case i2c_SLA_fsm is case i2c_SLA_fsm is
when R0_RESET => when R0_RESET =>
...@@ -634,7 +647,7 @@ begin ...@@ -634,7 +647,7 @@ begin
when S5W1_I2C_ADDR => when S5W1_I2C_ADDR =>
if s_bit_done = '1' then if s_bit_done = '1' then
if s_bit_cnt = 7 then if s_bit_cnt = 7 then
if s_DRX_slv(6 downto 0) = "0000000" if s_DRX_slv(6 downto 0) = "0000000" -- ????????????????
or s_DRX_slv(6 downto 0) = or s_DRX_slv(6 downto 0) =
STD_LOGIC_VECTOR(s_CTR0.I2C_ADDR) then STD_LOGIC_VECTOR(s_CTR0.I2C_ADDR) then
i2c_SLA_fsm <= S5W1A_I2C_ADDR_ACK; i2c_SLA_fsm <= S5W1A_I2C_ADDR_ACK;
...@@ -645,6 +658,7 @@ begin ...@@ -645,6 +658,7 @@ begin
check_start_stop; check_start_stop;
end if; end if;
when S5W1A_I2C_ADDR_ACK => when S5W1A_I2C_ADDR_ACK =>
txsr <= f_ch_endian(pf_wb_data_i);
if s_bit_done = '1' then if s_bit_done = '1' then
i2c_SLA_fsm <= S5W2_WRITE_SDA; i2c_SLA_fsm <= S5W2_WRITE_SDA;
end if; end if;
...@@ -654,8 +668,9 @@ begin ...@@ -654,8 +668,9 @@ begin
end if; end if;
when S5W2_WRITE_SDA => when S5W2_WRITE_SDA =>
if s_bit_done = '1' then if s_bit_done = '1' then
txsr <= txsr(30 downto 0) & '0';
if s_bit_cnt = 8 then if s_bit_cnt = 8 then
i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK; i2c_SLA_fsm <= S5W2A_WRITE_SDA_ACK;
end if; end if;
--! It can be removed, never reached --! It can be removed, never reached
check_start_stop; check_start_stop;
......
hdl/i2c_slave_wb_master/test/i2c_master_driver.vhd
View file @ 722c523e
...@@ -17,6 +17,7 @@ entity i2c_master_driver is ...@@ -17,6 +17,7 @@ entity i2c_master_driver is
g_SCL_PERIOD : TIME := 250 us; g_SCL_PERIOD : TIME := 250 us;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt"); g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC; port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC; sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC; sda_master_o : out STD_LOGIC;
...@@ -283,13 +284,23 @@ begin ...@@ -283,13 +284,23 @@ begin
s_sda_master_o <= '0'; s_sda_master_o <= '0';
end procedure; end procedure;
variable first : boolean := true;
begin begin
if (first = true) then
wait until rst_n = '1';
first := false;
end if;
if start_i = '1' then if start_i = '1' then
assert false report "mst start" severity note;
start_I2c; start_I2c;
elsif pause_i = '1' then elsif pause_i = '1' then
assert false report "mst pause" severity note;
pause_I2C; pause_I2C;
elsif write_i = '1' then elsif write_i = '1' then
assert false report "mst write" severity note;
s_test_id <= s_test_id + 1; s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i); v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0] --! 1.- Send [ADDRESS|0]
...@@ -320,6 +331,7 @@ begin ...@@ -320,6 +331,7 @@ begin
wait until rising_edge(tb_clk); wait until rising_edge(tb_clk);
s_write_done <= '0'; s_write_done <= '0';
elsif read_i = '1' then elsif read_i = '1' then
assert false report "mst read" severity note;
s_test_id <= s_test_id + 1; s_test_id <= s_test_id + 1;
v_write_data := order_write_data(wr_data_i); v_write_data := order_write_data(wr_data_i);
--! 1.- Send [ADDRESS|0] --! 1.- Send [ADDRESS|0]
...@@ -357,7 +369,9 @@ begin ...@@ -357,7 +369,9 @@ begin
wait until rising_edge(tb_clk); wait until rising_edge(tb_clk);
s_read_done <= '0'; s_read_done <= '0';
end if; end if;
wait until rising_edge(tb_clk); wait until rising_edge(tb_clk);
end process; end process;
end; end;
hdl/i2c_slave_wb_master/test/i2c_tb_pkg.vhd
View file @ 722c523e
...@@ -66,6 +66,7 @@ package i2c_tb_pkg is ...@@ -66,6 +66,7 @@ package i2c_tb_pkg is
g_SCL_PERIOD : TIME := c_SCL_I_PERIOD; g_SCL_PERIOD : TIME := c_SCL_I_PERIOD;
g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt"); g_LOG_PATH : STRING := "../test/log/i2c_master_driver.txt");
port(tb_clk : in STD_LOGIC; port(tb_clk : in STD_LOGIC;
rst_n : in std_logic;
sda_master_i : in STD_LOGIC; sda_master_i : in STD_LOGIC;
sda_master_o : out STD_LOGIC; sda_master_o : out STD_LOGIC;
......
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