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Conv TTL Blocking - Gateware
Commit 68e5ac71 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Updated HDL guide 

- made HDL block diagram clearer
- updated architecture organization figure
- updated folder structure
- changed overall document organization, `Folder structure' and
`Getting around the code sections' are now after `Introduction'
- some small changes in text and wording
Signed-off-by: Theodor-Adrian Stana's avatarThedi Stana <t.stana@cern.ch>
parent 03f3fdcb
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doc/hdlguide/cern-title.tex
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\noindent \rule{\textwidth}{.1cm}
\hfill Gateware v2.00
\hfill Gateware v1.0
\hfill\today
\hfill January 5, 2014
\vspace*{3cm}
......
doc/hdlguide/fig/arch.svg
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doc/hdlguide/hdlguide-conv-ttl-blo.tex
View file @ 68e5ac71
......@@ -55,6 +55,7 @@
14-08-2013 & 1.02 & Changed name of \textit{elma\_i2c} to \textit{vbcp\_wb} \\
29-10-2013 & 1.03 & Added MultiBoot support to firmware \\
20-11-2013 & 1.04 & Changed system clock to 20~MHz \\
05-01-2014 & 1.05 & Updated folder structure and renamed \textit{vbcp\_wb} to \textit{i2c\_bridge} \\
\hline
\end{tabular}
}
......@@ -67,7 +68,6 @@
%------------------------------------------------------------------------------
% List of figs, tables, abbrevs
%------------------------------------------------------------------------------
\pagebreak
\listoffigures
\listoftables
......@@ -77,7 +77,7 @@ DAC & Digital-to-Analog Converter \\
FPGA & Field-Programmable Gate Array \\
FSM & Finite-State Machine \\
IC & Integrated Circuit \\
I$^2$C & Inter-Intergrated Circuit (bus) \\
I$^2$C & Inter-Integrated Circuit (bus) \\
PLL & Phase-Locked Loop \\
SPI & Serial Peripheral Interface \\
SysMon & (ELMA) System Montior \\
......@@ -100,8 +100,8 @@ the CONV-TTL-BLO capabilities:
\begin{itemize}
\item pulse detection (on pulse rising edge)
\item fixed-width pulse generation
\item status retrieval via I$^2$C and VBCP
\item remote reprogramming via I$^2$C and VBCP
\item status retrieval via I$^2$C
\item remote reprogramming via I$^2$C
\end{itemize}
Figure~\ref{fig:hdl-bd} shows a simplified block diagram of the HDL firmware. Each of the
......@@ -118,13 +118,182 @@ blocks in the figure is presented in following sections.
%------------------------------------------------------------------------------
\subsection*{Additional documentation}
%\textcolor{red}{\textbf{!!!}}
\begin{itemize}
\item CONV-TTL-BLO User Guide \cite{ctb-ug}
\item CONV-TTL-BLO Hardware Guide \cite{ctb-hwguide}
\end{itemize}
%======================================================================================
% SEC: Folder structure
%======================================================================================
\section{Folder Structure}
\label{sec:fold-struct}
The folder structure for the project is presented below.
\renewcommand{\labelitemi}{$\rightarrow$}
\renewcommand{\labelitemii}{$\rightarrow$}
\renewcommand{\labelitemiii}{$\rightarrow$}
\renewcommand{\labelitemiv}{$\rightarrow$}
\begin{itemize}
\item conv-ttl-blo-gw/
\begin{itemize}
\item doc/
\begin{itemize}
\item hdlguide/
\end{itemize}
\item ip\_cores/
\begin{itemize}
\item general-cores/
\end{itemize}
\item modules/
\begin{itemize}
\item Release/
% \begin{itemize}
% \item conv\_regs.vhd
% \item conv\_regs.wb
% \end{itemize}
\item pulsetest/
% \begin{itemize}
% \item conv\_regs.vhd
% \item conv\_regs.wb
% \item pgen\_ctrl\_regs.vhd
% \item pgen\_ctrl\_regs.wb
% \item pulse\_cnt\_regs.vhd
% \item pulse\_cnt\_regs.wb
% \item pulse\_gen\_gp.vhd
% \end{itemize}
\item ctb\_pulse\_gen.vhd
\item reset\_gen.vhd
\item rtm\_detector.vhd
\end{itemize}
\item sim/
\item syn/
\begin{itemize}
\item Release/
\item pulsetest/
\item regtest/
\end{itemize}
\item top/
\begin{itemize}
\item Release/
\begin{itemize}
\item conv\_ttl\_blo.ucf
\item conv\_ttl\_blo.vhd
\end{itemize}
\item pulsetest/
\begin{itemize}
\item pulsetest.ucf
\item pulsetest.vhd
\end{itemize}
\item regtest/
\begin{itemize}
\item pulsetest.ucf
\item pulsetest.vhd
\end{itemize}
\end{itemize}
\end{itemize}
\end{itemize}
Gateware files are organized on a per type-of-project basis. There are two different types of
projects for CONV-TTL-BLO gateware: the \textit{release project} and \textit{test projects}.
The release project is the latest production firmware version, that goes on the CONV-TTL-BLO
board used in the field. Test projects are meant to be downloaded to a CONV-TTL-BLO for
testing the CONV-TTL-BLO system under long-term test conditions. The projects present in the
repository at the time of writing of this document are presented in Table~\ref{tbl:fold-struct-proj}.
\begin{table}[h]
\caption{Gateware projects in the repository}
\label{tbl:fold-struct-proj}
\centerline
{
\begin{tabular}{l p{.6\textwidth}}
\hline
\multicolumn{1}{c}{\textbf{Project}} & \multicolumn{1}{c}{\textbf{Description}} \\
\hline
\textit{conv\_ttl\_blo} & Design-wide release project to be used in the field \\
\textit{regtest} & Long-term test for testing the I$^2$C communication by writing
to a RAM on the FPGA \\
\textit{pulsetest} & Long-term test for testing pulse repetition on the CONV-TTL-BLO \\
\hline
\end{tabular}
}
\end{table}
As can be seen from the folder structure above, gateware files are organized in the
\textit{modules/}, \textit{syn/} and \textit{top/} folders following this project convention.
Files in these folders (where relevant) are organized in the \textit{Release/}, \textit{pulsetest/}
and \textit{regtest/} folders, where the \textit{Release/} folder of course represents the
release firmware and the other two are test projects, as their names suggest.
HDL files are organized into modules and top-level files. Modules are blocks used within the
design, while top-level files combine modules together into a design. Modules relevant for the
whole design are stored directly under the \textit{modules/} folder, while modules specific
to a certain project are stored within the project's sub-folder in the \textit{modules/} folder.
Apart from the top folder of the design, the \textit{top/} folder for each project also contains
the .ucf constraints file for synthesis.
One place where the project structure is not necessarily enforced is the \textit{sim/} folder.
This folder is meant to contain files relevant for simulation of various modules within
the design and as such can be composed of folders named after the component to be simulated.
The \textit{syn/} folder holds the actual project files for Xilinx ISE, as well as other
various output files from ISE. Each ISE project, be it for release or test project, together
with its output files, is contained within its own sub-folder in the \textit{syn/} folder.
%======================================================================================
% SEC: Getting Around the Code
%======================================================================================
\section{Getting Around the Code}
\label{sec:get-around}
Code in the top-level files is organized in code sections. A code section is a piece of code
pertaining to a certain part of the design, where component instantiations and input and
output port assignments are made. For example, there is a section pertaining to
pulse repetition, where there is a generate block to generate the logic necessary for pulse
repetition on each channel, including the pulse status LEDs.
\begin{figure}[h]
\centerline{\includegraphics[width=.59\textwidth]{fig/arch}}
\caption{VHDL architecture of the release firmware}
\label{fig:arch}
\end{figure}
Ports and signals usually follow the coding guideline at~\cite{coding-guidelines}. Most of the
top-level ports of the firmware are lower-case versions of their schematics counterparts. The
exceptions from this are due to either net names that could not be syntactically represented in
VHDL, or net names that have been made clearer in VHDL code.
The declarative part of the architecture is organized as shown in Figure~\ref{fig:arch}~(a).
Types are declared right after the architecture declaration, followed by constant
declarations, followed by component declarations, after which the various signals
are declared.
The body of the architecture is organised in code sections as shown in
Figure~\ref{fig:arch}~(b). It starts with the instantiation of the \textit{reset\_gen}
component which generates the board-wide reset.
Then, in the I$^2$C section, the I$^2$C bridge component is instantiated,
the logic for lighting the I2C front panel LED is defined, as well as the CWDTO bit
in the SR (see Appendix~\ref{app:memmap-csr}). Before the end of this section, an
\textit{xwb\_crossbar} is instantiated to communicate to the various peripherals.
The I$^2$C section is followed by the main code section of the design, the pulse
generation section. Here, a generate block is used to generate the logic for each
channel, including the instantiation of a \textit{ctb\_pulse\_gen} block, the
implementation of the no signal detect block (see Section~\ref{sec:pulse-gen-brdlvl}),
the output pulse assignments and the logic for flashing the pulse LED for 262~ms.
After the pulse generation section, the MultiBoot component is instantiated and
connected to the SPI pins to and from the on-board flash chip.
Two more short code sections remain, that in which the \textit{bicolor\_led\_ctrl}
component is connected to the line and column outputs to the bicolor LED matrix,
and the connection of the RTM detection inputs to the \textit{rtm\_detector}
component.
%==============================================================================
% SEC: Clocks
%==============================================================================
......@@ -138,14 +307,14 @@ of 125~MHz is generated on-board via a Texas Instruments PLL IC from a 25~MHz VC
Two DACs are provided on-board for controlling the two VCXOs. The DACs can be
controlled via SPI, but this feature is not yet implemented.
\begin{figure}
Table~\ref{tbl:clocks} lists the clock domains used in the firmware.
\begin{figure}[h]
\centerline{\includegraphics[width=\textwidth]{fig/clocks}}
\caption{FPGA clock inputs}
\label{fig:clocks}
\end{figure}
Table~\ref{tbl:clocks} lists the clock domains in the firmware.
\begin{table}[h]
\caption{Clock domains}
\label{tbl:clocks}
......@@ -199,7 +368,10 @@ signal is de-asserted, the counter is disabled and the \textit{reset\_gen}
module remains inactive.
The module reactivates on the power-on reset, or when a reset is triggered externally, via
the \textit{rst\_i} pin.
the \textit{rst\_i} pin. The \textit{rst\_i} pin is tied in the design to the first bit
in the control register (CR, see Appendix~\ref{app:memmap-csr}), which has to be first
unlocked by writing the RST\_UNLOCK bit. Both these registers are implemented in the
top-level file of the design.
Note that the VHDL of this module is Xilinx and XST-specific and porting to a different
FPGA architecture is not guaranteed to provide the same results. The \textit{reset\_gen}
......@@ -240,7 +412,9 @@ module sets the \textit{rtmm\_ok} and \textit{rtmp\_ok} signals low if the
\textit{rtmm\_i} and \textit{rtmp\_i} input signals are respectively all-ones.
The \textit{rtmm\_ok} and \textit{rtmp\_ok} signals are NANDed together to light
the ERR status LED on the CONV-TTL-BLO.
the ERR status LED on the CONV-TTL-BLO. The status of the RTM detection lines
can also be read via their respective fields in the CONV board status register
(see Appendix~\ref{app:memmap-csr}).
\begin{figure}[h]
\centerline{\includegraphics[width=.85\textwidth]{fig/rtm-detect}}
......@@ -248,10 +422,6 @@ the ERR status LED on the CONV-TTL-BLO.
\label{fig:rtm-detect}
\end{figure}
The status of the RTM detection lines can also be read via their respective fields
in the CONV board status register (Appendix~\ref{app:memmap-csr}).
%==============================================================================
% SEC: Bicolor LEDs
%==============================================================================
......@@ -288,12 +458,13 @@ in the CONV board status register (Appendix~\ref{app:memmap-csr}).
The \textit{bicolor\_led\_ctrl} block controls the lighting of a bicolor
LED matrix. Based on the refresh rate given via the \textit{g\_REFRESH\_RATE}
generic, the clock frequency (\textit{g\_CLK\_FREQ} generic) and the number of
lines and columns, the module controls lighting each LED in the LED matrix.
lines and columns, the module lights each LED in the LED matrix sequentially at
the refresh rate given by the user.
Figure~\ref{fig:bicolor-led} shows an example of controlling a three-line,
two-column red-and-green LED matrix. The FPGA ouputs for the columns~(C) are connected
to buffers and serial resistors and then to the LEDs. The FPGA outputs for lines~(L)
are connected to tri-state buffers and the to the LEDs. The FPGA outputs for line
are connected to tri-state buffers and then to the LEDs. The FPGA outputs for line
output enables~(L\_OEN) are connected to the output enable of the tri-state buffers.
\begin{figure}[hbtp]
......@@ -304,9 +475,9 @@ output enables~(L\_OEN) are connected to the output enable of the tri-state buff
The two-bit \textit{led\_state\_i} vector can be used to control the color of each
LED. Table~\ref{tbl:bicolor-led-state} lists the values that should be input on
\textit{led\_state\_i} to get the needed color. Definitions are provided in
the \textit{bicolor\_led\_ctrl\_pkg.vhd} file for setting the color of the LED
via \textit{led\_state\_i}; these constants are also listed in Table~\ref{tbl:bicolor-led-state}.
\textit{led\_state\_i} to get the needed color, as well as constant definitions
provided in the \textit{bicolor\_led\_ctrl\_pkg.vhd} file for setting the color of the LED
via \textit{led\_state\_i}.
\begin{table}[h]
\caption{LED state input}
......@@ -345,9 +516,9 @@ for the bicolor status LEDs in the CONV-TTL-BLO firmware.
\label{tbl:bicolor-led-state-conn}
\centerline
{
\begin{tabular}{l c l c c}
\begin{tabular}{l c l c}
\hline
\textbf{Line} & \textbf{Column} & \multicolumn{1}{c}{\textbf{LED}} & \textbf{LED state bits} & \textbf{Setting}\\
\textbf{Line} & \textbf{Column} & \multicolumn{1}{c}{\textbf{LED}} & \textbf{LED state bits} \\
\hline
1 & 1 & WHITE\_RABBIT\_ADDR & \textit{1..0} \\
1 & 2 & WHITE\_RABBIT\_GMT & \textit{3..2} \\
......@@ -366,9 +537,9 @@ for the bicolor status LEDs in the CONV-TTL-BLO firmware.
}
\end{table}
The states of the used LEDs can be found in Table 1 of \cite{ctb-ug}. They are
controlled by combinatorial multiplexers. The selection signals to these
multiplexers are set throughout the logic.
The states of the used LEDs can be found in Table 1 of the CONV-TTL-BLO User
Guide~\cite{ctb-ug}. They are controlled by combinatorial multiplexers. The
selection signals to these multiplexers are set throughout the logic.
%==============================================================================
% SEC: Pulse gen
......@@ -386,7 +557,7 @@ multiplexers are set throughout the logic.
\hline
\textbf{Entity} & \textit{ctb\_pulse\_gen} & \\
\textbf{Generics} & \textit{g\_pwidth} & Width of the output pulse in \textit{clk\_i} cycles \\
& \textit{g\_gf\_len} & Length of glitch filter \\
& \textit{g\_gf\_len} & Length of glitch filter in \textit{clk\_i} cycles \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{en\_i} & Pulse generator enable \\
......@@ -440,8 +611,9 @@ leading-edge pulse jitter, the glitch filter can be left disabled.
Regardless of whether the glitch filter is enabled or not, the FSM reacts to the
rising edge of one of its two start inputs. A rising edge on an input starts
the internal counter, which counts up to a maximum value of \textit{g\_pwidth}.
The behavior of the outputs are different, depending on the state of the glitch filter.
the internal counter, which counts up to a maximum value in order to assure a
pulse with the length \textit{g\_pwidth}.
The behavior of the outputs is different depending on the state of the glitch filter.
With the glitch filter disabled, the input pulse enables the
input flip-flop, which starts pulse generation. The pulse signal is then synchronized
......@@ -459,6 +631,12 @@ where the pulse reset is kept high. If any pulses arrive on the input while the
is in this rejection state, they are not replicated at the output. The pulse rejection
phase lasts for 4*\textit{g\_pwidth}, yielding a maximum duty cycle of 1/5 for input pulses.
Note that due to the fact that the counter starts counting up from zero and delays
in the glitch filter when it is enabled, the maximum value of the internal counter is not
\textit{g\_pwidth}. Instead, the counter counts up to a pair of VHDL constants defined
in the code. These constants assure the pulse at the output is kept high for a number of
\textit{g\_pwidth} cycles of the \textit{clk\_i} signal.
%------------------------------------------------------------------------------
% SUBSEC: Board-level
%------------------------------------------------------------------------------
......@@ -506,25 +684,25 @@ channel.
This section details the various peripherals mapped on the internal
Wishbone bus. Access to these peripherals is made through the two serial lines
on the VME P1 connector (\textit{SERCLK}, \textit{SERDAT}). The VBCP protocol
is used to access these peripherals. A bridge module translates VBCP transfers into
Wishbone transfers.
on the VME P1 connector (SERCLK, SERDAT). A protocol based on I$^2$C is used to
access these peripherals. The protocol, as well as the bridge component
translating I$^2$C accesses into Wishbone accesses, are defined in the bridge
component's documentation.
The complete memory map of the firmware can be found in Appendix~\ref{app:memmap}.
%------------------------------------------------------------------------------
% SUBSEC: Statregs
%------------------------------------------------------------------------------
\subsection{VBCP to Wishbone bridge}
\label{sec:elma-i2c}
\subsection{I$^2$C to Wishbone bridge}
\label{sec:i2c-bridge}
The \textit{vbcp\_wb} module implements a bridge between the serial lines on the
VME P1 connector using VBCP and the Wishbone interconnect. The module provides
The \textit{i2c\_bridge} module implements a bridge to translate I$^2$C accesses
on the VME P1 connector into Wishbone accesses on the FPGA. The module provides
one I$^2$C slave interface for connecting to an ELMA SysMon and one Wishbone
master interface.
Details about the module's implementation can be found in its documentation, in
the \textit{conv\_ttl\_blo\_gw/doc/vbcp\_wb/} folder (see Section~\ref{sec:fold-struct}).
Details about the module's implementation can be found in its documentation.
%------------------------------------------------------------------------------
% SUBSEC: CSR
......@@ -549,157 +727,10 @@ The MultiBoot module offers the remote reprogramming capabilities for the
CONV-TTL-BLO board. It offers a set of registers for controlling writing a bitstream
to the M25P32 flash chip and for issuing the remote reprogramming command.
For information on the module, refer to its documentation under the
\textit{conv\_ttl\_blo\_gw/doc/multiboot/} folder (see Section~\ref{sec:fold-struct}).
The memory map of the module is also present in this manual, for quick reference
For information on the module, refer to the module's documentation. The memory
map of the module is also present in this manual, for quick reference
(see Appendix~\ref{app:memmap-multiboot}).
%======================================================================================
% SEC: Folder structure
%======================================================================================
\section{Folder Structure}
\label{sec:fold-struct}
The folder structure for the project is presented below.
\renewcommand{\labelitemi}{$\rightarrow$}
\renewcommand{\labelitemii}{$\rightarrow$}
\renewcommand{\labelitemiii}{$\rightarrow$}
\renewcommand{\labelitemiv}{$\rightarrow$}
\begin{itemize}
\item ../ip\_cores/
\item conv-ttl-blo-gw/doc/
\begin{itemize}
\item hdlguide/
\item i2c\_slave/
\item multiboot/
\item vbcp\_wb/
\end{itemize}
\item conv-ttl-blo-gw/hdl/
\begin{itemize}
\item bicolor\_led\_ctrl/
\begin{itemize}
\item \textit{bicolor\_led\_ctrl.vhd}
\item \textit{bicolor\_led\_ctrl\_pkg.vhd}
\end{itemize}
\item ctb\_pulse\_gen/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{ctb\_pulse\_gen.vhd}
\end{itemize}
\end{itemize}
\item glitch\_filt/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{glitch\_filt.vhd}
\end{itemize}
\end{itemize}
\item multiboot/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{multiboot\_fsm.vhd}
\item \textit{multiboot\_regs.vhd}
\item \textit{spi\_master.vhd}
\item \textit{xil\_multiboot.vhd}
\end{itemize}
\end{itemize}
\textbf
{
\item release/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{conv\_regs.vhd}
\end{itemize}
\item top/
\begin{itemize}
\item \textit{conv\_ttl\_blo.vhd}
\item \textit{conv\_ttl\_blo.ucf}
\end{itemize}
\end{itemize}
}
\item reset\_gen/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{reset\_gen.vhd}
\end{itemize}
\end{itemize}
\item rtm\_detector/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{rtm\_detector.vhd}
\end{itemize}
\end{itemize}
\item vbcp\_wb/
\begin{itemize}
\item rtl/
\begin{itemize}
\item \textit{i2c\_slave.vhd}
\item \textit{vbcp\_wb.vhd}
\end{itemize}
\end{itemize}
\end{itemize}
\end{itemize}
The \textit{ip\_cores/} folder contains repository files that the firmware uses, such
as the Wishbone crossbar (\textit{xwb\_crossbar}).
Documentation such as this HDL guide and some HDL modules developed as part of the
CONV-TTL-BLO project can be found in the \textit{conv-ttl-blo/doc/} folder.
Modules that have been developed as part of the CONV-TTL-BLO project are present in
their own folders as sub-nodes of the \textit{conv-ttl-blo/hdl/} folder. In general,
the module files are present under an \textit{rtl/} sub-folder. The I$^2$C bridge
module folder also contains the instantiated \textit{i2c\_slave} module.
The \textit{release/} folder is the main folder in the firmware package, as can be seen from the
fact that it is bolded in the folder structure above. It contains top-level files in the
\textit{top/} folder (HDL and UCF file for pin definitions) and other specific modules in
the \textit{rtl/} folder.
%======================================================================================
% SEC: Getting Around the Code
%======================================================================================
\section{Getting Around the Code}
\label{sec:get-around}
As described above, the main part of the release firmware can be found in the
\textit{conv-ttl-blo/hdl/release/} folder. The top-level file is \textit{conv\_ttl\_blo.vhd}.
Ports and signals usually follow the coding guideline at~\cite{coding-guidelines}. Most of the
top-level ports of the firmware are lower-case versions of their schematics counterparts. The
exceptions from this are due to either net names that could not be syntactically represented in
VHDL, or net names that have been made clearer in VHDL code. Input ports are assigned to architecture
signals and signals are assigned to output ports in each code section.
\begin{figure}[h]
\centerline{\includegraphics[width=.7\textwidth]{fig/arch}}
\caption{VHDL architecture}
\label{fig:arch}
\end{figure}
The declarative part of the architecture is organized as shown in Figure~\ref{fig:arch}~(a).
Types are declared right after the architecture declaration, followed by con-
stant declarations, followed by component declarations, after which the var-
ious signals are declared.
The body of the architecture is organised as shown in in Figure~\ref{fig:arch}~(b). It begins
by instantiating a differential buffer for the 125~MHz system clock and instantiating the
\textit{reset\_gen} component. Then, the \textit{vbcp\_wb} bridge module is instantiated
along with the Wishbone crossbar that offers access to the rest of the Wishbone modules in
the design. Next, the CONV board CSR module is instantiated, followed by the instantiation
of twelve pulse generator modules, six for pulse repetition and six for the pulse LEDs.
This is followed by the logic for the status LEDs and the file ends with the RTM detection
modules.
%==============================================================================
% Appendices
%==============================================================================
......@@ -746,7 +777,6 @@ following sections list the memory map of each peripheral.
0x0 & BID & Board ID register \\
0x4 & SR & Status register \\
0x8 & CR & Control register \\
0xc & \textit{Reserved} & Write as '0'; read undefined \\
\end{tabular}
\end{table}
......@@ -771,12 +801,12 @@ following sections list the memory map of each peripheral.
%------------------------------------------------------------------------------
\subsubsection{Status register}
\begin{tabular}{l l c c l}
\begin{tabular}{l l c c p{.35\textwidth}}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
7..0 & FWVERS & R/O & X & Firmware version \\
15..8 & SWITCHES & R/O & X & Switch status \\
21..16 & RTM & R/O & X & RTM detection lines \\
22 & CWDTO & R/W & 0 & Communication Watchdog Timeout \\
22 & CWDTO & R/W & 0 & Communication watchdog timeout \\
31..23 & \textit{Reserved} & -- & X & \\
\end{tabular}
......@@ -816,25 +846,25 @@ following sections list the memory map of each peripheral.
\begin{tabular}{l l c c l}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
0 & RST\_UNL & R/W & 0 & Reset bit unlock \\
0 & RST\_UNLOCK & R/W & 0 & Reset bit unlock \\
1 & RST & R/W & 0 & Reset bit \\
31..2 & \textit{Reserved} & -- & X & \\
\end{tabular}
\noindent
{
\begin{tabular}{l p{.8\textwidth}}
\begin{tabular}{l p{.7\textwidth}}
\textbf{Field} & \textbf{Description} \\
RST\_UNL & Reset bit unlock \newline
RST\_UNLOCK & Reset bit unlock \newline
\textbf{0} -- RST bit locked, cannot be written \newline
\textbf{1} -- RST bit unlocked, can be written \\
RST & Reset bit \newline
\textbf{0} -- Idle \newline
\textbf{1} -- Initiate a system reset \newline
This bit needs to be unlocked by writing a '1' to the RST\_UNL bit in a
previous cycle. A write to this bit while RST\_UNL = '0' has no effect. \newline
Writing this bit to 1 with RST\_UNL = '1' will issue a system reset and
This bit needs to be unlocked by writing a '1' to the RST\_UNLOCK bit in a
previous cycle. A write to this bit while RST\_UNLOCK = '0' has no effect. \newline
Writing this bit to 1 with RST\_UNLOCK = '1' will issue a system reset and
the communication to the board will be lost for approx. 100~ms \\
\textit{Reserved} & Write as '0'; read undefined \\
\end{tabular}
......@@ -855,13 +885,10 @@ following sections list the memory map of each peripheral.
\begin{tabular}{l l p{.6\textwidth}}
\textbf{Offset} & \textbf{Name} & \textbf{Description} \\
0x00 & CR & Control Register \\
0x04 & SR & Status register \\
0x04 & SR & Status Register \\
0x08 & GBBAR & Golden Bitstream Base Address Register \\
0x0c & MBBAR & Multiboot Bitstream Base Address Register \\
0x10 & FAR & Flash access register \\
0x14 & \textit{Reserved} & Write as '0'; read undefined \\
0x18 & \textit{Reserved} & Write as '0'; read undefined \\
0x1c & \textit{Reserved} & Write as '0'; read undefined \\
0x10 & FAR & Flash Access Register \\
\end{tabular}
}
......@@ -873,7 +900,7 @@ following sections list the memory map of each peripheral.
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..18 & \textit{Reserved} & -- & X & \\
17 & IPROG & R/W & 0 & IPROG bit \\
16 & IPROG\_UNL & R/W & 0 & IPROG unlock bit \\
16 & IPROG\_UNLOCK & R/W & 0 & IPROG unlock bit \\
15..7 & \textit{Reserved} & -- & X & \\
6 & RDCFGREG & R/W & 0 & Read config register \\
5..0 & CFGREGADR & R/W & 0 & Config register address \\
......@@ -889,11 +916,11 @@ following sections list the memory map of each peripheral.
IPROG & Start IPROG sequence \newline
\textbf{0} -- Idle \newline
\textbf{1} -- Start the IPROG sequence \newline
This bit needs to be unlocked by setting the IPROG\_UNL bit in a previous cycle. Any
write to this bit with IPROG\_UNL = '0' has no effect. \newline
Writing this bit to '1' with IPROG\_UNL = '1' will issue the IPROG sequence and
This bit needs to be unlocked by setting the IPROG\_UNLOCK bit in a previous cycle. Any
write to this bit with IPROG\_UNLOCK = '0' has no effect. \newline
Writing this bit to '1' with IPROG\_UNLOCK = '1' will issue the IPROG sequence and
communication to the board will be lost until reprogramming is completed \\
IPROG\_UNL & Unlock bit for the IPROG command \newline
IPROG\_UNLOCK & Unlock bit for the IPROG command \newline
\textbf{0} -- IPROG bit locked, cannot be written \newline
\textbf{1} -- IPROG bit unlocked, can be written \\
RDCFGREG & Read FPGA configuration register \newline
......@@ -906,13 +933,13 @@ following sections list the memory map of each peripheral.
}
%------------------------------------------------------------------------------
\subsubsection{SR -- Image Register}
\subsubsection{SR -- Status Register}
\label{app:memmap-multiboot-sr}
\begin{tabular}{l l c c l}
\begin{tabular}{l l c c p{.3\textwidth}}
\textbf{Bits} & \textbf{Field} & \textbf{Access} & \textbf{Default} & \textbf{Description} \\
31..18 & \textit{Reserved} & -- & X & \\
17 & WDTO & R/W & 0 & Watchdog timeout \\
17 & MWDTO & R/W & 0 & Multiboot watchdog timeout \\
16 & IMGVALID & R/O & 0 & Image register is valid \\
15..0 & CFGREGIMG & R/O & 0 & Config. register image \\
\end{tabular}
......@@ -925,7 +952,7 @@ following sections list the memory map of each peripheral.
\textbf{Field} & \textbf{Description} \\
\textit{Reserved} & Write as '0'; read undefined. \\
WDTO & The watchdog of the MultiBoot FSM has timed out \newline
MWDTO & The watchdog of the MultiBoot FSM has timed out \newline
This bit is cleared by writing a '1' to it \\
IMGVALID & A read has been performed from the FPGA configuration
register at address CR.CFGREGADR, and its value is
......
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