Preparing for new folder structure

This commit: trying .gise in .gitignore Signed-off-by: Theodor Stana <t.stana@cern.ch>

Preparing for new folder structure
This commit: trying .gise in .gitignore Signed-off-by: Theodor Stana <t.stana@cern.ch>
5e1ddca0 · Theodor-Adrian Stana · 08c03415 · 5e1ddca0 · 08c03415 · 08c03415
Commit 5e1ddca0 authored Nov 18, 2013 by Theodor-Adrian Stana
13 changed files
--- a/hdl/glitch_filt/rtl/glitch_filt.vhd
+++ b/hdl/glitch_filt/rtl/glitch_filt.vhd
@@ -38,6 +38,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+use work.gencores_pkg.all;

 entity glitch_filt is
  generic
@@ -65,11 +66,30 @@ end entity glitch_filt;

 architecture behav of glitch_filt is

+  --============================================================================
+  -- Component declarations
+  --============================================================================
+  component gc_sync_ffs is
+    generic(
+      g_sync_edge : string := "positive"
+      );
+    port(
+      clk_i    : in  std_logic;  -- clock from the destination clock domain
+      rst_n_i  : in  std_logic;           -- reset
+      data_i   : in  std_logic;           -- async input
+      synced_o : out std_logic;           -- synchronized output
+      npulse_o : out std_logic;  -- negative edge detect output (single-clock
+      -- pulse)
+      ppulse_o : out std_logic   -- positive edge detect output (single-clock
+     -- pulse)
+      );
+  end component gc_sync_ffs;
+
  --============================================================================
  -- Signal declarations
  --============================================================================
  signal glitch_filt : std_logic_vector(g_len downto 0);
-  signal degl_dat    : std_logic;
+  signal dat_synced  : std_logic;

 --==============================================================================
 --  architecture begin
@@ -79,8 +99,20 @@ begin
  --============================================================================
  -- Glitch filtration logic
  --============================================================================
-  -- First, assign the current sample of the glitch filter
-  glitch_filt(0) <= dat_i;
+  -- First, synchronize the data input in the clk_i domain
+  cmp_sync : gc_sync_ffs
+    port map
+    (
+      clk_i    => clk_i,
+      rst_n_i  => rst_n_i,
+      data_i   => dat_i,
+      synced_o => dat_synced,
+      npulse_o => open,
+      ppulse_o => open
+    );
+  
+  -- Then, assign the current sample of the glitch filter
+  glitch_filt(0) <= dat_synced;

  -- Generate glitch filter FFs when the filter length is > 0
  gen_glitch_filt: if (g_len > 0) generate

--- a/hdl/release/syn/conv_ttl_blo.gise
+++ b/hdl/release/syn/conv_ttl_blo.gise
--- a/hdl/release/syn/run.tcl
+++ b/hdl/release/syn/run.tcl
-project open conv_ttl_blo.xise
-process run {Generate Programming File} -force rerun_all
--- a/hdl/test_pulse/syn/conv_ttl_blo.gise
+++ b/hdl/test_pulse/syn/conv_ttl_blo.gise
--- a/hdl/test_pulse/syn/run.tcl
+++ b/hdl/test_pulse/syn/run.tcl
-project open conv_ttl_blo.xise
-process run {Generate Programming File} -force rerun_all
--- a/hdl/test_regs/syn/conv_ttl_blo.bit
+++ b/hdl/test_regs/syn/conv_ttl_blo.bit
--- a/hdl/test_regs/syn/conv_ttl_blo.gise
+++ b/hdl/test_regs/syn/conv_ttl_blo.gise
--- a/hdl/test_regs/syn/conv_ttl_blo.xise
+++ b/hdl/test_regs/syn/conv_ttl_blo.xise
@@ -146,6 +146,9 @@
    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -302,6 +305,7 @@
    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>

--- a/hdl/test_regs/syn/run.tcl
+++ b/hdl/test_regs/syn/run.tcl
-project open conv_ttl_blo.xise
-process run {Generate Programming File} -force rerun_all
--- a/hdl/test_regs/top/conv_ttl_blo.vhd
+++ b/hdl/test_regs/top/conv_ttl_blo.vhd
@@ -158,8 +158,8 @@ architecture behav of conv_ttl_blo is

      -- I2C address and status
      i2c_addr_i : in  std_logic_vector(6 downto 0);
-      i2c_done_o : out std_logic;
-      i2c_err_o  : out std_logic;
+      tip_o : out std_logic;
+      err_o  : out std_logic;

      -- Wishbone master signals
      wbm_stb_o  : out std_logic;
@@ -198,8 +198,8 @@ architecture behav of conv_ttl_blo is
  signal bicolor_led_state          : std_logic_vector(23 downto 0);

  -- I2C bridge signals
-  signal i2c_done            : std_logic;
-  signal i2c_err             : std_logic;
+  signal vbcp_done            : std_logic;
+  signal vbcp_err             : std_logic;
  signal i2c_err_led         : std_logic;
  signal i2c_up              : std_logic;
  signal i2c_addr            : std_logic_vector(6 downto 0);
@@ -270,8 +270,8 @@ begin

      -- I2C address and status
      i2c_addr_i => i2c_addr,
-      i2c_done_o => i2c_done,
-      i2c_err_o  => i2c_err,
+      tip_o      => vbcp_done,
+      err_o      => vbcp_err,

      -- Wishbone master signals
      wbm_stb_o  => xbar_slave_in(0).stb,
@@ -286,7 +286,7 @@ begin
      wbm_err_i  => xbar_slave_out(0).err
    );

-  -- Process to blink the LED for a finite amount of time when the i2c_done
+  -- Process to blink the LED for a finite amount of time when the vbcp_done
  -- signal is set.
  p_i2c_blink : process(clk125)
  begin
@@ -301,7 +301,7 @@ begin

          when '0' =>
            led_i2c <= '0';
-            if (i2c_done = '1') then
+            if (vbcp_done = '1') then
              blink_state <= '1';
            end if;

@@ -333,7 +333,7 @@ begin
  if rising_edge(clk125) then
    if (rst_n = '0') then
      i2c_err_led <= '0';
-    elsif (i2c_err = '1') then
+    elsif (vbcp_err = '1') then
      i2c_err_led <= '1';
    end if;
  end if;

--- a/hdl/vbcp_wb/rtl/i2c_slave.vhd
+++ b/hdl/vbcp_wb/rtl/i2c_slave.vhd
--- a/hdl/vbcp_wb/rtl/i2c_slave_pkg.vhd
+++ b/hdl/vbcp_wb/rtl/i2c_slave_pkg.vhd
@@ -70,9 +70,10 @@ package i2c_slave_pkg is
      i2c_addr_i : in  std_logic_vector(6 downto 0);
      
      -- ACK input, should be set after done_p_o = '1'
-      -- '0' - ACK
-      -- '1' - NACK
-      ack_n_i    : in  std_logic;
+      -- (note that the bit is reversed wrt I2C ACK bit)
+      -- '1' - ACK
+      -- '0' - NACK
+      i2c_ack_i  : in  std_logic;

      -- I2C bus operation, set after address detection
      -- '0' - write

--- a/hdl/vbcp_wb/rtl/vbcp_wb.vhd
+++ b/hdl/vbcp_wb/rtl/vbcp_wb.vhd