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Conv TTL Blocking - Gateware
Commit 5e1ddca0 authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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Preparing for new folder structure 

This commit: trying .gise in .gitignore
Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent 08c03415
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hdl/glitch_filt/rtl/glitch_filt.vhd
View file @ 5e1ddca0
......@@ -9,12 +9,12 @@
--
-- version: 1.0
--
-- description:
-- description:
--
-- dependencies:
--
-- references:
--
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
......@@ -31,13 +31,14 @@
-- last changes:
-- 2013-03-12 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
-- TODO: -
--==============================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
entity glitch_filt is
generic
......@@ -52,7 +53,7 @@ entity glitch_filt is
(
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Data input
dat_i : in std_logic;
......@@ -65,11 +66,30 @@ end entity glitch_filt;
architecture behav of glitch_filt is
--============================================================================
-- Component declarations
--============================================================================
component gc_sync_ffs is
generic(
g_sync_edge : string := "positive"
);
port(
clk_i : in std_logic; -- clock from the destination clock domain
rst_n_i : in std_logic; -- reset
data_i : in std_logic; -- async input
synced_o : out std_logic; -- synchronized output
npulse_o : out std_logic; -- negative edge detect output (single-clock
-- pulse)
ppulse_o : out std_logic -- positive edge detect output (single-clock
-- pulse)
);
end component gc_sync_ffs;
--============================================================================
-- Signal declarations
--============================================================================
signal glitch_filt : std_logic_vector(g_len downto 0);
signal degl_dat : std_logic;
signal dat_synced : std_logic;
--==============================================================================
-- architecture begin
......@@ -79,8 +99,20 @@ begin
--============================================================================
-- Glitch filtration logic
--============================================================================
-- First, assign the current sample of the glitch filter
glitch_filt(0) <= dat_i;
-- First, synchronize the data input in the clk_i domain
cmp_sync : gc_sync_ffs
port map
(
clk_i => clk_i,
rst_n_i => rst_n_i,
data_i => dat_i,
synced_o => dat_synced,
npulse_o => open,
ppulse_o => open
);
-- Then, assign the current sample of the glitch filter
glitch_filt(0) <= dat_synced;
-- Generate glitch filter FFs when the filter length is > 0
gen_glitch_filt: if (g_len > 0) generate
......
hdl/release/syn/conv_ttl_blo.gise deleted 100644 → 0
View file @ 08c03415
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hdl/release/syn/run.tcl deleted 100644 → 0
View file @ 08c03415
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hdl/test_pulse/syn/conv_ttl_blo.gise deleted 100644 → 0
View file @ 08c03415
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hdl/test_pulse/syn/run.tcl deleted 100644 → 0
View file @ 08c03415
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
hdl/test_regs/syn/conv_ttl_blo.gise deleted 100644 → 0
View file @ 08c03415
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<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="conv_ttl_blo.twr"/>
<outfile xil_pn:name="conv_ttl_blo.twx"/>
</transform>
</transforms>
</generated_project>
hdl/test_regs/syn/conv_ttl_blo.xise
View file @ 5e1ddca0
......@@ -146,6 +146,9 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -302,6 +305,7 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
......
hdl/test_regs/syn/run.tcl deleted 100644 → 0
View file @ 08c03415
project open conv_ttl_blo.xise
process run {Generate Programming File} -force rerun_all
hdl/test_regs/top/conv_ttl_blo.vhd
View file @ 5e1ddca0
......@@ -49,12 +49,12 @@ entity conv_ttl_blo is
g_nr_ttl_chan : natural := 6;
g_nr_inv_chan : natural := 4
);
port
port
(
-- Clock lines
fpga_clk_p_i : in std_logic; --Using the 125MHz clock
fpga_clk_n_i : in std_logic;
-- LEDs
led_ctrl0_o : out std_logic;
led_ctrl0_oen_o : out std_logic;
......@@ -66,7 +66,7 @@ entity conv_ttl_blo is
led_wr_link_syserror_o : out std_logic;
led_wr_ok_syspw_o : out std_logic;
led_wr_ownaddr_i2c_o : out std_logic;
-- Lines for the i2c_slave
scl_i : in std_logic;
scl_o : out std_logic;
......@@ -140,7 +140,7 @@ architecture behav of conv_ttl_blo is
end component reset_gen;
-- I2C bridge
-- (use: convert I2C transfers into WB transfers on memmapped registers)
-- (use: convert I2C transfers into WB transfers on memmapped registers)
component vbcp_wb is
port
(
......@@ -158,8 +158,8 @@ architecture behav of conv_ttl_blo is
-- I2C address and status
i2c_addr_i : in std_logic_vector(6 downto 0);
i2c_done_o : out std_logic;
i2c_err_o : out std_logic;
tip_o : out std_logic;
err_o : out std_logic;
-- Wishbone master signals
wbm_stb_o : out std_logic;
......@@ -174,7 +174,7 @@ architecture behav of conv_ttl_blo is
wbm_err_i : in std_logic
);
end component vbcp_wb;
--============================================================================
-- Signal declarations
--============================================================================
......@@ -189,7 +189,7 @@ architecture behav of conv_ttl_blo is
signal xbar_slave_out : t_wishbone_slave_out_array (c_nr_masters - 1 downto 0);
signal xbar_master_in : t_wishbone_master_in_array (c_nr_slaves - 1 downto 0);
signal xbar_master_out : t_wishbone_master_out_array(c_nr_slaves - 1 downto 0);
-- RAM signals
signal ram_we : std_logic;
signal ram_ack : std_logic;
......@@ -198,8 +198,8 @@ architecture behav of conv_ttl_blo is
signal bicolor_led_state : std_logic_vector(23 downto 0);
-- I2C bridge signals
signal i2c_done : std_logic;
signal i2c_err : std_logic;
signal vbcp_done : std_logic;
signal vbcp_err : std_logic;
signal i2c_err_led : std_logic;
signal i2c_up : std_logic;
signal i2c_addr : std_logic_vector(6 downto 0);
......@@ -207,19 +207,19 @@ architecture behav of conv_ttl_blo is
signal led_i2c_clkdiv : unsigned(22 downto 0);
signal led_i2c_cnt : unsigned( 2 downto 0);
signal blink_state : std_logic;
begin
--============================================================================
-- Generate 125 MHz global signal from differential lines
--============================================================================
cmp_125_diff_buf : IBUFGDS
generic map
generic map
(
DIFF_TERM => TRUE,
IBUF_LOW_PWR => TRUE
)
port map
port map
(
I => fpga_clk_p_i,
IB => fpga_clk_n_i,
......@@ -242,7 +242,7 @@ begin
rst_i => '0',
rst_n_o => rst_n
);
-- rst <= not rst_n;
mr_n_o <= rst_n;
......@@ -251,7 +251,7 @@ begin
--============================================================================
-- Set the I2C address signal according to ELMA protocol [1]
i2c_addr <= "10" & fpga_ga_i;
-- Instantiate VBCP bridge component
cmp_i2c_bridge : vbcp_wb
port map
......@@ -270,8 +270,8 @@ begin
-- I2C address and status
i2c_addr_i => i2c_addr,
i2c_done_o => i2c_done,
i2c_err_o => i2c_err,
tip_o => vbcp_done,
err_o => vbcp_err,
-- Wishbone master signals
wbm_stb_o => xbar_slave_in(0).stb,
......@@ -285,8 +285,8 @@ begin
wbm_rty_i => xbar_slave_out(0).rty,
wbm_err_i => xbar_slave_out(0).err
);
-- Process to blink the LED for a finite amount of time when the i2c_done
-- Process to blink the LED for a finite amount of time when the vbcp_done
-- signal is set.
p_i2c_blink : process(clk125)
begin
......@@ -301,7 +301,7 @@ begin
when '0' =>
led_i2c <= '0';
if (i2c_done = '1') then
if (vbcp_done = '1') then
blink_state <= '1';
end if;
......@@ -333,7 +333,7 @@ begin
if rising_edge(clk125) then
if (rst_n = '0') then
i2c_err_led <= '0';
elsif (i2c_err = '1') then
elsif (vbcp_err = '1') then
i2c_err_led <= '1';
end if;
end if;
......@@ -406,7 +406,7 @@ begin
--============================================================================
-- Bicolor LED matrix logic
--============================================================================
-- Bicolor LED controls, corresponding to the column orders on the
-- Bicolor LED controls, corresponding to the column orders on the
-- bicolor_led_ctrl unit.
-- WR address
......@@ -443,7 +443,7 @@ begin
bicolor_led_state(19 downto 18) <= c_LED_GREEN;
-- MULTICAST 2
bicolor_led_state(21 downto 20) <= c_LED_OFF;
bicolor_led_state(21 downto 20) <= c_LED_OFF;
-- MULTICAST 3
bicolor_led_state(23 downto 22) <= c_LED_OFF;
......
hdl/vbcp_wb/rtl/i2c_slave.vhd
View file @ 5e1ddca0
......@@ -9,9 +9,9 @@
--
-- version: 1.0
--
-- description:
--
-- Simple I2C slave interface, providing the basic low-level functionality
-- description:
--
-- Simple I2C slave interface, providing the basic low-level functionality
-- of the I2C protocol.
--
-- The i2c_slave module waits for a master to initiate a transfer via
......@@ -24,7 +24,7 @@
-- For master write (slave read) transfers, the received byte can be read at
-- the rx_byte_o output when the done_p_o pin is high. For master read (slave
-- write) transfers, the slave sends the byte at the tx_byte_i input, which
-- should be set when the done_p_o output is high, either after I2C address
-- should be set when the done_p_o output is high, either after I2C address
-- reception, or a successful send of a previous byte.
--
-- dependencies:
......@@ -32,7 +32,7 @@
--
-- references:
-- [1] The I2C bus specification, version 2.1, NXP Semiconductor, Jan. 2000
-- http://www.nxp.com/documents/other/39340011.pdf
-- http://www.nxp.com/documents/other/39340011.pdf
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
......@@ -50,7 +50,7 @@
-- last changes:
-- 2013-03-13 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO:
-- TODO:
-- - Stop condition
--==============================================================================
......@@ -77,11 +77,12 @@ entity i2c_slave is
-- Slave address
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- '0' - ACK
-- '1' - NACK
ack_n_i : in std_logic;
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
i2c_ack_i : in std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
......@@ -116,17 +117,17 @@ architecture behav of i2c_slave is
--============================================================================
-- Type declarations
--============================================================================
type t_state is
type t_state is
(
ST_IDLE, -- idle
ST_STA, -- start condition received
ST_ADDR, -- shift in I2C address bits
ST_ADDR_ACK, -- ACK/NACK to I2C address
ST_RD, -- shift in byte to read
ST_RD_ACK, -- ACK/NACK to received byte
ST_WR_LOAD_TXSR, -- load byte to send via I2C
ST_WR, -- shift out byte
ST_WR_ACK -- get ACK/NACK from master
IDLE, -- idle
STA, -- start condition received
ADDR, -- shift in I2C address bits
ADDR_ACK, -- ACK/NACK to I2C address
RD, -- shift in byte to read
RD_ACK, -- ACK/NACK to received byte
WR_LOAD_TXSR, -- load byte to send via I2C
WR, -- shift out byte
WR_ACK -- get ACK/NACK from master
);
--============================================================================
......@@ -159,15 +160,22 @@ architecture behav of i2c_slave is
-- Signal declarations
--============================================================================
-- Deglitched signals and delays for SCL and SDA lines
signal scl_degl, scl_degl_d0 : std_logic;
signal sda_degl, sda_degl_d0 : std_logic;
signal scl_falling : std_logic;
signal sda_falling : std_logic;
signal sda_rising : std_logic;
signal scl_deglitched : std_logic;
signal scl_deglitched_d0 : std_logic;
signal sda_deglitched : std_logic;
signal sda_deglitched_d0 : std_logic;
signal scl_r_edge_p : std_logic;
signal scl_f_edge_p : std_logic;
signal sda_f_edge_p : std_logic;
signal sda_r_edge_p : std_logic;
-- FSM
signal state : t_state;
-- FSM tick
signal tick_p : std_logic;
signal tick_cnt : std_logic_vector(5 downto 0);
-- RX and TX shift registers
signal txsr : std_logic_vector(7 downto 0);
signal rxsr : std_logic_vector(7 downto 0);
......@@ -191,7 +199,10 @@ begin
-- No clock stretching implemented, always disable SCL line
scl_o <= '0';
scl_en_o <= '0';
-- SDA line driven low; SDA_EN line controls when the tristate buffer is enabled
sda_o <= '0';
-- Assign RX byte output
rx_byte_o <= rxsr;
......@@ -199,7 +210,7 @@ begin
-- Deglitching logic
--============================================================================
-- Generate deglitched SCL signal with 54-ns max. glitch width
cmp_scl_deglitch: glitch_filt
cmp_scl_deglitch : glitch_filt
generic map
(
g_len => 7
......@@ -209,29 +220,28 @@ begin
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => scl_i,
dat_o => scl_degl
dat_o => scl_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling-edge detection signal
p_scl_degl_d0: process(clk_i) is
p_scl_degl_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
scl_degl_d0 <= '0';
scl_falling <= '0';
scl_deglitched_d0 <= '0';
scl_f_edge_p <= '0';
scl_r_edge_p <= '0';
else
scl_degl_d0 <= scl_degl;
scl_falling <= '0';
if (scl_degl = '0') and (scl_degl_d0 = '1') then
scl_falling <= '1';
end if;
scl_deglitched_d0 <= scl_deglitched;
scl_f_edge_p <= (not scl_deglitched) and scl_deglitched_d0;
scl_r_edge_p <= scl_deglitched and (not scl_deglitched_d0);
end if;
end if;
end process p_scl_degl_d0;
-- Generate deglitched SDA signal with 54-ns max. glitch width
cmp_sda_deglitch: glitch_filt
cmp_sda_deglitch : glitch_filt
generic map
(
g_len => 7
......@@ -241,33 +251,51 @@ begin
clk_i => clk_i,
rst_n_i => rst_n_i,
dat_i => sda_i,
dat_o => sda_degl
dat_o => sda_deglitched
);
-- and create a delayed version of this signal, together with one-tick-long
-- falling- and rising-edge detection signals
p_sda_degl_d0: process(clk_i) is
p_sda_deglitched_d0 : process(clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
sda_degl_d0 <= '0';
sda_rising <= '0';
sda_falling <= '0';
sda_deglitched_d0 <= '0';
sda_f_edge_p <= '0';
sda_r_edge_p <= '0';
else
sda_degl_d0 <= sda_degl;
sda_rising <= '0';
if (sda_degl = '1') and (sda_degl_d0 = '0') then
sda_rising <= '1';
end if;
sda_falling <= '0';
if (sda_degl = '0') and (sda_degl_d0 = '1') then
sda_falling <= '1';
sda_deglitched_d0 <= sda_deglitched;
sda_f_edge_p <= (not sda_deglitched) and sda_deglitched_d0;
sda_r_edge_p <= sda_deglitched and (not sda_deglitched_d0);
end if;
end if;
end process p_sda_deglitched_d0;
--============================================================================
-- Tick generation
--============================================================================
p_tick : process (clk_i) is
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
tick_cnt <= '0';
tick_p <= '0';
elsif (scl_f_edge_p = '1') then
tick_en <= '1';
else
if (tick_en = '1') then
tick_cnt <= tick_cnt + 1;
tick_p <= '0';
if (tick_cnt = (tick_cnt'range => '1')) then
tick_p <= '1';
tick_en <= '0';
end if;
else
tick_p <= '0';
end if;
end if;
end if;
end process p_sda_degl_d0;
end process p_tick;
--============================================================================
-- FSM logic
......@@ -276,24 +304,25 @@ begin
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') or (rst_fr_watchdog = '1') then
state <= ST_IDLE;
state <= IDLE;
watchdog_rst <= '1';
bit_cnt <= (others => '0');
rxsr <= (others => '0');
txsr <= (others => '0');
sda_o <= '0';
sda_en_o <= '0';
done_p_o <= '0';
op_o <= '0';
stat_o <= c_i2cs_idle;
-- I2C start condition
elsif (sda_falling = '1') and (scl_degl = '1') then
state <= ST_STA;
elsif (sda_f_edge_p = '1') and (scl_deglitched = '1') then
state <= ADDR;
bit_cnt <= (others => '0');
watchdog_rst <= '0';
-- I2C stop condition
elsif (sda_rising = '1') and (scl_degl = '1') then
state <= ST_IDLE;
elsif (sda_r_edge_p = '1') and (scl_deglitched = '1') then
state <= IDLE;
done_p_o <= '1';
stat_o <= c_i2cs_idle;
......@@ -301,58 +330,51 @@ begin
else
case state is
---------------------------------------------------------------------
-- ST_IDLE
-- IDLE
---------------------------------------------------------------------
-- When idle, outputs and bit counters are cleared, while waiting
-- for a start condition.
---------------------------------------------------------------------
when ST_IDLE =>
when IDLE =>
bit_cnt <= (others => '0');
sda_o <= '0';
sda_en_o <= '0';
done_p_o <= '0';
watchdog_rst <= '1';
stat_o <= c_i2cs_idle;
---------------------------------------------------------------------
-- ST_STA
---------------------------------------------------------------------
-- When a start condition is received, the bit counter gets cleared
-- to prepare for receiving the address byte. On the falling edge of
-- SCL, we go into the address state.
---------------------------------------------------------------------
when ST_STA =>
watchdog_rst <= '0';
bit_cnt <= (others => '0');
if (scl_falling = '1') then
watchdog_rst <= '1';
state <= ST_ADDR;
end if;
-- ---------------------------------------------------------------------
-- -- STA
-- ---------------------------------------------------------------------
-- -- When a start condition is received, the bit counter gets cleared
-- -- to prepare for receiving the address byte. On the falling edge of
-- -- SCL, we go into the address state.
-- ---------------------------------------------------------------------
-- when STA =>
-- bit_cnt <= (others => '0');
-- if (scl_f_edge_p = '1') then
-- state <= ADDR;
-- end if;
---------------------------------------------------------------------
-- ST_ADDR
-- ADDR
---------------------------------------------------------------------
-- Shift in the seven address bits and the R/W bit, and go to address
-- acknowledgement. When the eighth bit has been shifted in, check
-- if address is ours and signal to external module. Then, go to
-- ADDR_ACK state.
---------------------------------------------------------------------
when ST_ADDR =>
-- Clear watchdog reset
watchdog_rst <= '0';
-- Shifting in is done on falling edge of SCL
if (scl_falling = '1') then
watchdog_rst <= '1';
rxsr <= rxsr(6 downto 0) & sda_degl;
bit_cnt <= bit_cnt + 1;
when ADDR =>
-- Shifting in is done on rising edge of SCL
if (scl_r_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
-- Shifted in 8 bits, go to ADDR_ACK. Check to see if received
-- address is ours and set op_o if so.
if (bit_cnt = 7) then
state <= ST_ADDR_ACK;
state <= ADDR_ACK;
if (rxsr(6 downto 0) = i2c_addr_i) then
op_o <= sda_degl;
op_o <= sda_deglitched;
done_p_o <= '1';
stat_o <= c_i2cs_addr_good;
end if;
......@@ -360,148 +382,127 @@ begin
end if;
---------------------------------------------------------------------
-- ST_ADDR_ACK
-- ADDR_ACK
---------------------------------------------------------------------
-- Here, we check to see if the address is ours and ACK/NACK
-- accordingly. The next action is dependent upon the state of the
-- R/W bit received via I2C.
---------------------------------------------------------------------
when ST_ADDR_ACK =>
-- Clear watchdog reset
watchdog_rst <= '0';
when ADDR_ACK =>
-- Clear done pulse
done_p_o <= '0';
-- we write the ACK bit, so enable output
sda_en_o <= '1';
sda_en_o <= i2c_ack_i;
-- If the received address is ours, send the ACK set by external
-- module and, on the falling edge of SCL, go to appropriate state
-- module and, on the falling edge of SCL, go to appropriate state
-- based on R/W bit.
if (rxsr(7 downto 1) = i2c_addr_i) then
sda_o <= ack_n_i;
if (scl_falling = '1') then
watchdog_rst <= '1';
if (scl_f_edge_p = '1') then
sda_en_o <= '0';
if (rxsr(0) = '0') then
state <= ST_RD;
state <= RD;
else
state <= ST_WR_LOAD_TXSR;
state <= WR_LOAD_TXSR;
end if;
end if;
-- If received address is not ours, NACK and go back to IDLE
else
sda_en_o <= '0';
state <= ST_IDLE;
state <= IDLE;
end if;
---------------------------------------------------------------------
-- ST_RD
-- RD
---------------------------------------------------------------------
-- Shift in bits sent by the master.
---------------------------------------------------------------------
when ST_RD =>
-- Clear watchdog reset
watchdog_rst <= '0';
when RD =>
-- Shifting occurs on falling edge of SCL
if (scl_falling = '1') then
watchdog_rst <= '1';
rxsr <= rxsr(6 downto 0) & sda_degl;
if (scl_f_edge_p = '1') then
rxsr <= rxsr(6 downto 0) & sda_deglitched;
bit_cnt <= bit_cnt + 1;
-- Received 8 bits, go to RD_ACK and signal external module
if (bit_cnt = 7) then
state <= ST_RD_ACK;
state <= RD_ACK;
done_p_o <= '1';
stat_o <= c_i2cs_rd_done;
end if;
end if;
---------------------------------------------------------------------
-- ST_RD_ACK
-- RD_ACK
---------------------------------------------------------------------
-- Send ACK/NACK, as received from external command
---------------------------------------------------------------------
when ST_RD_ACK =>
-- Clear watchdog reset
watchdog_rst <= '0';
when RD_ACK =>
-- Clear done pulse
done_p_o <= '0';
-- we write the ACK bit, so enable output and send the ACK bit
sda_en_o <= '1';
sda_o <= ack_n_i;
sda_en_o <= i2c_ack_i;
-- based on the ACK received by external command, we read the next
-- bit (ACK) or go back to idle state (NACK)
if (scl_falling = '1') then
watchdog_rst <= '1';
if (scl_f_edge_p = '1') then
sda_en_o <= '0';
if (ack_n_i = '0') then
state <= ST_RD;
if (i2c_ack_i = '1') then
state <= RD;
else
state <= ST_IDLE;
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- ST_WR_LOAD_TXSR
-- WR_LOAD_TXSR
---------------------------------------------------------------------
-- Load TXSR with the input value.
---------------------------------------------------------------------
when ST_WR_LOAD_TXSR =>
when WR_LOAD_TXSR =>
txsr <= tx_byte_i;
state <= ST_WR;
state <= WR;
---------------------------------------------------------------------
-- ST_WR
-- WR
---------------------------------------------------------------------
-- Shift out the eight bits of TXSR.
---------------------------------------------------------------------
when ST_WR =>
watchdog_rst <= '0';
when WR =>
-- slave writes, so enable output
sda_en_o <= '1';
sda_o <= txsr(7);
sda_en_o <= txsr(7);
-- Shift TXSR on falling edge of SCL
if (scl_falling = '1') then
watchdog_rst <= '1';
txsr <= txsr(6 downto 0) & '0';
bit_cnt <= bit_cnt + 1;
if (scl_f_edge_p = '1') then
txsr <= txsr(6 downto 0) & '0';
bit_cnt <= bit_cnt + 1;
-- Eight bits sent, disable SDA end go to WR_ACK
if (bit_cnt = 7) then
sda_en_o <= '0';
state <= ST_WR_ACK;
state <= WR_ACK;
done_p_o <= '1';
stat_o <= c_i2cs_wr_done;
end if;
end if;
---------------------------------------------------------------------
-- ST_WR_ACK
-- WR_ACK
---------------------------------------------------------------------
-- The master drives the ACK bit here, so on the falling edge of
-- SCL, we check the ack bit. A '0' (ACK) means more bits should be sent,
-- so we load the next value of the TXSR. A '1' (NACK) means the
-- master is done reading and a STO follows, so we go back to IDLE
-- so we load the next value of the TXSR. A '1' (NACK) means the
-- master is done reading and a STO follows, so we go back to IDLE
-- state.
---------------------------------------------------------------------
when ST_WR_ACK =>
watchdog_rst <= '0';
when WR_ACK =>
done_p_o <= '0';
if (scl_falling = '1') then
watchdog_rst <= '1';
if (sda_degl = '0') then
state <= ST_WR_LOAD_TXSR;
if (scl_f_edge_p = '1') then
if (sda_deglitched = '0') then
state <= WR_LOAD_TXSR;
else
state <= ST_IDLE;
state <= IDLE;
end if;
end if;
......@@ -509,7 +510,7 @@ begin
-- Any other state: go back to idle.
---------------------------------------------------------------------
when others =>
state <= ST_IDLE;
state <= IDLE;
end case;
end if;
......@@ -518,9 +519,9 @@ begin
--============================================================================
-- Watchdog counter process
-- Resets the FSM after one second. The watchdog_rst signal is controlled by
-- the FSM and resets the watchdog if the I2C master still controls the
-- slave, signaled by the SCL line going low. If for one second the master
-- Resets the FSM after one second. The watchdog_rst signal is controlled by
-- the FSM and resets the watchdog if the I2C master still controls the
-- slave, signaled by the SCL line going low. If for one second the master
-- does not toggle the SCL line, the FSM gets reset.
--============================================================================
p_watchdog: process(clk_i)
......
hdl/vbcp_wb/rtl/i2c_slave_pkg.vhd
View file @ 5e1ddca0
......@@ -70,9 +70,10 @@ package i2c_slave_pkg is
i2c_addr_i : in std_logic_vector(6 downto 0);
-- ACK input, should be set after done_p_o = '1'
-- '0' - ACK
-- '1' - NACK
ack_n_i : in std_logic;
-- (note that the bit is reversed wrt I2C ACK bit)
-- '1' - ACK
-- '0' - NACK
i2c_ack_i : in std_logic;
-- I2C bus operation, set after address detection
-- '0' - write
......
hdl/vbcp_wb/rtl/vbcp_wb.vhd
View file @ 5e1ddca0
......@@ -9,16 +9,16 @@
--
-- version: 1.0
--
-- description:
-- description:
-- This module implements an I2C to Wishbone bridge for VME64x crates,
-- following the protocol defined in [1]. It uses a low-level I2C slave module
-- reacting to transfers initiated by an I2C master, in this case, a VME64x
-- system monitor (SysMon) [2].
--
-- The I2C slave module sets its done_p_o pin high when the I2C address received
-- from the SysMon corresponds to the slave address and every time a byte has
-- The I2C slave module sets its done_p_o pin high when the I2C address received
-- from the SysMon corresponds to the slave address and every time a byte has
-- been received or sent correctly. The done_p_o pin of the slave module is
-- de-asserted when the slave performs a transfer.
-- de-asserted when the slave performs a transfer.
--
-- The bridge module employs a state machine that checks for low-to-high
-- transitions in the slave done_p_o pin and shifts bytes in and out over I2C
......@@ -32,7 +32,7 @@
-- http://www.ohwr.org/documents/227
-- [2] System Monitor's Users Manual
-- http://www.ohwr.org/documents/226
--
--
--==============================================================================
-- GNU LESSER GENERAL PUBLIC LICENSE
--==============================================================================
......@@ -49,7 +49,7 @@
-- last changes:
-- 2013-02-28 Theodor Stana t.stana@cern.ch File created
--==============================================================================
-- TODO: -
-- TODO: -
--==============================================================================
library ieee;
......@@ -106,21 +106,21 @@ architecture behav of vbcp_wb is
--============================================================================
type t_state is
(
ST_IDLE, -- idle state
ST_WB_ADR, -- get the WB register address
ST_SIM_WB_TRANSF, -- simulate a WB transfer with the received address
ST_OP, -- operation to perform on the WB register
ST_SYSMON_RD_WB, -- perform a WB read transfer, for sending word to the SysMon
ST_SYSMON_RD, -- send the word to the SysMon during read transfer
ST_SYSMON_WR, -- read the word sent by the SysMon during write transfer
ST_SYSMON_WR_WB -- perform a WB write transfer, storing the received word
IDLE, -- idle state
SYSMON_WB_ADR, -- get the WB register address
SIM_WB_TRANSF, -- simulate a WB transfer with the received address
OPER, -- operation to perform on the WB register
SYSMON_RD_WB, -- perform a WB read transfer, for sending word to the SysMon
SYSMON_RD, -- send the word to the SysMon during read transfer
SYSMON_WR, -- read the word sent by the SysMon during write transfer
SYSMON_WR_WB -- perform a WB write transfer, storing the received word
);
--============================================================================
-- Signal declarations
--============================================================================
-- Slave component signals
signal ack_n : std_logic;
signal i2c_ack : std_logic;
signal op : std_logic;
signal start_op : std_logic;
signal tx_byte : std_logic_vector(7 downto 0);
......@@ -170,7 +170,7 @@ begin
-- ACK input, should be set after done_p_o = '1'
-- '0' - ACK
-- '1' - NACK
ack_n_i => ack_n,
i2c_ack_i => i2c_ack,
-- I2C bus operation, set after address detection
-- '0' - write
......@@ -219,7 +219,7 @@ begin
begin
if rising_edge(clk_i) then
if (rst_n_i = '0') then
state <= ST_IDLE;
state <= IDLE;
wb_adr <= (others => '0');
wb_dat_out <= (others => '0');
wb_dat_in <= (others => '0');
......@@ -227,7 +227,7 @@ begin
wb_stb <= '0';
wb_we <= '0';
start_op <= '0';
ack_n <= '0';
i2c_ack <= '0';
tip_o <= '0';
err_o <= '0';
adr_byte_cnt <= (others => '0');
......@@ -236,7 +236,7 @@ begin
else
case state is
---------------------------------------------------------------------
-- ST_IDLE
-- IDLE
---------------------------------------------------------------------
-- After the slave acknowledges its I2C address, the register address
-- bytes have to be shifted in. The start-of-transfer operation
......@@ -244,61 +244,64 @@ begin
-- the protocol. At this point, since the SysMon writes the WB
-- address, start_op will be '0' (write).
---------------------------------------------------------------------
when ST_IDLE =>
err_o <= '0';
tip_o <= '0';
ack_n <= '0';
when IDLE =>
err_o <= '0';
tip_o <= '0';
i2c_ack <= '0';
dat_byte_cnt <= (others => '0');
if (done = '1') and (stat = c_i2cs_addr_good) then
tip_o <= '1';
state <= ST_WB_ADR;
i2c_ack <= '1';
state <= SYSMON_WB_ADR;
start_op <= op;
end if;
---------------------------------------------------------------------
-- ST_WB_ADR
-- SYSMON_WB_ADR
---------------------------------------------------------------------
-- Shift in the two address bytes sent by the master and ACK each of
-- Shift in the two address bytes sent by the SysMon and ACK each of
-- them. The second byte's ACK is also controlled by the next state.
---------------------------------------------------------------------
when ST_WB_ADR =>
when SYSMON_WB_ADR =>
if (done = '1') then
if (stat = c_i2cs_rd_done) then
wb_adr <= wb_adr(7 downto 0) & rx_byte;
ack_n <= '0';
i2c_ack <= '1';
adr_byte_cnt <= adr_byte_cnt + 1;
if (adr_byte_cnt = 1) then
state <= ST_SIM_WB_TRANSF;
state <= SIM_WB_TRANSF;
end if;
else
state <= ST_IDLE;
i2c_ack <= '0';
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- ST_SIM_WB_TRANSF
-- SIM_WB_TRANSF
---------------------------------------------------------------------
-- Simulate a Wishbone transfer with the received address and go
-- to operation state if we get a WB ACK, or back to idle if we get
-- a WB error. In the latter case, an NACK is sent to the SysMon.
---------------------------------------------------------------------
when ST_SIM_WB_TRANSF =>
when SIM_WB_TRANSF =>
wb_cyc <= '1';
wb_stb <= '1';
if (wb_ack = '1') then
ack_n <= '0';
wb_cyc <= '0';
wb_stb <= '0';
state <= ST_OP;
i2c_ack <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= OPER;
elsif (wb_err = '1') then
err_o <= '1';
ack_n <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= ST_IDLE;
err_o <= '1';
i2c_ack <= '0';
wb_cyc <= '0';
wb_stb <= '0';
state <= IDLE;
end if;
---------------------------------------------------------------------
-- ST_OP
-- OPER
---------------------------------------------------------------------
-- This is the third I2C transfer occuring in the protocol. At this
-- point, the first byte of a SysMon write transfer is sent, or a
......@@ -313,48 +316,51 @@ begin
-- If a read transfer follows, the data byte counter and WB data
-- output are cleared to avoid conflicts with future transfers.
---------------------------------------------------------------------
when ST_OP =>
when OPER =>
if (done = '1') then
if (stat = c_i2cs_rd_done) then
wb_dat_out <= rx_byte & wb_dat_out(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
ack_n <= '0';
state <= ST_SYSMON_WR;
i2c_ack <= '1';
state <= SYSMON_WR;
elsif (stat = c_i2cs_addr_good) and (op /= start_op) then
state <= ST_SYSMON_RD_WB;
i2c_ack <= '1';
state <= SYSMON_RD_WB;
else
state <= ST_IDLE;
i2c_ack <= '0';
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- ST_SYSMON_WR
-- SYSMON_WR
---------------------------------------------------------------------
-- During write transfers, each byte is shifted in, until all bytes
-- in the transfer have been sent. When this has occured, a Wishbone
-- write transfer is initiated in the next state.
---------------------------------------------------------------------
when ST_SYSMON_WR =>
when SYSMON_WR =>
if (done = '1') then
if (stat = c_i2cs_rd_done) then
wb_dat_out <= rx_byte & wb_dat_out(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
ack_n <= '0';
i2c_ack <= '1';
if (dat_byte_cnt = 3) then
state <= ST_SYSMON_WR_WB;
state <= SYSMON_WR_WB;
end if;
else
state <= ST_IDLE;
i2c_ack <= '0';
state <= IDLE;
end if;
end if;
---------------------------------------------------------------------
-- ST_SYSMON_WR_WB
-- SYSMON_WR_WB
---------------------------------------------------------------------
-- Perform a write transfer over Wishbone bus with the received
-- data word.
---------------------------------------------------------------------
when ST_SYSMON_WR_WB =>
when SYSMON_WR_WB =>
wb_cyc <= '1';
wb_stb <= '1';
wb_we <= '1';
......@@ -362,50 +368,52 @@ begin
wb_cyc <= '0';
wb_stb <= '0';
wb_we <= '0';
state <= ST_SYSMON_WR; --ST_IDLE;
state <= SYSMON_WR; --IDLE;
elsif (wb_err = '1') then
err_o <= '1';
state <= ST_IDLE;
err_o <= '1';
state <= IDLE;
end if;
---------------------------------------------------------------------
-- ST_SYSMON_RD_WB
-- SYSMON_RD_WB
---------------------------------------------------------------------
-- This state is reached from the operation state; here, we perform
-- a read transfer on the Wishbone bus to prepare the data that
-- should be sent to the SysMon. If the WB address is incorrect, we
-- go back to the IDLE state.
---------------------------------------------------------------------
when ST_SYSMON_RD_WB =>
when SYSMON_RD_WB =>
wb_cyc <= '1';
wb_stb <= '1';
if (wb_ack = '1') then
wb_dat_in <= wbm_dat_i;
wb_cyc <= '0';
wb_stb <= '0';
state <= ST_SYSMON_RD;
state <= SYSMON_RD;
elsif (wb_err = '1') then
err_o <= '1';
wb_cyc <= '0';
wb_stb <= '0';
state <= ST_IDLE;
state <= IDLE;
end if;
---------------------------------------------------------------------
-- ST_SYSMON_RD
-- SYSMON_RD
---------------------------------------------------------------------
-- Shift out the bytes over I2C and go back to IDLE state.
---------------------------------------------------------------------
when ST_SYSMON_RD =>
when SYSMON_RD =>
if (done = '1') then
if (stat = c_i2cs_wr_done) then
wb_dat_in <= x"00" & wb_dat_in(31 downto 8);
wb_dat_in <= x"00" & wb_dat_in(31 downto 8);
dat_byte_cnt <= dat_byte_cnt + 1;
i2c_ack <= '1';
if (dat_byte_cnt = 3) then
state <= ST_IDLE;
state <= IDLE;
end if;
else
state <= ST_IDLE;
i2c_ack <= '0';
state <= IDLE;
end if;
end if;
......@@ -413,7 +421,7 @@ begin
-- Any other state: go back to idle.
---------------------------------------------------------------------
when others =>
state <= ST_IDLE;
state <= IDLE;
end case;
end if;
......
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