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Conv TTL Blocking - Gateware
Commit 43db528f authored by Theodor-Adrian Stana's avatar Theodor-Adrian Stana
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doc: Change max. pulse frequency, substitute FIFO with ring buffer 

Signed-off-by: Theodor-Adrian Stana's avatarTheodor Stana <t.stana@cern.ch>
parent cc71e6a0
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doc/hdlguide/cern-title.tex
View file @ 43db528f
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
\hfill Gateware v2.0 \hfill Gateware v2.0
\hfill February 14, 2014 \hfill March 26, 2014
\vspace*{3cm} \vspace*{3cm}
......
doc/hdlguide/conv-regs.tex
View file @ 43db528f
\subsection{Converter board registers} \subsection{Converter board registers}
\label{app:conv-regs} \label{app:conv-regs}
Base address: 0x000 Base address: 0xf{}f{}f{}f{}f{}f{}f{}f
{ {
\rowcolors{2}{white}{gray!25} \rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.45\textwidth}} \begin{longtable}{l l l p{.5\textwidth}}
\hline \hline
\textbf{Offset} & \textbf{Default} & \textbf{Name} \textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\ & \textbf{Description} \\
\hline \hline
\endfirsthead \endfirsthead
...@@ -15,27 +15,27 @@ Base address: 0x000 ...@@ -15,27 +15,27 @@ Base address: 0x000
\endhead \endhead
\hline \hline
\endfoot \endfoot
0x0 & 0x54424c4f & BIDR & Board ID Register\\ 0x0 & 0x54424c4f & BIDR & Board ID Register\\
0x4 & Undefined (1) & SR & Status Register\\ 0x4 & (1) & SR & Status Register\\
0x8 & 0x00000000 & CR & Control Register\\ 0x8 & 0x00000000 & CR & Control Register\\
0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\ 0xc & 0x00000000 & CH1PCR & Channel 1 Pulse Counter Register\\
0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\ 0x10 & 0x00000000 & CH2PCR & Channel 2 Pulse Counter Register\\
0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\ 0x14 & 0x00000000 & CH3PCR & Channel 3 Pulse Counter Register\\
0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\ 0x18 & 0x00000000 & CH4PCR & Channel 4 Pulse Counter Register\\
0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\ 0x1c & 0x00000000 & CH5PCR & Channel 5 Pulse Counter Register\\
0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\ 0x20 & 0x00000000 & CH6PCR & Channel 6 Pulse Counter Register\\
0x24 & 0x00000000 & TVLR & Time Value Low Register\\ 0x24 & 0x00000000 & TVLR & Time Value Low Register\\
0x28 & 0x00000000 & TVHR & Time Value High Register\\ 0x28 & 0x00000000 & TVHR & Time Value High Register\\
0x2c & 0x00000000 & TFMR & Tag FIFO Meta Register\\ 0x2c & 0x00000000 & TBMR & Tag Buffer Meta Register\\
0x30 & 0x00000000 & TFCYR & Tag FIFO Cycles Register \\ 0x30 & 0x00000000 & TBCYR & Tag Buffer Cycles Register\\
0x34 & 0x00000000 & TFTLR & Tag FIFO TAI Low Register \\ 0x34 & 0x00000000 & TBTLR & Tag Buffer TAI Low Register\\
0x38 & 0x00000000 & TFTHR & Tag FIFO TAI High Register \\ 0x38 & 0x00000000 & TBTHR & Tag Buffer TAI High Register\\
0x3c & 0x00020000 & TFCSR & Tag FIFO Control and Status Register \\ 0x3c & 0x00020000 & TBCSR & Tag Buffer Control and Status Register\\
\end{longtable} \end{longtable}
} }
\noindent Note 1: The SR is undefined on startup due to the fact that the \noindent Note (1): The reset value of the SR cannot be specified, since it is based on the
gateware version, switches and RTM fields may have different values. gateware version, the state of the on-board switches and whether an RTM is plugged in or not.
\vspace{11pt} \vspace{11pt}
\subsubsection{BIDR -- Board ID Register} \subsubsection{BIDR -- Board ID Register}
...@@ -47,19 +47,19 @@ gateware version, switches and RTM fields may have different values. ...@@ -47,19 +47,19 @@ gateware version, switches and RTM fields may have different values.
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[31:24]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[31:24]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[23:16]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[23:16]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[15:8]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[15:8]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}BITS[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}BIDR[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -176,14 +176,14 @@ WRPRES ...@@ -176,14 +176,14 @@ WRPRES
RST\_UNLOCK RST\_UNLOCK
} [\emph{read/write}]: Reset unlock bit } [\emph{read/write}]: Reset unlock bit
\\ \\
1 - Reset bit unlocked \\ 0 - Reset bit locked 1 -- Reset bit unlocked \\ 0 -- Reset bit locked
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
RST RST
} [\emph{read/write}]: Reset bit } [\emph{read/write}]: Reset bit
\\ \\
1 - initiate logic reset \\ 0 - no reset 1 -- initiate logic reset \\ 0 -- no reset
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
...@@ -496,8 +496,9 @@ Writing this field resets the internal cycles counter. ...@@ -496,8 +496,9 @@ Writing this field resets the internal cycles counter.
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\end{itemize} \end{itemize}
\subsubsection{TFMR -- Tag FIFO Meta Register} \vspace{11pt}
\label{app:conv-regs-tfmr} \subsubsection{TBMR -- Tag Buffer Meta Register}
\label{app:conv-regs-tbmr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -540,9 +541,13 @@ WRTAG ...@@ -540,9 +541,13 @@ WRTAG
\item \begin{small} \item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\item \begin{small}
\textbf{A read from this register advances the buffer read pointer, if the ring buffer is not empty}
\end{small}
\end{itemize} \end{itemize}
\subsubsection{TFCYR -- Tag FIFO Cycles Register} \vspace{11pt}
\label{app:conv-regs-tfcyr} \subsubsection{TBCYR -- Tag Buffer Cycles Register}
\label{app:conv-regs-tbcyr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -550,19 +555,19 @@ WRTAG ...@@ -550,19 +555,19 @@ WRTAG
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}CYC[27:24]}\\ \multicolumn{1}{|c}{-} & - & - & - & \multicolumn{4}{|c|}{\cellcolor{gray!25}TBCYR[27:24]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[23:16]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[23:16]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[15:8]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[15:8]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}CYC[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}TBCYR[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -570,7 +575,7 @@ WRTAG ...@@ -570,7 +575,7 @@ WRTAG
\begin{itemize} \begin{itemize}
\item \begin{small} \item \begin{small}
{\bf {\bf
CYC TBCYR
} [\emph{read-only}]: Cycles counter } [\emph{read-only}]: Cycles counter
\\ \\
Value of the 8-ns cycles counter when time tag was taken. Value of the 8-ns cycles counter when time tag was taken.
...@@ -579,8 +584,9 @@ Value of the 8-ns cycles counter when time tag was taken. ...@@ -579,8 +584,9 @@ Value of the 8-ns cycles counter when time tag was taken.
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\end{itemize} \end{itemize}
\subsubsection{TFTLR -- Tag FIFO TAI Low Register } \vspace{11pt}
\label{app:conv-regs-tftlr} \subsubsection{TBTLR -- Tag Buffer TAI Low Register}
\label{app:conv-regs-tbtlr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -588,19 +594,19 @@ Value of the 8-ns cycles counter when time tag was taken. ...@@ -588,19 +594,19 @@ Value of the 8-ns cycles counter when time tag was taken.
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\ 31 & 30 & 29 & 28 & 27 & 26 & 25 & 24\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[31:24]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[31:24]}\\
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[23:16]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[23:16]}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[15:8]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[15:8]}\\
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_L[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}TBTLR[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -608,7 +614,7 @@ Value of the 8-ns cycles counter when time tag was taken. ...@@ -608,7 +614,7 @@ Value of the 8-ns cycles counter when time tag was taken.
\begin{itemize} \begin{itemize}
\item \begin{small} \item \begin{small}
{\bf {\bf
TAI\_L TBTLR
} [\emph{read-only}]: Lower part of TAI seconds counter } [\emph{read-only}]: Lower part of TAI seconds counter
\\ \\
Value of the TAI seconds counter bits 31..0 when time tag was taken. Value of the TAI seconds counter bits 31..0 when time tag was taken.
...@@ -617,10 +623,11 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken. ...@@ -617,10 +623,11 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\end{itemize} \end{itemize}
\subsubsection{TFTHR -- Tag FIFO TAI High Register}
\label{app:conv-regs-tfthr}
\vspace{11pt} \vspace{11pt}
\subsubsection{TBTHR -- Tag Buffer TAI High Register}
\label{app:conv-regs-tbthr}
%\vspace{11pt}
\noindent \noindent
\resizebox{\textwidth}{!}{ \resizebox{\textwidth}{!}{
\begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} } \begin{tabular}{>{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} >{\centering\arraybackslash}p{1.5cm} }
...@@ -638,7 +645,7 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken. ...@@ -638,7 +645,7 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\hline \hline
7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\ 7 & 6 & 5 & 4 & 3 & 2 & 1 & 0\\
\hline \hline
\multicolumn{8}{|c|}{\cellcolor{gray!25}TAI\_H[7:0]}\\ \multicolumn{8}{|c|}{\cellcolor{gray!25}TBTHR[7:0]}\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -646,7 +653,7 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken. ...@@ -646,7 +653,7 @@ Value of the TAI seconds counter bits 31..0 when time tag was taken.
\begin{itemize} \begin{itemize}
\item \begin{small} \item \begin{small}
{\bf {\bf
TAI\_H TBTHR
} [\emph{read-only}]: Upper part of TAI seconds counter } [\emph{read-only}]: Upper part of TAI seconds counter
\\ \\
Value of the TAI seconds counter bits 39..32 when time tag was taken. Value of the TAI seconds counter bits 39..32 when time tag was taken.
...@@ -655,8 +662,9 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken. ...@@ -655,8 +662,9 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken.
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
\end{small} \end{small}
\end{itemize} \end{itemize}
\subsubsection{TFCSR -- Tag FIFO Control and Status Register } \vspace{11pt}
\label{app:conv-regs-tfcsr} \subsubsection{TBCSR -- Tag Buffer Control and Status Register}
\label{app:conv-regs-tbcsr}
\vspace{11pt} \vspace{11pt}
\noindent \noindent
...@@ -668,7 +676,7 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken. ...@@ -668,7 +676,7 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken.
\hline \hline
23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\ 23 & 22 & 21 & 20 & 19 & 18 & 17 & 16\\
\hline \hline
\multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLEAR\_BUS} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\ \multicolumn{1}{|c}{-} & - & - & - & - & \multicolumn{1}{|c|}{\cellcolor{gray!25}CLR} & \multicolumn{1}{|c|}{\cellcolor{gray!25}EMPTY} & \multicolumn{1}{|c|}{\cellcolor{gray!25}FULL}\\
\hline \hline
15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\ 15 & 14 & 13 & 12 & 11 & 10 & 9 & 8\\
\hline \hline
...@@ -684,33 +692,31 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken. ...@@ -684,33 +692,31 @@ Value of the TAI seconds counter bits 39..32 when time tag was taken.
\begin{itemize} \begin{itemize}
\item \begin{small} \item \begin{small}
{\bf {\bf
FULL USEDW
} [\emph{read-only}]: FIFO full flag } [\emph{read-only}]: Buffer counter
\\ \\
1: FIFO is full\\0: FIFO is not full Number of samples in the ring buffer
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
EMPTY FULL
} [\emph{read-only}]: FIFO empty flag } [\emph{read-only}]: Buffer full
\\ \\
1: FIFO is empty\\0: FIFO is not empty 1 -- buffer full \\ 0 -- buffer is not full
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
CLEAR\_BUS EMPTY
} [\emph{write-only}]: FIFO clear } [\emph{read-only}]: Buffer empty
\\ \\
write 1: clears FIFO \\write 0: no effect\\ 1 -- buffer empty\\ 0 -- buffer is not empty
Note that a clear will not delete the data in the FIFO, just bring the
read and write pointers at the same position.\\
\end{small} \end{small}
\item \begin{small} \item \begin{small}
{\bf {\bf
USEDW CLR
} [\emph{read-only}]: FIFO counter } [\emph{write-only}]: Clear tag buffer
\\ \\
Number of data records currently being stored in FIFO. 1 -- clear\\ 0 -- no effect
\end{small} \end{small}
\item \begin{small} \item \begin{small}
\textbf{Unimplemented bits}: write as '0', read undefined \textbf{Unimplemented bits}: write as '0', read undefined
......
doc/hdlguide/fig/timetag-arch.svg
View file @ 43db528f
...@@ -9,8 +9,8 @@ ...@@ -9,8 +9,8 @@
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doc/hdlguide/hdlguide-conv-ttl-blo.tex
View file @ 43db528f
...@@ -66,6 +66,8 @@ ...@@ -66,6 +66,8 @@
14-02-2014 & 2.00 & Version 2.0 of gateware, with diagnostics support including: unique board ID 14-02-2014 & 2.00 & Version 2.0 of gateware, with diagnostics support including: unique board ID
and temperature readout, input pulse counters, pulse time-tagging and and temperature readout, input pulse counters, pulse time-tagging and
manual pulse triggering. \\ manual pulse triggering. \\
26-03-2014 & 2.10 & Version 2.1 of gateware, bringing down the max. allowed pulse frequency
to 1.6~kHz and changing the pulse timetag FIFO for a timetag buffer\\
\hline \hline
\end{tabular} \end{tabular}
} }
...@@ -91,6 +93,7 @@ IC & Integrated Circuit \\ ...@@ -91,6 +93,7 @@ IC & Integrated Circuit \\
I$^2$C & Inter-Integrated Circuit (bus) \\ I$^2$C & Inter-Integrated Circuit (bus) \\
PLL & Phase-Locked Loop \\ PLL & Phase-Locked Loop \\
RTM & Rear-Transition Module \\ RTM & Rear-Transition Module \\
RAM & Random-Access Memory \\
SPI & Serial Peripheral Interface \\ SPI & Serial Peripheral Interface \\
SysMon & (ELMA) System Montior \\ SysMon & (ELMA) System Montior \\
VCXO & Voltage-controlled oscillator \\ VCXO & Voltage-controlled oscillator \\
...@@ -482,8 +485,9 @@ selection signals to these multiplexers are set throughout the logic. ...@@ -482,8 +485,9 @@ selection signals to these multiplexers are set throughout the logic.
{ {
\begin{tabular}{l l l} \begin{tabular}{l l l}
\hline \hline
\textbf{Entity} & \textit{conv\_pulse\_gen} & \\ \textbf{Entity} & \textit{ctblo\_pulse\_gen} & \\
\textbf{Generics} & \textit{g\_pwidth} & Width of the output pulse in \textit{clk\_i} cycles \\ \textbf{Generics} & \textit{g\_pwidth} & Width of the output pulse in \textit{clk\_i} cycles \\
& \textit{g\_duty\_cycle\_div} & Duty cycle divider ratio \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\ \textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\ & \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{en\_i} & Pulse generator enable \\ & \textit{en\_i} & Pulse generator enable \\
...@@ -567,7 +571,8 @@ state of the rising-edge detector on the FSM input. ...@@ -567,7 +571,8 @@ state of the rising-edge detector on the FSM input.
After the pulse generation period, the FSM goes into a pulse rejection state, After the pulse generation period, the FSM goes into a pulse rejection state,
where the pulse reset is kept high. If any pulses arrive on the input while the FSM where the pulse reset is kept high. If any pulses arrive on the input while the FSM
is in this rejection state, they are not replicated at the output. The pulse rejection is in this rejection state, they are not replicated at the output. The pulse rejection
phase lasts for 4*\textit{g\_pwidth}, yielding a maximum duty cycle of 1/5 for input pulses. phase lasts for \textit{g\_duty\_cycle\_div}*\textit{g\_pwidth}, yielding a maximum duty
cycle of 1/\textit{g\_duty\_cycle\_div} for input pulses.
Note that due to the fact that the counter starts counting up from zero and delays Note that due to the fact that the counter starts counting up from zero and delays
in the glitch filter when it is enabled, the maximum value of the internal counter is not in the glitch filter when it is enabled, the maximum value of the internal counter is not
...@@ -731,94 +736,103 @@ state (Figure~\ref{fig:man-trig-fsm}). ...@@ -731,94 +736,103 @@ state (Figure~\ref{fig:man-trig-fsm}).
\section{Pulse time-tagging} \section{Pulse time-tagging}
\label{sec:timetag} \label{sec:timetag}
\centerline The time-tagging architecture is shown in Figure~\ref{fig:timetag-arch}. There are two
{ clock domains in the design. The time-tag controller and the time from the WRPC are both
\begin{tabular}{l l p{.5\textwidth}} in the 125~MHz clock domain, while the ring buffer is in both the 20~MHz clock domain and
\hline the 125~MHz clock domain.
\textbf{Entity} & \textit{pulse\_timetag} & \\
\textbf{Generics} & \textit{g\_clk\_rate} & Frequency in Hz of \textit{clk\_i} signal \\
& \textit{g\_nr\_chan} & Pulse repeater number of channels \\
\textbf{Ports} & \textit{clk\_i} & Clock signal \\
& \textit{rst\_n\_i} & Active-low reset signal \\
& \textit{pulse\_a\_i} & Asynchronouse pulse input \\
& \textit{wr\_tm\_cycles\_i} & Cycles counter from WRPC \\
& \textit{wr\_tm\_tai\_i} & TAI seconds counter from WRPC \\
& \textit{wr\_tm\_valid\_i} & Time from WRPC is valid \\
& \textit{wb\_tm\_tai\_l\_i} & Lower bits of TAI time counter from register \\
& \textit{wb\_tm\_tai\_l\_ld\_i} & Lower bits register write \\
& \textit{wb\_tm\_tai\_h\_i} & Upper bits of TAI time counter from register \\
& \textit{wb\_tm\_tai\_h\_ld\_i} & Upper bits register write \\
& \textit{tm\_cycles\_o} & Cycles counter to FIFO \\
& \textit{tm\_tai\_o} & TAI seconds counter to FIFO \\
& \textit{tm\_wpres\_o} & Time from WRPC is valid \\
& \textit{chan\_o} & Trigger channel to FIFO \\
& \textit{fifo\_full\_i} & FIFO status input \\
& \textit{fifo\_wr\_req\_o} & FIFO write request output, max. four clock cycles
delay after pulse rising edge \\
\hline
\end{tabular}
}
\vspace*{11pt}
A simplified view of the time-tagging architecture is shown in Figure~\ref{fig:timetag-arch}.
There are two clock domains in the design. The time-tag controller and the time from the
WRPC are both in the 125~MHz clock domain, while the \textit{conv\_regs} component is in the
20~MHz clock domain. The FIFO is asynchronous and clocked by both the 125 and 20~MHz clocks.
\begin{figure}[h] \begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/timetag-arch}} \centerline{\includegraphics[width=.9\textwidth]{fig/timetag-arch}}
\caption{Time-tag architecture} \caption{Pulse time-tagging architecture}
\label{fig:timetag-arch} \label{fig:timetag-arch}
\end{figure} \end{figure}
The time-tag controller in the figure is the \textit{pulse\_timetag} VHDL component. The timetag controller and ring buffer components are connected at the top-level. The outputs
It is designed to be connected directly to the FIFO as shown above.As opposed to what the of the ring buffer are connected directly to the \textit{conv\_regs} component at the top
simplified architecture above shows, the time-tag controller also implements the local time counters. level also.
The block's design is presented in Figure~\ref{fig:timetag-core}. This figure shows the functioning
when the \textit{pulse\_timetag} component is clocked from the 125~MHz clock, as is the case in the %======================================================================================
converter board designs. Note however that the component can work with any clock rate by changing % SUBSEC: Timetag controller
the \textit{g\_clk\_rate} generic. %======================================================================================
\subsection{Timetag controller}
\label{sec:timetag-ctrl}
The time-tag controller in Figure~\ref{fig:timetag-arch} is the \textit{conv\_pulse\_timetag}
VHDL component. It is designed to be connected directly to the ring buffer as shown above. As opposed
to what the simplified architecture above shows, the time-tag controller also implements the
local time counters.
\begin{figure}[h] \begin{figure}[h]
\centerline{\includegraphics[width=.9\textwidth]{fig/timetag-core}} \centerline{\includegraphics[width=\textwidth]{fig/timetag-core}}
\caption{Time-tag controller logic} \caption{Timetag controller logic}
\label{fig:timetag-core} \label{fig:timetag-core}
\end{figure} \end{figure}
The block's design is presented in Figure~\ref{fig:timetag-core}. This figure shows the functioning
when the \textit{conv\_pulse\_timetag} component is clocked from the 125~MHz clock, as is the case in the
converter board designs. Note however that the component can work with any clock rate by changing
the \textit{g\_clk\_rate} generic.
A free-running counter inside the block counts the ticks of the \textit{clk\_i} signal A free-running counter inside the block counts the ticks of the \textit{clk\_i} signal
to count the seconds. When it reaches the value \textit{g\_clk\_rate-1} (125~mega in to count the seconds. When it reaches the value \textit{g\_clk\_rate-1} (125~mega in
the figure), it resets and sends a "tick" to the TAI seconds counter, which then increments. the figure), it resets and sends a "tick" to the TAI seconds counter, which then increments.
As seen in Figure~\ref{fig:hdl-bd}, the pulse inputs are derived from the OR gate which As seen in Figure~\ref{fig:hdl-bd}, the pulse inputs are derived from the OR gate which
ORs together the TTL and blocking inputs. Since these pulses can be asynchronous, they ORs together the TTL and blocking inputs. Since these pulses can be asynchronous, they
are synchronized in the 125~MHz domain and passed through rising edge detectors. If the are synchronized in the 125~MHz domain and passed through rising edge detectors. A rising
FIFO is not full, a rising edge on any channel then triggers the edge on any pulse channel triggers the \textit{buf\_wr\_req\_p\_o} signal. As the port's
\textit{fifo\_wr\_req\_p\_o} output. As the port's name suggests, this signal is a one-cycle name suggests, the \textit{buf\_wr\_req\_p\_o} signal is a one-cycle pulse that triggers
pulse that triggers a write to the FIFO. a write to the ring buffer.
Note that due to the synchronization logic, rising edge detector and the latching of the All the output ports are connected externally directly to the ring buffer, therefore when the
ORed pulse rising edge detection signal, the \textit{fifo\_wr\_req\_p\_o} signal is \textit{buf\_wr\_req\_p\_o} output pulses, they are written to the ring buffer. As shown in
set between three and four cycles after the pulse signal actually arrives on the input.
All the output ports are connected externally directly to the FIFO, therefore when the
\textit{fifo\_wr\_req\_p\_o} output pulses, they are written to the FIFO. As shown in
Figure~\ref{fig:timetag-arch}, the \textit{tm\_wpres\_o} signal is also reflected in the Figure~\ref{fig:timetag-arch}, the \textit{tm\_wpres\_o} signal is also reflected in the
board status register (SR -- see Appendix~\ref{app:conv-regs-sr}). board status register (SR -- see Appendix~\ref{app:conv-regs-sr}).
The FIFO itself is generated using \textit{wbgen2}~\cite{wbgen2} and connected Note that due to the synchronization logic, rising edge detector and the latching of the
on the top-level to the \textit{pulse\_timetag} component. ORed pulse rising edge detection signal, the \textit{buf\_wr\_req\_p\_o} signal is
set between three and four cycles after the pulse signal actually arrives on the input.
Due to the two clock domains in the design, some synchronization logic is needed. This is Due to the two clock domains in the design, some synchronization logic is needed. This is
achieved via \textit{gc\_sync\_ffs} components from the \textit{general-cores} achieved via \textit{gc\_sync\_ffs} components from the \textit{general-cores}
library~\cite{gencores-ohwr} in the case of the WR time valid signals storage to the SR library~\cite{gencores-ohwr} in the case of the WR time valid signals storage to the SR
and in the case of the TAI time value load pulses from the \textit{conv\_regs} to the and in the case of the TAI time value load pulses from the \textit{conv\_regs} to the
\textit{pulse\_timetag} components. \textit{conv\_pulse\_timetag} components.
The TAI time signal is not synchronized before being connected to the \textit{conv\_regs} The TAI time signal is not synchronized before being connected to the \textit{conv\_regs}
component, since its rate of change of once per second is considered too slow to present component, since its rate of change of once per second is considered too slow to present
any problem of synchronization when read by the user. any problem of synchronization when read by the user.
%======================================================================================
% SUBSEC: Ring buffer
%======================================================================================
\subsection{Ring buffer}
\label{sec:timetag-ring-buf}
The mechanics of the ring buffer are presented in the \textbf{Ring buffer mechanics}
section of the CONV-TTL-BLO user guide~\cite{ctb-ug}. This section gives a few more details about the
implementation of the ring buffer, which can be found in the \textit{conv\_ring\_buf.vhd} file.
\begin{figure}
\centerline{\includegraphics[width=.8\textwidth]{fig/timetag-ring-buf}}
\caption{Ring buffer implementation}
\label{fig:timetag-ring-buf}
\end{figure}
A high-level view of the implementation is shown in Figure~\ref{fig:timetag-ring-buf}.
This figure is oriented towards the converter board designs, but the ring buffer is
generic and can be used in other designs by properly instantiating it.
The ring buffer is implemented via a dual-clock, asynchronous FIFO, whose purpose is to
synchronize data between the read and write clock domains, a dual-port RAM clocked
with the read clock, and control logic for the buffer RAM. In the case of the converter
board designs, the write clock is the 125~MHz clock and the read clock is the 20~MHz clock.
The buffer control logic controls when the read and write pointers get incremented and
when the empty and full signals are set. The setting of the empty and full signals are
based on a buffer count signal, which gets incremented when a write is performed and the
buffer is not full, and decremented when a read is performed and the buffer is not empty.
%====================================================================================== %======================================================================================
% SEC: Folder structure % SEC: Folder structure
%====================================================================================== %======================================================================================
...@@ -879,10 +893,10 @@ The folder structure for the project is presented below. ...@@ -879,10 +893,10 @@ The folder structure for the project is presented below.
\item Release/ \item Release/
\begin{itemize} \begin{itemize}
\item conv\_man\_trig.vhd \item conv\_man\_trig.vhd
\item conv\_pulse\_gen.vhd
\item conv\_regs.vhd \item conv\_regs.vhd
\item conv\_regs.wb \item conv\_regs.wb
\item pulse\_timetag.vhd \item conv\_pulse\_timetag.vhd
\item ctblo\_pulse\_gen.vhd
\end{itemize} \end{itemize}
\item pulsetest/ \item pulsetest/
\begin{itemize} \begin{itemize}
......
doc/hdlguide/multiboot-regs.tex
View file @ 43db528f
...@@ -6,7 +6,7 @@ Base address: 0x040 ...@@ -6,7 +6,7 @@ Base address: 0x040
\rowcolors{2}{white}{gray!25} \rowcolors{2}{white}{gray!25}
\begin{longtable}{l l l p{.5\textwidth}} \begin{longtable}{l l l p{.5\textwidth}}
\hline \hline
\textbf{Offset} & \textbf{Default} & \textbf{Name} \textbf{Offset} & \textbf{Reset} & \textbf{Name}
& \textbf{Description} \\ & \textbf{Description} \\
\hline \hline
\endfirsthead \endfirsthead
......
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