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Conv TTL Blocking - Gateware
Commit 1a34f694 authored by Denia Bouhired-Ferrag's avatar Denia Bouhired-Ferrag
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Small modification in p_inhibit_first_pulse process, now checks that all lines… 

Small modification in p_inhibit_first_pulse process, now checks that all lines are low before end of 100us first pulse inhibit period.
parent 257f2226
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sim/Release/burst_ctrl_tb.vhd
View file @ 1a34f694
...@@ -58,8 +58,17 @@ architecture behav of testbench is ...@@ -58,8 +58,17 @@ architecture behav of testbench is
-- Clock periods -- Clock periods
constant c_clk_20_per : time := 50 ns; constant c_clk_20_per : time := 50 ns;
constant random_intervals : boolean := false; constant random_intervals : boolean := false;
constant c_pgen_pwidth : natural := 5; constant c_pgen_pwidth: natural := 5;
constant c_pgen_duty_cycle_div : natural := 2; constant c_pgen_duty_cycle_div : natural := 2;
constant pwidth_sel : std_logic := '0';
constant gf_en_n :std_logic:= '0';
constant test_pgen : boolean:=false;
-- constant g_temp_decre_step_in: t_temp_decre_step := (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125);
constant g_temp_decre_step_in: t_temp_decre_step := (0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0);
-- constant g_1_pulse_temp_rise_in :unsigned (19 downto 0) := x"17700";
constant g_1_pulse_temp_rise_in :unsigned (19 downto 0) :=x"01388";
type t_time_array is array (2 downto 0) of integer;
component conv_pulse_gen is component conv_pulse_gen is
generic generic
...@@ -93,6 +102,8 @@ architecture behav of testbench is ...@@ -93,6 +102,8 @@ architecture behav of testbench is
-- Trigger input, has to be '1' to assure pulse output with delay no greater -- Trigger input, has to be '1' to assure pulse output with delay no greater
-- than internal gate delays. -- than internal gate delays.
trig_a_i : in std_logic; trig_a_i : in std_logic;
trig_r_edge_p_i : in std_logic; --synced 1 cycle-long r edge output
trig_f_edge_p_i : in std_logic; --synced 1 cycle-long f edge output
-- Pulse error output, pulses high for one clock cycle when a pulse arrives -- Pulse error output, pulses high for one clock cycle when a pulse arrives
-- within a pulse period -- within a pulse period
...@@ -128,6 +139,7 @@ end component conv_pulse_gen; ...@@ -128,6 +139,7 @@ end component conv_pulse_gen;
pulse_burst_i : in std_logic; pulse_burst_i : in std_logic;
pulse_r_edge_p_i : in std_logic; pulse_r_edge_p_i : in std_logic;
pulse_f_edge_p_i : in std_logic; pulse_f_edge_p_i : in std_logic;
temp_rise_o :out unsigned (39 downto 0);
pulse_burst_o : out std_logic; pulse_burst_o : out std_logic;
-- Burst error output, pulses high for one clock cycle when a pulse arrives -- Burst error output, pulses high for one clock cycle when a pulse arrives
...@@ -141,21 +153,41 @@ end component conv_pulse_gen; ...@@ -141,21 +153,41 @@ end component conv_pulse_gen;
-- Signal declarations -- Signal declarations
signal clk_20 : std_logic; signal clk_20 : std_logic;
signal rst : std_logic; signal rst_n : std_logic;
signal en : std_logic; signal en : std_logic;
signal burst_train_d0 : std_logic;
signal burst_train_d1 : std_logic;
-- signal burst_train_d2 : std_logic;
signal burst_train : std_logic; signal burst_train : std_logic;
signal burst_train_f_edge : std_logic; signal burst_train_f_edge : std_logic;
signal burst_train_r_edge : std_logic; signal burst_train_r_edge : std_logic;
signal burst_train_redge_in : std_logic;
signal burst_train_fedge_in : std_logic;
signal burst_train_regulated_dyn : std_logic; signal burst_train_regulated_dyn : std_logic;
signal rand_num : integer := 0; signal rand_num : integer := 0;
signal pulse_outp_err_p :std_logic; signal pulse_outp_err_p :std_logic;
signal burst_outp_err_p :std_logic; signal burst_outp_err_p :std_logic;
signal pulse_outp :std_logic; signal pulse_outp :std_logic;
signal pgen_pwidth : integer;
signal pgen_duty_cycle_div : integer;
signal temp_rise : unsigned (39 downto 0);
signal pnumber : integer;
signal period_array_lg : t_time_array;
signal period_array_sh : t_time_array;
signal pwidth_array_lg : t_time_array;
signal pwidth_array_sh : t_time_array;
signal t_start : TIME := NOW; signal t_start : TIME := NOW;
signal t_sim1 :TIME := 0 ns; signal t_sim1 :TIME := 0 ns;
signal t_sim2 :TIME := 0 ns; signal t_sim2 :TIME := 0 ns;
signal t_sim3 :TIME := 0 ns;
--============================================================================== --==============================================================================
-- architecture begin -- architecture begin
--============================================================================== --==============================================================================
...@@ -171,6 +203,8 @@ end component conv_pulse_gen; ...@@ -171,6 +203,8 @@ end component conv_pulse_gen;
--============================================================================ --============================================================================
-- Instantiate the DUT: Dynamic -- Instantiate the DUT: Dynamic
--============================================================================ --============================================================================
cmp_pulse_gen_sh : conv_pulse_gen cmp_pulse_gen_sh : conv_pulse_gen
generic map generic map
( (
...@@ -181,14 +215,15 @@ end component conv_pulse_gen; ...@@ -181,14 +215,15 @@ end component conv_pulse_gen;
port map port map
( (
clk_i => clk_20, clk_i => clk_20,
rst_n_i => rst, rst_n_i => rst_n,
gf_en_n_i => '1', gf_en_n_i => gf_en_n,
en_i => '1', en_i => '1',
trig_a_i => burst_train, trig_a_i => burst_train_d1,
trig_r_edge_p_i => burst_train_redge_in,
trig_f_edge_p_i => burst_train_fedge_in,
pulse_err_p_o => pulse_outp_err_p, pulse_err_p_o => pulse_outp_err_p,
pulse_o => pulse_outp, pulse_o => pulse_outp,
...@@ -197,31 +232,41 @@ end component conv_pulse_gen; ...@@ -197,31 +232,41 @@ end component conv_pulse_gen;
); );
cmp_dut : conv_dyn_burst_ctrl cmp_dut : conv_dyn_burst_ctrl
generic map generic map
( (
g_pwidth => c_pgen_pwidth, -- g_pwidth => c_pgen_pwidth, --
-- g_temp_decre_step => (0,0,0,0,0,0,0,0,2500,731,220,250,40,85,50,125), g_temp_decre_step => g_temp_decre_step_in,
g_temp_decre_step => (0, 0, 769, 31, 104, 14, 82, 0 ,0, 0, 0, 0, 0, 0, 0, 0), g_1_pulse_temp_rise => g_1_pulse_temp_rise_in,
g_1_pulse_temp_rise => x"01388",
-- g_1_pulse_temp_rise => x"17700", -- for 1.2us pulse
g_max_temp => x"00000F4240" --10^6 g_max_temp => x"00000F4240" --10^6
-- g_max_temp => x"02540BE400" --10^10 -- g_max_temp => x"02540BE400" --10^10
) )
port map( port map(
clk_i => clk_20, clk_i => clk_20,
rst_n_i => rst, rst_n_i => rst_n,
en_i => en, en_i => '1',
pulse_burst_i => pulse_outp, pulse_burst_i => pulse_outp,
pulse_r_edge_p_i => burst_train_r_edge, pulse_r_edge_p_i => burst_train_r_edge,
pulse_f_edge_p_i => burst_train_f_edge, pulse_f_edge_p_i => burst_train_f_edge,
temp_rise_o => temp_rise,
pulse_burst_o => burst_train_regulated_dyn, pulse_burst_o => burst_train_regulated_dyn,
burst_err_p_o => burst_outp_err_p burst_err_p_o => burst_outp_err_p
); );
cmp_sync_ffs : gc_sync_ffs
port map
(
clk_i => clk_20,
rst_n_i => rst_n,
data_i => burst_train_d1,
ppulse_o => burst_train_redge_in,
npulse_o => burst_train_fedge_in
);
--============================================================================ --============================================================================
-- Generate clock signals -- Generate clock signals
--============================================================================ --============================================================================
...@@ -251,11 +296,11 @@ end process p_ran_gen; ...@@ -251,11 +296,11 @@ end process p_ran_gen;
process process
begin begin
rst <= '1'; rst_n <= '1';
wait for 2500 ns; wait for 2500 ns;
rst <= '0'; rst_n <= '0';
wait for 2000 ns; wait for 2000 ns;
rst <= '1'; rst_n <= '1';
wait; wait;
end process; end process;
...@@ -280,21 +325,107 @@ end process p_ran_gen; ...@@ -280,21 +325,107 @@ end process p_ran_gen;
-- port map -- port map
-- ( -- (
-- clk_i => clk_20, -- clk_i => clk_20,
-- rst_n_i => rst, -- rst_n_i => rst_n,
-- data_i => burst_train, -- data_i => burst_train,
-- npulse_o => burst_train_f_edge, -- npulse_o => burst_train_f_edge,
-- ppulse_o => burst_train_r_edge -- ppulse_o => burst_train_r_edge
-- ); -- );
period_array_lg <= (8000 , 9600 , 20000 );
pwidth_array_lg <= (2000 , 500 , 1200 );
period_array_sh <= (450 , 500 , 1000 );
pwidth_array_sh <= (400 , 100 , 250 );
-- p_sel_params : process
-- variable interval : time;
-- begin
-- -- if rst_n = '1' and en = '1' then
-- --for gf_en_n in
-- if pwidth_sel = '1' then
-- for pwidth_index in 2 downto 0 loop
-- for period_index in 2 downto 0 loop
-- pnumber <= 0;
-- while pnumber < 9 loop
-- -- if random_intervals then
-- -- interval := rand_num * 1 ns;
-- -- if interval < 250 ns then
-- -- interval := 250 ns;
-- -- end if;
-- -- else
-- interval := (period_array_lg(period_index) - pwidth_array_lg(pwidth_index))*1ns;
-- -- end if;
-- burst_train <= '0';
-- wait for interval;
-- burst_train <= '1';
-- wait for pwidth_array_lg(pwidth_index)*1ns;-- changes pulse width
-- burst_train <= '0';
-- pnumber <= pnumber + 1;
-- end loop;
-- wait for 0.1 ms;
-- end loop;
-- wait for 0.2 ms;
-- end loop;
-- wait for 0.5 ms;
-- else
-- for pwidth_index in 2 downto 0 loop
-- for period_index in 2 downto 0 loop
-- pnumber<=0;
-- while pnumber < 9 loop
-- -- if random_intervals then
-- -- interval := rand_num * 1 ns;
-- -- if interval < 250 ns then
-- -- interval := 250 ns;
-- -- end if;
-- -- else
-- interval := (period_array_sh(period_index) - pwidth_array_sh(pwidth_index))*1ns;
-- -- end if;
-- burst_train <= '0';
-- wait for interval;
-- burst_train <= '1';
-- wait for pwidth_array_sh(pwidth_index)*1ns;-- changes pulse width
-- burst_train <= '0';
-- pnumber <= pnumber+1;
-- end loop;
-- wait for 0.01 ms;
-- end loop;
-- wait for 0.02 ms;
-- end loop;
-- wait for 0.05 ms;
-- -- end if;
-- end if;
-- end process p_sel_params;
p_delay : process (clk_20)
begin
if rising_edge(clk_20) then
if (rst_n = '0') then
burst_train_d0 <= '0';
burst_train_d1 <= '0';
else
burst_train_d0 <= burst_train;
burst_train_d1 <= burst_train_d0;
end if;
end if;
end process p_delay;
p_stim_burst1 : process p_stim_burst1 : process
variable interval : time;-- := 1000 ns; variable interval : time;-- := 1000 ns;
variable period1 : time := 450 ns;--changes pulse frequency variable period1 : time := 250 ns;--changes pulse frequency
variable period2 : time := 2000 ns;--changes pulse frequency variable period2 : time := 2000 ns;--changes pulse frequency
variable pwidth : time := 250 ns; variable period3 : time := 450 ns;--changes pulse frequency
variable pwidth : time := 100 ns;
begin begin
while t_sim1 < 50000 us loop
-- while true loop
while t_sim1 < 10000 us loop
t_sim1 <= NOW - t_start; t_sim1 <= NOW - t_start;
if random_intervals then if random_intervals then
interval := rand_num * 1 ns; interval := rand_num * 1 ns;
...@@ -311,7 +442,7 @@ end process p_ran_gen; ...@@ -311,7 +442,7 @@ end process p_ran_gen;
burst_train <= '0'; burst_train <= '0';
end loop; end loop;
while t_sim2 < 100000 us loop while t_sim2 < 10000 us loop
t_sim2 <= NOW - t_sim1; t_sim2 <= NOW - t_sim1;
if random_intervals then if random_intervals then
interval := rand_num * 1 ns; interval := rand_num * 1 ns;
...@@ -325,6 +456,18 @@ end process p_ran_gen; ...@@ -325,6 +456,18 @@ end process p_ran_gen;
burst_train <= '0'; burst_train <= '0';
end loop; end loop;
burst_train <= '0';
wait for 5 ms;
while t_sim3 < 30000 us loop
t_sim3 <= NOW - t_sim1;
interval := period3 - pwidth;
burst_train <= '0';
wait for interval;
burst_train <= '1';
wait for pwidth;-- changes pulse width
burst_train <= '0';
end loop;
end process p_stim_burst1; end process p_stim_burst1;
......
sim/Release/testbenchv4.vhd
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syn/Release/iseconfig/conv_ttl_blo.xreport
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syn/Release/testbench_envsettings.html
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...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
</tr> </tr>
<tr> <tr>
<td>Path</td> <td>Path</td>
<td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Skype\Phone\;<br>C:\EDA\Cadence\SPB_166\tools\pspice;<br>C:\EDA\Cadence\SPB_166\tools\capture;<br>C:\EDA\Cadence\SPB_166\tools\bin;<br>C:\EDA\Cadence\SPB_166\openaccess\bin\win32\opt;<br>C:\EDA\Cadence\SPB_166\tools\fet\bin;<br>C:\EDA\Cadence\SPB_166\tools\pcb\bin;<br>C:\EDA\Cadence\SPB_166\tools\specctra\bin;<br>C:\EDA\Cadence\SPB_166\tools\libutil\bin;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Users\debouhir\Documents\MikTex\miktex\bin\;<br>C:\Program Files\wbgen2-bin.tar\bin;<br>C:\Program Files\Git\cmd;<br>C:\modeltech64_10.1c\win64</td> <td>C:\Xilinx\14.7\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.7\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_be\bin;<br>C:\Xilinx\14.7\ISE_DS\EDK\gnu\microblaze\linux_toolchain\nt64_le\bin;<br>C:\Xilinx\14.7\ISE_DS\common\bin\nt64;<br>C:\Xilinx\14.7\ISE_DS\common\lib\nt64;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Skype\Phone\;<br>C:\EDA\Cadence\SPB_166\tools\pspice;<br>C:\EDA\Cadence\SPB_166\tools\capture;<br>C:\EDA\Cadence\SPB_166\tools\bin;<br>C:\EDA\Cadence\SPB_166\openaccess\bin\win32\opt;<br>C:\EDA\Cadence\SPB_166\tools\fet\bin;<br>C:\EDA\Cadence\SPB_166\tools\pcb\bin;<br>C:\EDA\Cadence\SPB_166\tools\specctra\bin;<br>C:\EDA\Cadence\SPB_166\tools\libutil\bin;<br>C:\Program Files\TortoiseGit\bin;<br>C:\Users\debouhir\Documents\MikTex\miktex\bin\;<br>C:\Program Files\wbgen2-bin.tar\bin;<br>C:\Program Files\Git\cmd;<br>C:\VXIPNP\WinNT\Bin;<br>C:\modeltech64_10.1c\win64</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td> <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td> <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td> <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
...@@ -95,7 +95,7 @@ ...@@ -95,7 +95,7 @@
<tr> <tr>
<td>-p</td> <td>-p</td>
<td>&nbsp;</td> <td>&nbsp;</td>
<td>xc6slx4-3-tqg144</td> <td>xc6slx45t-3-fgg484</td>
<td>&nbsp;</td> <td>&nbsp;</td>
</tr> </tr>
<tr> <tr>
......
syn/Release/testbench_summary.html
View file @ 1a34f694
...@@ -7,16 +7,17 @@ ...@@ -7,16 +7,17 @@
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>conv_ttl_blo.xise</TD> <TD>conv_ttl_blo.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD> <TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD ALIGN=LEFT><font color='red'; face='Arial'><b>X </b></font><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\_xmsgs/pn_parser.xmsgs?&DataKey=Error'>1 Error</A></TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD> <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>conv_ttl_blo</TD> <TD>conv_ttl_blo</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD> <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD> <TD>New (Failed)</TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD> <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx4-3tqg144</TD> <TD>xc6slx45t-3fgg484</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
</TR> </TR>
...@@ -40,7 +41,10 @@ ...@@ -40,7 +41,10 @@
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD> <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD> <TD>
<A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\testbench_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD> <TD>&nbsp;&nbsp;</TD>
</TR> </TR>
...@@ -71,8 +75,9 @@ ...@@ -71,8 +75,9 @@
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/debouhir/work/CONV-TTL-BLO/conv-ttl-blo/conv-ttl-blo-gw/syn/Release\isim.log'>ISIM Simulator Log</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Tue 7. Feb 16:41:32 2017</TD></TR>
</TABLE> </TABLE>
<br><center><b>Date Generated:</b> 11/10/2016 - 12:17:10</center> <br><center><b>Date Generated:</b> 02/13/2017 - 18:37:49</center>
</BODY></HTML> </BODY></HTML>
\ No newline at end of file
syn/Release/transcript
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top/Release/conv_ttl_blo.vhd
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...@@ -52,6 +52,7 @@ ...@@ -52,6 +52,7 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
use work.gencores_pkg.all; use work.gencores_pkg.all;
...@@ -298,7 +299,7 @@ begin ...@@ -298,7 +299,7 @@ begin
inhibit_first_pulse <= '1'; inhibit_first_pulse <= '1';
elsif (inhibit_first_pulse = '1') then elsif (inhibit_first_pulse = '1') then
inhibit_cnt <= inhibit_cnt + 1; inhibit_cnt <= inhibit_cnt + 1;
if (inhibit_cnt = 1999) then if (inhibit_cnt >= 1999 and and_reduce(ttl_n_i)='1') then
inhibit_first_pulse <= '0'; inhibit_first_pulse <= '0';
end if; end if;
end if; end if;
...@@ -318,10 +319,6 @@ begin ...@@ -318,10 +319,6 @@ begin
end if; end if;
end process; end process;
-- Pulse input valid only after inhibit period is over -- Pulse input valid only after inhibit period is over
pulse_in <= (pulse_ttl or pulse_blo) when (inhibit_first_pulse_d0 = '0') else pulse_in <= (pulse_ttl or pulse_blo) when (inhibit_first_pulse_d0 = '0') else
(others => '0'); (others => '0');
...@@ -335,15 +332,14 @@ begin ...@@ -335,15 +332,14 @@ begin
-- Switch inputs for reflection in status register -- Switch inputs for reflection in status register
sw_gp <= not sw_gp_n_i; sw_gp <= not sw_gp_n_i;
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
--Note that this burst mode functionality is activated only for PCB v4 or later --Note that this burst mode functionality is activated only for PCB v4 or later
--The FPGA --The FPGA
-- Functionality enabled for versions 4 and above -- Functionality enabled for versions 4 and above
-- when version is below 4 then disable burst functionality -- when version is below 4 then disable burst functionality
-- burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1'; -- burst_en_n <= '0' when pcbrev_i (5 downto 0) >= "010000" else '1';
--************************************************************************** --**************************************************************************
...@@ -367,7 +363,7 @@ begin ...@@ -367,7 +363,7 @@ begin
g_pgen_fixed_width => true, g_pgen_fixed_width => true,
g_pgen_pwidth_lg => 24, g_pgen_pwidth_lg => 24,
g_pgen_pwidth_sh => 5, g_pgen_pwidth_sh => 5,
g_pgen_pperiod_cont=> 4800, g_pgen_pperiod_cont => 4800,
-- Minimum period supported for 1.2us pulse ~ max freq 104kHz -- Minimum period supported for 1.2us pulse ~ max freq 104kHz
g_pgen_pperiod_lg => 191, g_pgen_pperiod_lg => 191,
-- Minimum period supported for 250ns pulse ~ max freq 2MHz -- Minimum period supported for 250ns pulse ~ max freq 2MHz
...@@ -405,6 +401,10 @@ begin ...@@ -405,6 +401,10 @@ begin
burst_en_n_i => burst_en_n, burst_en_n_i => burst_en_n,
-- Pulse width selection, port low means 250ns, high means 1.2us. -- Pulse width selection, port low means 250ns, high means 1.2us.
-- Switch to determine short or long pulse mode.
-- ON switch means SHORT 250ns pulse repetition with max frequency 2MHz
-- OFF switch means LONG 1.2us pulse repetition with max freq ~104kHz
pulse_width_sel_n_i => sw_gp_n_i(1), pulse_width_sel_n_i => sw_gp_n_i(1),
-- Channel enable -- Channel enable
......
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