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## Documentation
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\* The block diagram of the logic is shown below.
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- Gateware block
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diagram
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\* For information on the implementation of each block, consult the HDL
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guide:
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![](/uploads/05f7ef412393983ce1bce8aa6434abaa/hdl-bd.png)
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\* For the implementation of each block, consult the HDL guide
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* Clone the repository with the appropriate tag
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* [PDF
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version](https://www.ohwr.org/project/conv-ttl-blo-gw/uploads/738ffb21f53840311c5a7ccffddf09a8/hdlg-conv-ttl-blo-v2.0.pdf)
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* Then run the following commands in the project folder
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(`conv-ttl-blo-gw/`):
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* compile from
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source
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git clone git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git
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git checkout v1.0
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cd doc/hdlguide/
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make
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![](/uploads/05f7ef412393983ce1bce8aa6434abaa/hdl-bd.png)
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-----
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Theodor-Adrian Stana, Jan. 2014
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