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# CONV-TTL-BLO golden gateware version 0.2
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## Release notes
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- **CHANGES IN MEMORY MAP FROM PREVIOUS VERSIONS**
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- the Multiboot module is now at address **0x100**
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- see the [HDL
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guide](https://www.ohwr.org/project/conv-ttl-blo-gw/uploads/f3aaf1514ad6a777a56e31c3e4a71cb1/hdlg-conv-ttl-blo-v0.2.pdf)
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for details
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- Uses the [converter board common
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gateware](https://www.ohwr.org/project/conv-common-gw)
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- Fallback to golden gateware is now a system error
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- ERR LED lit red when golden gateware is booted to
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- Pulse repetition with max. frequency of 4160 Hz
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- 1.2us pulse on output
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- duty cycle of 1/200
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- input pulses with duty cycle of more than 1/200 are rejected
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- I2C to Wishbone bridge following the protocol defined together with
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ELMA
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- Diagnostics support
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- converter board ID
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- gateware version
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- state of on-board switches
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- state of [RTM detection
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lines](https://www.ohwr.org/project/conv-ttl-blo/wikis/RTM-board-detection)
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- state of I2C watchdog timer
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- system errors
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- remote logic reset
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- line status readout from dedicated register
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- Pulse and status LED control
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- [Remote reprogramming](/Xil-multiboot)
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- Connects VME SYSRESET signal to reset the FPGA logic
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## Binary files
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- Binary files for remote
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reprogramming
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- [golden-v0.2.bin](https://www.ohwr.org/project/conv-ttl-blo-gw/uploads/61101d7fab4f12663b968defd95d04a2/golden-v0.2.bin)
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- [golden-v0.2.bit](https://www.ohwr.org/project/conv-ttl-blo-gw/uploads/df49998036f9dbb6f91d3bb2f84d85a9/golden-v0.2.bit)
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- To create a complete bitstream (golden + release) for direct
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download to the flash, see
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[here](/Releases#preparing-a-bitstream-containing-the-golden-bitstream-for-multiboot)
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## Sources
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- [tag v0.2 in
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repository](https://www.ohwr.org/project/conv-ttl-blo-gw/tree/v0.2/)
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## Documentation
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- Block
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diagram
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[![](/uploads/e74ea69342b039e746e82f782edbd848/hdl-bd-v0.2.svg)](/uploads/e74ea69342b039e746e82f782edbd848/hdl-bd-v0.2.svg)
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\* For the implementation of each block, consult the HDL guide
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* [PDF
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version](https://www.ohwr.org/project/conv-ttl-blo-gw/uploads/f3aaf1514ad6a777a56e31c3e4a71cb1/hdlg-conv-ttl-blo-v0.2.pdf)
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* compile from
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source
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git clone git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git
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cd conv-ttl-blo-gw
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git checkout v0.2
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cd doc/hdlg/
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make
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-----
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Theodor-Adrian Stana, Sept. 2014
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