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# Golden release gateware v0.0
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## Release notes
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- Pulse repetition with max. frequency of 4160 Hz
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- 1.2us pulse on output
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- duty cycle of 1/200
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- input pulses with duty cycle of more than 1/200 are rejected
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- I2C to Wishbone bridge following the protocol defined together with
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ELMA
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- Dedicated CONV-TTL-BLO registers (see full memory map in the HDL
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guide):
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- Board ID register
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- CSR
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- remote logic reset
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- gateware version
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- state of on-board switches
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- state of [RTM detection
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lines](https://www.ohwr.org/pr\`ojects/conv-ttl-blo/wikis/RTM_board_detection)
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- state of I2C watchdog timer
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- Pulse and status LED control
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- [Remote
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reprogramming](/Xil-multiboot)
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## Binary files
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- [golden-v0.0.bin](https://www.ohwr.org/project/conv-ttl-blo-gw/uploads/80b052b69ebc684c199e93defb9a6a11/golden-v0.0.bin)
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- [golden-v0.0.bit](https://www.ohwr.org/project/conv-ttl-blo-gw/uploads/d3747c19e524e4e83efa702119ffb75d/golden-v0.0.bit)
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## Sources
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- [tag v0.0 in
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repository](https://www.ohwr.org/project/conv-ttl-blo-gw/tree/v0.0/)
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## Documentation
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- The block diagram of the logic is shown
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below.
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![](/uploads/5527fb35ae9a0aa4d00591f28554e9ac/hdl-bd-golden.png)
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\* For information on the implementation of each block, consult the HDL
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guide:
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git clone -b golden git:https://www.ohwr.org/level-conversion/conv-ttl-blo/conv-ttl-blo-gw.git
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git checkout v0.0
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cd doc/hdlguide/
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make
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-----
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Theodor-Adrian Stana, May 2014
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