... | @@ -28,7 +28,10 @@ in the figure below: |
... | @@ -28,7 +28,10 @@ in the figure below: |
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- Multiboot bitstream - the bitstream that is normally loaded when the
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- Multiboot bitstream - the bitstream that is normally loaded when the
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IPROG command is issued
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IPROG command is issued
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- Golden bitstream - the bitstream loaded if the multiboot bitstream
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- Golden bitstream - the bitstream loaded if the multiboot bitstream
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load fails
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load
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fails
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![](/uploads/4a0d89b5a42ebbf0152df6a74e7710ed/multiboot.png)
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A strike count is used to select which bitstream gets loaded; it
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A strike count is used to select which bitstream gets loaded; it
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increments every time there is an error:
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increments every time there is an error:
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... | @@ -44,14 +47,219 @@ In order to remotely reprogram a Xilinx FPGA, the following workflow is |
... | @@ -44,14 +47,219 @@ In order to remotely reprogram a Xilinx FPGA, the following workflow is |
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employed [\[2\]](/xil-multiboot#References):
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employed [\[2\]](/xil-multiboot#References):
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1. Prepare a Xilinx FPGA bitstream
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1. Prepare a Xilinx FPGA bitstream
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2. Erase the sector of the flash chip containing the bitstream
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2. Erase the sector of the Flash chip containing the bitstream
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3. Send the bitstream to the FPGA system via the protocol of choice
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3. Send the bitstream to the FPGA system via the protocol of choice
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(e.g. ELMA protocol)
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(e.g. ELMA protocol)
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4. Translate the protocol into Wishbone via a Wishbone bridge (e.g.
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4. Translate the protocol into Wishbone via a Wishbone bridge (e.g.
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elma\_i2c)
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elma\_i2c)
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5. Download the bitstream to the flash chip via the FPGA
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5. Download the bitstream to the Flash chip via the FPGA
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6. Issue a reprogramming command from the FPGA
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6. Issue a reprogramming command from the FPGA
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## Design specification
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Some intended features of the **xil\_multiboot** module are:
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- modular design
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- provide a Wishbone interface, with the potential possibility for
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implementing different types of FPGA interconnect (Avalon, AXI,
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etc.) to control it
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- provide an interface to write to a Flash memory chip
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- use the Xilinx ICAP primitive to control configuration logic of the
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FPGA
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- implement some registers (see [register
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map](xil-multiboot#register-map)) for external control
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- implement an FSM to control writing to Flash chip and send the IPRO
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command to the FPGA
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- FSM controlled by bits in multiboot registers
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- start with control of Numonyx M25P Flash memories
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- gradually migrate design to generic Flash memory (FSM to support
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different page/sector size, etc.)
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A block diagram of the **xil\_multiboot** module is shown below. It
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consists of the following
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blocks:
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![](/uploads/33a36e7b8449344d15f9df9dc610d6a2/multiboot-bd.png)
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Block </b></td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td><b> <strong>multiboot_regs</strong> </b></td>
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<td>Wishbone interface and registers</td>
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</tr>
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<tr class="odd">
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<td><b> <strong>multiboot_fsm</strong> </b></td>
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<td>Main FSM of the multiboot block</td>
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</tr>
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<tr class="even">
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<td><b> <strong>icap_spartan6</strong> </b></td>
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<td>Xilinx ICAP IP core</td>
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</tr>
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<tr class="odd">
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<td><b> <strong>m25p_flash</strong> </b></td>
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<td>Slightly modified version of M25P flash chip controller block in the <a href="https://www.ohwr.org/project/svec">SVEC</a> design.</td>
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</tr>
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</tbody>
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</table>
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## Register map
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Register </b></td>
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<td align="center">* Offset *</td>
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<td align="center">* Access *</td>
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<td align="center">* Default *</td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td>CR</td>
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<td align="center">0x000</td>
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<td align="center">R/W</td>
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<td align="center">0xXXXXXXX0</td>
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<td>Control register</td>
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</tr>
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<tr class="odd">
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<td>SR</td>
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<td align="center">0x004</td>
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<td align="center">R/O</td>
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<td align="center">0xXXXXXXXX</td>
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<td>Status register</td>
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</tr>
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<tr class="even">
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<td>GBBAR</td>
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<td align="center">0x008</td>
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<td align="center">R/W</td>
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<td align="center">0x00000000</td>
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<td>Golden bitstream base address register</td>
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</tr>
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<tr class="odd">
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<td>MBBAR</td>
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<td align="center">0x00C</td>
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<td align="center">R/W</td>
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<td align="center">0x00000000</td>
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<td>MultiBoot bitstream base address register</td>
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</tr>
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</tbody>
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</table>
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The GBBAR and MBBAR are image replicas of the GENERAL1..5
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[\[1\]](/xil-multiboot#References) configuration registers in the Xilinx
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Spartan-6 FPGA.
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### CR
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Bits </b></td>
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<td><b> Field </b></td>
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<td align="center">* Default *</td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td>31..3</td>
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<td><em>Reserved</em></td>
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<td align="center">X</td>
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<td>Reserved bits read as undefined; they should be written as '0'</td>
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</tr>
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<tr class="odd">
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<td>2</td>
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<td>IPROG</td>
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<td align="center">0</td>
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<td>When 1, it triggers the FSM sending the IPROG command to the ICAP controller</td>
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</tr>
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<tr class="even">
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<td>1</td>
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<td>WGB</td>
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<td align="center">0</td>
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<td>Initiate Flash write to golden bitstream address (GBBAR)</td>
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</tr>
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<tr class="odd">
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<td>0</td>
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<td>WMB</td>
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<td align="center">0</td>
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<td>Initiate Flash write to multiboot bitstream address (MBBAR)</td>
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</tr>
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</tbody>
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</table>
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### SR
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Bits </b></td>
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<td><b> Field </b></td>
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<td><b> Default </b></td>
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<td><b> Description </b></td>
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</tr>
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</tbody>
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</table>
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### GBBAR
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This register is an image replica of the GENERAL3,4
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[\[1\]](/xil-multiboot#References) configuration registers in Xilinx
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Spartan-6 FPGAs.
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Bits </b></td>
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<td><b> Field </b></td>
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<td align="center">* Default *</td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td>31..24</td>
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<td>OPCODE</td>
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<td align="center">0x00</td>
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<td>Read op-code to be sent to Flash chip</td>
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</tr>
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<tr class="odd">
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<td>23..0</td>
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<td>GBA</td>
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<td align="center">0x000000</td>
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<td>Golden bitstream start address in Flash memory</td>
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</tr>
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</tbody>
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</table>
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### MBBAR
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This register is an image replica of the GENERAL1,2
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[\[1\]](/xil-multiboot#References) configuration registers in Xilinx
|
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Spartan-6 FPGAs.
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Bits </b></td>
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<td><b> Field </b></td>
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<td align="center">* Default *</td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td>31..24</td>
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<td>OPCODE</td>
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<td align="center">0x00</td>
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<td>Read op-code to be sent to Flash chip</td>
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</tr>
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<tr class="odd">
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<td>23..0</td>
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<td>MBA</td>
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<td align="center">0x000000</td>
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<td>Golden bitstream start address in Flash memory</td>
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</tr>
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</tbody>
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</table>
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## References
|
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## References
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|
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\[1\] [Xilinx UG380: Spartan-6 FPGA Configuration, User
|
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\[1\] [Xilinx UG380: Spartan-6 FPGA Configuration, User
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... | | ... | |