... | @@ -785,9 +785,9 @@ an eight-bit SPI master interface with the following settings: |
... | @@ -785,9 +785,9 @@ an eight-bit SPI master interface with the following settings: |
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![](/uploads/00097f59eb46bf074a5958372f98cf41/SPI_timing_diagram2.svg)
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![](/uploads/00097f59eb46bf074a5958372f98cf41/SPI_timing_diagram2.svg)
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(source: Wikipedia)
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(source: Wikipedia)
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Thus, the idle state of SCK is high and bits are shifted out on the MOSI
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Thus, the idle state of SCK is low ('0') and bits are shifted out on the
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line on the falling edge of SCK, and shifted in on the MISO line on the
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MOSI line on the falling edge of SCK, and shifted in on the MISO line on
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rising edge of SCK.
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the rising edge of SCK.
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