... | @@ -46,7 +46,7 @@ in the figure below: |
... | @@ -46,7 +46,7 @@ in the figure below: |
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load
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load
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fails
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fails
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![](/uploads/4a0d89b5a42ebbf0152df6a74e7710ed/multiboot.png)
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![](https://ohwr.org/project/conv-ttl-blo-gw/uploads/4a0d89b5a42ebbf0152df6a74e7710ed/multiboot.png)
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A strike count is used to select which bitstream gets loaded. In Xilinx
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A strike count is used to select which bitstream gets loaded. In Xilinx
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FPGAs, two kinds of errors can exist when loading a bitstream:
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FPGAs, two kinds of errors can exist when loading a bitstream:
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... | @@ -252,7 +252,7 @@ consists of the following blocks: |
... | @@ -252,7 +252,7 @@ consists of the following blocks: |
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|** **spi_master** **|SPI master from the bootloader design under the [SVEC](https://www.ohwr.org/project/svec) project|
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|** **spi_master** **|SPI master from the bootloader design under the [SVEC](https://www.ohwr.org/project/svec) project|
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![](/uploads/33a36e7b8449344d15f9df9dc610d6a2/multiboot-bd.png)
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![](https://ohwr.org/project/conv-ttl-blo-gw/uploads/33a36e7b8449344d15f9df9dc610d6a2/multiboot-bd.png)
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-----
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-----
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... | @@ -455,7 +455,7 @@ the FSM is comprised of several states that lead to the phase being |
... | @@ -455,7 +455,7 @@ the FSM is comprised of several states that lead to the phase being |
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completed, but most of these states have been omitted for ease of
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completed, but most of these states have been omitted for ease of
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understanding.
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understanding.
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![](/uploads/08c937264a9d16cdd0097716e4ea286a/multiboot-fsm.png)
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![](https://ohwr.org/project/conv-ttl-blo-gw/uploads/08c937264a9d16cdd0097716e4ea286a/multiboot-fsm.png)
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The following table describes these phases. More involved descriptions
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The following table describes these phases. More involved descriptions
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on each phase are given below.
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on each phase are given below.
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... | @@ -543,7 +543,7 @@ an eight-bit SPI master interface with the following settings: |
... | @@ -543,7 +543,7 @@ an eight-bit SPI master interface with the following settings: |
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- CPHA =
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- CPHA =
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0
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0
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![](/uploads/00097f59eb46bf074a5958372f98cf41/SPI_timing_diagram2.svg)
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![](https://ohwr.org/project/conv-ttl-blo-gw/uploads/00097f59eb46bf074a5958372f98cf41/SPI_timing_diagram2.svg)
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(source: Wikipedia)
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(source: Wikipedia)
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Thus, the idle state of SCK is low ('0') and bits are shifted out on the
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Thus, the idle state of SCK is low ('0') and bits are shifted out on the
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