... | @@ -224,9 +224,9 @@ All this can be done from the GUI of Xilinx ISE: |
... | @@ -224,9 +224,9 @@ All this can be done from the GUI of Xilinx ISE: |
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Apart from setting the **-g reset\_on\_error** switch, the **-g
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Apart from setting the **-g reset\_on\_error** switch, the **-g
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next\_config\_register\_write** switch should also be set to
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next\_config\_register\_write** switch should also be set to
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*Disable**, to keep the values of the GENERAL configuration registers
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*Disable**, to keep the values of the GENERAL configuration registers
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intact in between subsequent reprograms. This **must be done**,
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intact between subsequent reprograms. This **must be done**, otherwise a
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otherwise a corrupted multiboot image **will not** boot back to the
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corrupted multiboot image **will not** boot back to the Golden image and
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Golden image and the card will requre a power-on reset.
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the card will require a power-on reset.
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Adding the BitGen flags can be done in two ways:
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Adding the BitGen flags can be done in two ways:
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... | @@ -289,42 +289,36 @@ consists of the following blocks: |
... | @@ -289,42 +289,36 @@ consists of the following blocks: |
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<td><b> Register </b></td>
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<td><b> Register </b></td>
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<td align="center">* Offset *</td>
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<td align="center">* Offset *</td>
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<td align="center">* Access *</td>
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<td align="center">* Access *</td>
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<td align="center">* Default *</td>
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<td><b> Description </b></td>
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<td><b> Description </b></td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>[CR](xil-multiboot#cr)</td>
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<td>[CR](xil-multiboot#cr)</td>
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<td align="center">0x000</td>
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<td align="center">0x000</td>
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<td align="center">R/W</td>
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<td align="center">R/W</td>
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<td align="center">0xXXXXXXX0</td>
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<td>Control Register</td>
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<td>Control Register</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>[IMGR](xil-multiboot#imgr)</td>
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<td>[IMGR](xil-multiboot#imgr)</td>
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<td align="center">0x004</td>
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<td align="center">0x004</td>
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<td align="center">R/O</td>
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<td align="center">R/O</td>
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<td align="center">0xXXXXXXXX</td>
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<td>Configuration Image Register</td>
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<td>Configuration Image Register</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>[GBBAR](xil-multiboot#gbbar)</td>
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<td>[GBBAR](xil-multiboot#gbbar)</td>
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<td align="center">0x008</td>
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<td align="center">0x008</td>
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<td align="center">R/W</td>
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<td align="center">R/W</td>
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<td align="center">0x00000000</td>
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<td>Golden Bitstream Base Address Register</td>
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<td>Golden Bitstream Base Address Register</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>[MBBAR](xil-multiboot#mbbar)</td>
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<td>[MBBAR](xil-multiboot#mbbar)</td>
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<td align="center">0x00C</td>
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<td align="center">0x00C</td>
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<td align="center">R/W</td>
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<td align="center">R/W</td>
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<td align="center">0x00000000</td>
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<td>MultiBoot Bitstream Base Address Register</td>
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<td>MultiBoot Bitstream Base Address Register</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>[FAR](xil-multiboot#far)</td>
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<td>[FAR](xil-multiboot#far)</td>
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<td align="center">0x010</td>
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<td align="center">0x010</td>
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<td align="center">R/W</td>
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<td align="center">R/W</td>
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<td align="center">0x00000000</td>
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<td>Flash Access Register</td>
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<td>Flash Access Register</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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... | @@ -356,7 +350,7 @@ FPGA. |
... | @@ -356,7 +350,7 @@ FPGA. |
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<td>17</td>
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<td>17</td>
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<td>IPROG</td>
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<td>IPROG</td>
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<td align="center">0</td>
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<td align="center">0</td>
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<td>When 1, it triggers the FSM sending the IPROG command to the ICAP controller<br />
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<td>When 1, it triggers the FSM to send the IPROG command to the ICAP controller<br />
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This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle</td>
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This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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... | @@ -569,7 +563,7 @@ done at the same time via one write to the FAR): |
... | @@ -569,7 +563,7 @@ done at the same time via one write to the FAR): |
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<tr class="odd">
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<tr class="odd">
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<td>28</td>
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<td>28</td>
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<td>READY</td>
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<td>READY</td>
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<td align="center">0</td>
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<td align="center">1</td>
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<td>1: SPI transfer is ready (NBYTES sent and received)<br />
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<td>1: SPI transfer is ready (NBYTES sent and received)<br />
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0: SPI transfer in progress</td>
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0: SPI transfer in progress</td>
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</tr>
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</tr>
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... | @@ -657,7 +651,10 @@ The **spi\_master** module in the **xil\_multiboot** module implements |
... | @@ -657,7 +651,10 @@ The **spi\_master** module in the **xil\_multiboot** module implements |
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an eight-bit SPI master interface with the following settings:
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an eight-bit SPI master interface with the following settings:
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- CPOL = 0
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- CPOL = 0
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- CPHA = 1
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- CPHA =
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1
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![](/uploads/00097f59eb46bf074a5958372f98cf41/SPI_timing_diagram2.svg)
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Thus, the idle state of SCL is high and bits are shifted out on the MOSI
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Thus, the idle state of SCL is high and bits are shifted out on the MOSI
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line on the falling edge of SCL, and shifted in on the MISO line on the
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line on the falling edge of SCL, and shifted in on the MISO line on the
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... | | ... | |