... | ... | @@ -751,13 +751,14 @@ an eight-bit SPI master interface with the following settings: |
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- CPOL = 0
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- CPHA =
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1
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0
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![](/uploads/00097f59eb46bf074a5958372f98cf41/SPI_timing_diagram2.svg)
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![](/uploads/00097f59eb46bf074a5958372f98cf41/SPI_timing_diagram2.svg)
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(source: Wikipedia)
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Thus, the idle state of SCL is high and bits are shifted out on the MOSI
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line on the falling edge of SCL, and shifted in on the MISO line on the
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rising edge of SCL.
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Thus, the idle state of SCK is high and bits are shifted out on the MOSI
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line on the falling edge of SCK, and shifted in on the MISO line on the
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rising edge of SCK.
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-----
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