... | @@ -12,6 +12,8 @@ Its main features are: |
... | @@ -12,6 +12,8 @@ Its main features are: |
|
- issues a programming command to the Xilinx FPGA, which starts
|
|
- issues a programming command to the Xilinx FPGA, which starts
|
|
reprogramming the FPGA with the new bitstream
|
|
reprogramming the FPGA with the new bitstream
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
## MultiBoot basics
|
|
## MultiBoot basics
|
|
|
|
|
|
Xilinx MultiBoot technology [\[1\]](/xil-multiboot#References) allows
|
|
Xilinx MultiBoot technology [\[1\]](/xil-multiboot#References) allows
|
... | @@ -41,6 +43,8 @@ increments every time there is an error: |
... | @@ -41,6 +43,8 @@ increments every time there is an error: |
|
- if it is 6..8, the header bitstream gets loaded
|
|
- if it is 6..8, the header bitstream gets loaded
|
|
- if it is 9, configuration is halted
|
|
- if it is 9, configuration is halted
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
## Workflow
|
|
## Workflow
|
|
|
|
|
|
In order to remotely reprogram a Xilinx FPGA, the following workflow is
|
|
In order to remotely reprogram a Xilinx FPGA, the following workflow is
|
... | @@ -55,6 +59,8 @@ employed [\[2\]](/xil-multiboot#References): |
... | @@ -55,6 +59,8 @@ employed [\[2\]](/xil-multiboot#References): |
|
5. Download the bitstream to the Flash chip via the FPGA
|
|
5. Download the bitstream to the Flash chip via the FPGA
|
|
6. Issue a reprogramming command from the FPGA
|
|
6. Issue a reprogramming command from the FPGA
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
## Design specification
|
|
## Design specification
|
|
|
|
|
|
Some intended features of the **xil\_multiboot** module are:
|
|
Some intended features of the **xil\_multiboot** module are:
|
... | @@ -68,7 +74,7 @@ Some intended features of the **xil\_multiboot** module are: |
... | @@ -68,7 +74,7 @@ Some intended features of the **xil\_multiboot** module are: |
|
FPGA
|
|
FPGA
|
|
- implement some registers (see [register
|
|
- implement some registers (see [register
|
|
map](xil-multiboot#register-map)) for external control
|
|
map](xil-multiboot#register-map)) for external control
|
|
- implement an FSM to control writing to Flash chip and send the IPRO
|
|
- implement an FSM to control writing to Flash chip and send the IPROG
|
|
command to the FPGA
|
|
command to the FPGA
|
|
- FSM controlled by bits in multiboot registers
|
|
- FSM controlled by bits in multiboot registers
|
|
- start with control of Numonyx M25P Flash memories
|
|
- start with control of Numonyx M25P Flash memories
|
... | @@ -105,8 +111,12 @@ consists of the following blocks: |
... | @@ -105,8 +111,12 @@ consists of the following blocks: |
|
|
|
|
|
![](/uploads/33a36e7b8449344d15f9df9dc610d6a2/multiboot-bd.png)
|
|
![](/uploads/33a36e7b8449344d15f9df9dc610d6a2/multiboot-bd.png)
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
## Register map
|
|
## Register map
|
|
|
|
|
|
|
|
*BASE ADDRESS: 0x80**
|
|
|
|
|
|
<table>
|
|
<table>
|
|
<tbody>
|
|
<tbody>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
... | @@ -117,33 +127,40 @@ consists of the following blocks: |
... | @@ -117,33 +127,40 @@ consists of the following blocks: |
|
<td><b> Description </b></td>
|
|
<td><b> Description </b></td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
<td>CR</td>
|
|
<td>[CR](xil-multiboot#cr)</td>
|
|
<td align="center">0x000</td>
|
|
<td align="center">0x000</td>
|
|
<td align="center">R/W</td>
|
|
<td align="center">R/W</td>
|
|
<td align="center">0xXXXXXXX0</td>
|
|
<td align="center">0xXXXXXXX0</td>
|
|
<td>Control register</td>
|
|
<td>Control register</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td>SR</td>
|
|
<td>[SR](xil-multiboot#sr)</td>
|
|
<td align="center">0x004</td>
|
|
<td align="center">0x004</td>
|
|
<td align="center">R/O</td>
|
|
<td align="center">R/O</td>
|
|
<td align="center">0xXXXXXXXX</td>
|
|
<td align="center">0xXXXXXXXX</td>
|
|
<td>Status register</td>
|
|
<td>Status register</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
<td>GBBAR</td>
|
|
<td>[GBBAR](xil-multiboot#gbbar)</td>
|
|
<td align="center">0x008</td>
|
|
<td align="center">0x008</td>
|
|
<td align="center">R/W</td>
|
|
<td align="center">R/W</td>
|
|
<td align="center">0x00000000</td>
|
|
<td align="center">0x00000000</td>
|
|
<td>Golden bitstream base address register</td>
|
|
<td>Golden bitstream base address register</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td>MBBAR</td>
|
|
<td>[MBBAR](xil-multiboot#mbbar)</td>
|
|
<td align="center">0x00C</td>
|
|
<td align="center">0x00C</td>
|
|
<td align="center">R/W</td>
|
|
<td align="center">R/W</td>
|
|
<td align="center">0x00000000</td>
|
|
<td align="center">0x00000000</td>
|
|
<td>MultiBoot bitstream base address register</td>
|
|
<td>MultiBoot bitstream base address register</td>
|
|
</tr>
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>[FAR](xil-multiboot#far)</td>
|
|
|
|
<td align="center">0x010</td>
|
|
|
|
<td align="center">R/W</td>
|
|
|
|
<td align="center">0x00000000</td>
|
|
|
|
<td>Flash access register</td>
|
|
|
|
</tr>
|
|
</tbody>
|
|
</tbody>
|
|
</table>
|
|
</table>
|
|
|
|
|
... | @@ -153,6 +170,8 @@ Spartan-6 FPGA. |
... | @@ -153,6 +170,8 @@ Spartan-6 FPGA. |
|
|
|
|
|
### CR
|
|
### CR
|
|
|
|
|
|
|
|
*Offset: 0x00**
|
|
|
|
|
|
<table>
|
|
<table>
|
|
<tbody>
|
|
<tbody>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
... | @@ -168,24 +187,18 @@ Spartan-6 FPGA. |
... | @@ -168,24 +187,18 @@ Spartan-6 FPGA. |
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td>3</td>
|
|
<td>4</td>
|
|
<td>IPROG</td>
|
|
<td>IPROG</td>
|
|
<td align="center">0</td>
|
|
<td align="center">0</td>
|
|
<td>When 1, it triggers the FSM sending the IPROG command to the ICAP controller</td>
|
|
<td>When 1, it triggers the FSM sending the IPROG command to the ICAP controller</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
<td>2</td>
|
|
<td>3..1</td>
|
|
<td>WGB</td>
|
|
<td><em>Reserved</em></td>
|
|
<td align="center">0</td>
|
|
<td align="center">X</td>
|
|
<td>Initiate Flash write to golden bitstream address (GBBAR)</td>
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td>1</td>
|
|
|
|
<td>WMB</td>
|
|
|
|
<td align="center">0</td>
|
|
|
|
<td>Initiate Flash write to multiboot bitstream address (MBBAR)</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>RDBOOTSTS</td>
|
|
<td>RDBOOTSTS</td>
|
|
<td align="center">0</td>
|
|
<td align="center">0</td>
|
... | @@ -196,6 +209,8 @@ Spartan-6 FPGA. |
... | @@ -196,6 +209,8 @@ Spartan-6 FPGA. |
|
|
|
|
|
### SR
|
|
### SR
|
|
|
|
|
|
|
|
*Offset: 0x04**
|
|
|
|
|
|
<table>
|
|
<table>
|
|
<tbody>
|
|
<tbody>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
... | @@ -312,6 +327,8 @@ Notes on the status register: |
... | @@ -312,6 +327,8 @@ Notes on the status register: |
|
|
|
|
|
### GBBAR
|
|
### GBBAR
|
|
|
|
|
|
|
|
*Offset: 0x08**
|
|
|
|
|
|
This register is an image of the GENERAL3,4
|
|
This register is an image of the GENERAL3,4
|
|
[\[1\]](/xil-multiboot#References) configuration registers in Xilinx
|
|
[\[1\]](/xil-multiboot#References) configuration registers in Xilinx
|
|
Spartan-6 FPGAs. Its contents are copied to the configuration registers
|
|
Spartan-6 FPGAs. Its contents are copied to the configuration registers
|
... | @@ -342,6 +359,8 @@ as part of the configuration sequence of the FPGA. |
... | @@ -342,6 +359,8 @@ as part of the configuration sequence of the FPGA. |
|
|
|
|
|
### MBBAR
|
|
### MBBAR
|
|
|
|
|
|
|
|
*Offset: 0x0C**
|
|
|
|
|
|
This register is an image of the GENERAL1,2
|
|
This register is an image of the GENERAL1,2
|
|
[\[1\]](/xil-multiboot#References) configuration registers in Xilinx
|
|
[\[1\]](/xil-multiboot#References) configuration registers in Xilinx
|
|
Spartan-6 FPGAs. Its contents are copied to the configuration registers
|
|
Spartan-6 FPGAs. Its contents are copied to the configuration registers
|
... | @@ -370,6 +389,59 @@ as part of the configuration sequence of the FPGA. |
... | @@ -370,6 +389,59 @@ as part of the configuration sequence of the FPGA. |
|
</tbody>
|
|
</tbody>
|
|
</table>
|
|
</table>
|
|
|
|
|
|
|
|
### FAR
|
|
|
|
|
|
|
|
*Offset: 0x10**
|
|
|
|
|
|
|
|
This register should be used by software to access the Flash chip.
|
|
|
|
|
|
|
|
<table>
|
|
|
|
<tbody>
|
|
|
|
<tr class="odd">
|
|
|
|
<td><b> Bits </b></td>
|
|
|
|
<td><b> Field </b></td>
|
|
|
|
<td align="center">* Default *</td>
|
|
|
|
<td><b> Description </b></td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>31.. 11</td>
|
|
|
|
<td><em>Reserved</em></td>
|
|
|
|
<td align="center">X</td>
|
|
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>10</td>
|
|
|
|
<td>CS</td>
|
|
|
|
<td align="center">0</td>
|
|
|
|
<td>Chip select bit. <em>Inverted with respect to SPI chip select, which is normally active low.</em><br />
|
|
|
|
1: Selects the Flash chip (CS pin = 0)<br />
|
|
|
|
0: Flash chip not selected (CS pin = 1)</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>9</td>
|
|
|
|
<td>READY</td>
|
|
|
|
<td align="center">0</td>
|
|
|
|
<td>1: SPI transfer is ready<br />
|
|
|
|
0: SPI transfer in progress</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>8</td>
|
|
|
|
<td>XFER</td>
|
|
|
|
<td align="center">0</td>
|
|
|
|
<td>1: Start SPI transfer</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>7..0</td>
|
|
|
|
<td>DATA</td>
|
|
|
|
<td align="center">0x00</td>
|
|
|
|
<td>Write this register with the next data byte to be written to the flash chip<br />
|
|
|
|
After an SPI transfer, this register contains the value read from the flash</td>
|
|
|
|
</tr>
|
|
|
|
</tbody>
|
|
|
|
</table>
|
|
|
|
|
|
|
|
-----
|
|
|
|
|
|
## References
|
|
## References
|
|
|
|
|
|
\[1\] [Xilinx UG380: Spartan-6 FPGA Configuration, User
|
|
\[1\] [Xilinx UG380: Spartan-6 FPGA Configuration, User
|
... | @@ -381,5 +453,3 @@ Design](http://www.xilinx.com/support/documentation/boards_and_kits/xtp059.pdf) |
... | @@ -381,5 +453,3 @@ Design](http://www.xilinx.com/support/documentation/boards_and_kits/xtp059.pdf) |
|
|
|
|
|
Theodor-Adrian Stana, Aug. 2013
|
|
Theodor-Adrian Stana, Aug. 2013
|
|
|
|
|
|
-----
|
|
|
|
|
|
|