... | @@ -52,12 +52,11 @@ employed [\[2\]](/xil-multiboot#References): |
... | @@ -52,12 +52,11 @@ employed [\[2\]](/xil-multiboot#References): |
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1. Prepare a Xilinx FPGA bitstream
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1. Prepare a Xilinx FPGA bitstream
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2. Erase the sector of the Flash chip containing the bitstream
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2. Erase the sector of the Flash chip containing the bitstream
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3. Send the bitstream to the FPGA system via the protocol of choice
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3. Send the bitstream to the FPGA system via software
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(e.g. ELMA protocol)
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4. Translate the protocol into Wishbone via a Wishbone bridge (e.g.
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4. Translate the protocol into Wishbone via a Wishbone bridge (e.g.
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elma\_i2c)
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vbcp\_wb)
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5. Download the bitstream to the Flash chip via the FPGA
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5. Download the bitstream to the Flash chip via the FPGA
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6. Issue a reprogramming command from the FPGA
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6. Issue a reprogramming command to the FPGA
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-----
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-----
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... | @@ -103,8 +102,8 @@ consists of the following blocks: |
... | @@ -103,8 +102,8 @@ consists of the following blocks: |
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<td>Xilinx ICAP IP core</td>
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<td>Xilinx ICAP IP core</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td><b> <strong>m25p_flash</strong> </b></td>
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<td><b> <strong>spi_master</strong> </b></td>
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<td>Serial master from the bootloader design under the <a href="https://www.ohwr.org/project/svec">SVEC</a> project</td>
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<td>SPI master from the bootloader design under the <a href="https://www.ohwr.org/project/svec">SVEC</a> project</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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... | | ... | |