... | @@ -104,7 +104,7 @@ consists of the following blocks: |
... | @@ -104,7 +104,7 @@ consists of the following blocks: |
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td><b> <strong>m25p_flash</strong> </b></td>
|
|
<td><b> <strong>m25p_flash</strong> </b></td>
|
|
<td>Slightly modified version of M25P flash chip controller block in the <a href="https://www.ohwr.org/project/svec">SVEC</a> design.</td>
|
|
<td>Serial master from the bootloader design under the <a href="https://www.ohwr.org/project/svec">SVEC</a> project</td>
|
|
</tr>
|
|
</tr>
|
|
</tbody>
|
|
</tbody>
|
|
</table>
|
|
</table>
|
... | @@ -187,18 +187,25 @@ Spartan-6 FPGA. |
... | @@ -187,18 +187,25 @@ Spartan-6 FPGA. |
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td>4</td>
|
|
<td>17</td>
|
|
<td>IPROG</td>
|
|
<td>IPROG</td>
|
|
<td align="center">0</td>
|
|
<td align="center">0</td>
|
|
<td>When 1, it triggers the FSM sending the IPROG command to the ICAP controller</td>
|
|
<td>When 1, it triggers the FSM sending the IPROG command to the ICAP controller<br />
|
|
|
|
This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
<td>3..1</td>
|
|
<td>16</td>
|
|
|
|
<td>IPROG_UNL</td>
|
|
|
|
<td align="center">0</td>
|
|
|
|
<td>Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing the IPROG bit</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>15..1</td>
|
|
<td><em>Reserved</em></td>
|
|
<td><em>Reserved</em></td>
|
|
<td align="center">X</td>
|
|
<td align="center">X</td>
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="even">
|
|
<td>0</td>
|
|
<td>0</td>
|
|
<td>RDBOOTSTS</td>
|
|
<td>RDBOOTSTS</td>
|
|
<td align="center">0</td>
|
|
<td align="center">0</td>
|
... | @@ -393,7 +400,15 @@ as part of the configuration sequence of the FPGA. |
... | @@ -393,7 +400,15 @@ as part of the configuration sequence of the FPGA. |
|
|
|
|
|
*Offset: 0x10**
|
|
*Offset: 0x10**
|
|
|
|
|
|
This register should be used by software to access the Flash chip.
|
|
This register should be used by software to access the Flash chip. It
|
|
|
|
contains the values of three data bytes to send to flash, as well as
|
|
|
|
control bits for the sending of data. The user should write NBYTES DATA
|
|
|
|
fields with the data to be sent to the chip, along with the NBYTES field
|
|
|
|
to select the number of data bytes to send, and CS to enable chip
|
|
|
|
selection. Setting XFER to 1 starts the transfer. This bit clears itself
|
|
|
|
automatically. After NBYTES have been sent to the chip, the READY bit is
|
|
|
|
set (1), and the DATA fields contain the three bytes read from the flash
|
|
|
|
chip.
|
|
|
|
|
|
<table>
|
|
<table>
|
|
<tbody>
|
|
<tbody>
|
... | @@ -404,42 +419,88 @@ This register should be used by software to access the Flash chip. |
... | @@ -404,42 +419,88 @@ This register should be used by software to access the Flash chip. |
|
<td><b> Description </b></td>
|
|
<td><b> Description </b></td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
<td>31.. 11</td>
|
|
<td>31..29</td>
|
|
<td><em>Reserved</em></td>
|
|
<td><em>Reserved</em></td>
|
|
<td align="center">X</td>
|
|
<td align="center">X</td>
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td>10</td>
|
|
<td>28</td>
|
|
|
|
<td>READY</td>
|
|
|
|
<td align="center">0</td>
|
|
|
|
<td>1: SPI transfer is ready (NBYTES sent and received)<br />
|
|
|
|
0: SPI transfer in progress</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="even">
|
|
|
|
<td>27</td>
|
|
<td>CS</td>
|
|
<td>CS</td>
|
|
<td align="center">0</td>
|
|
<td align="center">0</td>
|
|
<td>Chip select bit. <em>Inverted with respect to SPI chip select, which is normally active low.</em><br />
|
|
<td>Chip select bit. <em>Inverted with respect to SPI chip select, which is normally active low.</em><br />
|
|
1: Selects the Flash chip (CS pin = 0)<br />
|
|
1: Selects the Flash chip (CS pin = 0)<br />
|
|
0: Flash chip not selected (CS pin = 1)</td>
|
|
0: Flash chip not selected (CS pin = 1)</td>
|
|
</tr>
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
|
|
<td>26</td>
|
|
|
|
<td>XFER</td>
|
|
|
|
<td align="center">0</td>
|
|
|
|
<td>1: Start sending NBYTES over SPI</td>
|
|
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
<td>9</td>
|
|
<td>25..24</td>
|
|
<td>READY</td>
|
|
<td>NBYTES</td>
|
|
<td align="center">0</td>
|
|
<td align="center">0</td>
|
|
<td>1: SPI transfer is ready<br />
|
|
<td>Number of bytes to send during one transfer. If it is set to 0, no transfer will take place</td>
|
|
0: SPI transfer in progress</td>
|
|
|
|
</tr>
|
|
</tr>
|
|
<tr class="odd">
|
|
<tr class="odd">
|
|
<td>8</td>
|
|
<td>23..16</td>
|
|
<td>XFER</td>
|
|
<td>DATA [2]</td>
|
|
<td align="center">0</td>
|
|
<td align="center">0x00</td>
|
|
<td>1: Start SPI transfer</td>
|
|
<td>Write this register with the value of data byte 2<br />
|
|
|
|
After an SPI transfer, this register contains the value of data byte 2 read from the flash</td>
|
|
</tr>
|
|
</tr>
|
|
<tr class="even">
|
|
<tr class="even">
|
|
|
|
<td>15..8</td>
|
|
|
|
<td>DATA [1]</td>
|
|
|
|
<td align="center">0x00</td>
|
|
|
|
<td>Write this register with the value of data byte 1<br />
|
|
|
|
After an SPI transfer, this register contains the value of data byte 1 read from the flash</td>
|
|
|
|
</tr>
|
|
|
|
<tr class="odd">
|
|
<td>7..0</td>
|
|
<td>7..0</td>
|
|
<td>DATA</td>
|
|
<td>DATA [0]</td>
|
|
<td align="center">0x00</td>
|
|
<td align="center">0x00</td>
|
|
<td>Write this register with the next data byte to be written to the flash chip<br />
|
|
<td>Write this register with the value of data byte 0<br />
|
|
After an SPI transfer, this register contains the value read from the flash</td>
|
|
After an SPI transfer, this register contains the value of data byte 0 read from the flash</td>
|
|
</tr>
|
|
</tr>
|
|
</tbody>
|
|
</tbody>
|
|
</table>
|
|
</table>
|
|
|
|
|
|
|
|
The example below shows the setting of the FAR register for different
|
|
|
|
number of data bytes sent to the chip.
|
|
|
|
|
|
|
|
Sending bytes 0xAA 0xBB (in that order) to the flash chip:
|
|
|
|
|
|
|
|
DATA[0] = 0xAA
|
|
|
|
DATA[1] = 0xBB
|
|
|
|
DATA[2] = unimportant
|
|
|
|
NBYTES = 0x2
|
|
|
|
XFER = 1
|
|
|
|
CS = 1
|
|
|
|
|
|
|
|
FAR = 0x0E00BBAA
|
|
|
|
|
|
|
|
|
|
|
|
Sending bytes 0x11 0x22 0x33 (in that order) to the flash chip:
|
|
|
|
|
|
|
|
DATA[0] = 0x11
|
|
|
|
DATA[1] = 0x22
|
|
|
|
DATA[2] = 0x33
|
|
|
|
NBYTES = 0x3
|
|
|
|
XFER = 1
|
|
|
|
CS = 1
|
|
|
|
|
|
|
|
FAR = 0x0F332211
|
|
|
|
|
|
-----
|
|
-----
|
|
|
|
|
|
## References
|
|
## References
|
... | | ... | |