... | @@ -643,8 +643,93 @@ number of data bytes sent to the chip. |
... | @@ -643,8 +643,93 @@ number of data bytes sent to the chip. |
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FAR = 0x0E332211
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FAR = 0x0E332211
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-----
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## Finite-state machine
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## Finite-state machine
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A simplified block diagram of the MultiBoot FSM is shown below. In VHDL,
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the FSM is comprised of several states that lead to the phase being
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completed, but most of these states have been omitted for ease of
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understanding.
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![](/uploads/08c937264a9d16cdd0097716e4ea286a/multiboot-fsm.png)
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The following table describes these phases. More involved descriptions
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on each phase are given below.
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<table>
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<tbody>
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<tr class="odd">
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<td><b> Phase </b></td>
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<td><b> Description </b></td>
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</tr>
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<tr class="even">
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<td><strong>IDLE</strong></td>
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<td>Wait for one of the following control bits to be set:<br />
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CR.RDCFGREG<br />
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CR.IPROG (after CR.IPROG_UNL)<br />
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FAR.XFER</td>
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</tr>
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<tr class="odd">
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<td><strong>SPI transfer</strong></td>
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<td>Shift out NBYTES of the three DATA fields in the FAR register, and simultaneously shift in data received from the flash. When NBYTES have been sent, FAR.READY is written high and the FSM returns to IDLE</td>
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</tr>
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<tr class="even">
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<td><strong>IPROG</strong></td>
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<td>IPROG sequence (Table 7-1, p.130 [[1]](/xil-multiboot#References))</td>
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</tr>
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<tr class="odd">
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<td><strong>Read status register</strong></td>
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<td>Configuration register readout sequence (Table 6-1, p.130 [[1]](/xil-multiboot#References))</td>
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</tr>
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</tbody>
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</table>
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On reset and when not performing any work, the FSM is in the **IDLE**
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state. It waits in this state until one (and only one) of these control
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signals from **multiboot\_regs** are set:
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- CR.RDCFGREG
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- CR.IPROG
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- FAR.XFER
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Depending on which of these three bits are set, the FSM goes into one of
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the three possible states.
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In the **SPI transfer** phase, the FSM transfers up to three bytes to
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the SPI flash chip. The FSM sends one byte at a time to the
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*spi\_master** module and sets the appropriate control signals of this
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module. The **spi\_master** then handles shifting out each bit in the
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byte and simultaneously shifting in a byte from the flash. When a byte
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has been shifted out from the FPGA and in from the flash, the
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*spi\_master** module signals the FSM. The FSM then stores the received
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byte in the FAR.DATA \[0\] field and proceeds to shift out the next
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byte, if NBYTES \> 0. When the **spi\_master** sends and receives the
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second byte from the flash, this second byte received is stored in the
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FAR.DATA \[1\] field. Up to three bytes can be sent in this manner,
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depending on the value of the NBYTES field. After NBYTES bytes have been
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sent out, the FSM goes back into the IDLE state, setting the FAR.READY
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signal. The value of the DATA fields in the FAR now contain valid data,
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in the case of a read.
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In the **IPROG** phase, the FSM performs the steps listed in Table 7-1,
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p.130 of [\[1\]](/xil-multiboot#References), to initiate the IPROG
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command. It sends the values listed in this table to the ICAP component
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to initiate the IPROG command. Note that after the IPROG command has
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been initiated, the FPGA starts reconfiguring itself with the data in
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the flash chip and no further user control is possible on the FPGA until
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it has been reconfigured.
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In the **Read status register** stage, the FSM performs the steps listed
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in Table 6-1, p.130 of [\[1\]](/xil-multiboot#References). If the
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CR.RDCFGREG bit is set, the FSM will perform this sequence to read the
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configuration register at the address specified in CR.CFGREGADR. After
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this sequence is complete, the valid bit of the image register
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(IMGR.VALID) is set and the value of the configuration register is
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present in the lower half of the image register (IMGR.CFGREGIMG).
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-----
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## SPI master interface
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## SPI master interface
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The **spi\_master** module in the **xil\_multiboot** module implements
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The **spi\_master** module in the **xil\_multiboot** module implements
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