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# Xilinx Multiboot module
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This page describes the **xil\_multiboot** module, a VHDL module aiding
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in remotely reprogramming a Xilinx FPGA. The module will be capable of
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writing bitstreams for Xilinx FPGAs **only** and will contain (at least
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at the beginning) Xilinx IP modules.
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Its main features are:
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- receives a bitstream sent via Wishbone
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- writes the bitstream to an external Flash chip
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- issues a programming command to the Xilinx FPGA, which starts
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reprogramming the FPGA with the new bitstream
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## Multiboot basics
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Xilinx Multiboot technology [\[1\]](/xil-multiboot#References) allows
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reprogramming an FPGA by downloading a bitstream to a PROM chip external
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to the FPGA and then issuing an IPROG command to the configuration logic
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of the FPGA. This command triggers deleting the configuration of the
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FPGA and rewriting it with the new configuration written to the PROM.
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Multiple bitstreams may exist in the PROM at the same time, as outlined
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in the figure below:
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- Header bitstream - contains sync word, multiboot and golden
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bitstream addresses and the IPROG command
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- Multiboot bitstream - the bitstream that is normally loaded when the
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IPROG command is issued
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- Golden bitstream - the bitstream loaded if the multiboot bitstream
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load fails
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A strike count is used to select which bitstream gets loaded; it
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increments every time there is an error:
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- if it is 0..2, the multiboot bitstream gets loaded
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- if it is 3..5, the golden bitstream gets loaded
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- if it is 6..8, the header bitstream gets loaded
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- if it is 9, configuration is halted
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## Workflow
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In order to remotely reprogram a Xilinx FPGA, the following workflow is
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employed [\[2\]](/xil-multiboot#References):
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1. Prepare a Xilinx FPGA bitstream
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2. Erase the sector of the flash chip containing the bitstream
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3. Send the bitstream to the FPGA system via the protocol of choice
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(e.g. ELMA protocol)
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4. Translate the protocol into Wishbone via a Wishbone bridge (e.g.
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elma\_i2c)
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5. Download the bitstream to the flash chip via the FPGA
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6. Issue a reprogramming command from the FPGA
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## References
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\[1\] [Xilinx UG380: Spartan-6 FPGA Configuration, User
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Guide](http://www.xilinx.com/support/documentation/user_guides/ug380.pdf)
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\[2\] [Xilinx SP605 MultiBoot
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Design](http://www.xilinx.com/support/documentation/boards_and_kits/xtp059.pdf)
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