... | @@ -694,7 +694,7 @@ When NBYTES have been sent, FAR.READY is written high and the FSM returns to IDL |
... | @@ -694,7 +694,7 @@ When NBYTES have been sent, FAR.READY is written high and the FSM returns to IDL |
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td><strong>Read status register</strong></td>
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<td><strong>Read status register</strong></td>
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<td>Configuration register readout sequence (Table 6-1, p.130 [[1]](/xil-multiboot#References))</td>
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<td>Configuration register readout sequence (Table 6-1, p.113 [[1]](/xil-multiboot#References))</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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... | @@ -735,7 +735,7 @@ the flash chip and no further user control is possible on the FPGA until |
... | @@ -735,7 +735,7 @@ the flash chip and no further user control is possible on the FPGA until |
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it has been reconfigured.
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it has been reconfigured.
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In the **Read status register** stage, the FSM performs the steps listed
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In the **Read status register** stage, the FSM performs the steps listed
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in Table 6-1, p.130 of [\[1\]](/xil-multiboot#References). If the
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in Table 6-1, p.113 of [\[1\]](/xil-multiboot#References). If the
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CR.RDCFGREG bit is set, the FSM will perform this sequence to read the
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CR.RDCFGREG bit is set, the FSM will perform this sequence to read the
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configuration register at the address specified in CR.CFGREGADR. After
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configuration register at the address specified in CR.CFGREGADR. After
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this sequence is complete, the valid bit of the image register
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this sequence is complete, the valid bit of the image register
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... | | ... | |