... | @@ -47,16 +47,27 @@ increments every time there is an error: |
... | @@ -47,16 +47,27 @@ increments every time there is an error: |
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## Workflow
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## Workflow
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In order to remotely reprogram a Xilinx FPGA, the following workflow is
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In order to remotely reprogram a Xilinx FPGA using the
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employed [\[2\]](/xil-multiboot#References):
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*xil\_multiboot** module, the following workflow is employed
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[\[2\]](/xil-multiboot#References):
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1. Prepare a Xilinx FPGA bitstream
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1. Prepare a Xilinx FPGA bitstream
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2. Erase the sector of the Flash chip containing the bitstream
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2. Erase the sector if on a sector boundary, or erase the number of
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3. Send the bitstream to the FPGA system via software
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sectors needed to write the bitstream
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4. Translate the protocol into Wishbone via a Wishbone bridge (e.g.
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3. Split the bistream into flash pages and send it to the flash via the
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vbcp\_wb)
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FAR register
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5. Download the bitstream to the Flash chip via the FPGA
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4. Repeat the previous two steps until the bitstream has been sent
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6. Issue a reprogramming command to the FPGA
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5. Write the MultiBoot bitstream start address and flash chip read
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command op-code into the MBBAR register
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6. Write the golden bitstream start address and flash chip read command
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op-code into the GBBAR register
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7. Unlock the IPROG bit in the FPGA by setting CR.IPROG\_UNL bit
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8. Issue a reprogramming command to the FPGA by setting to the CR.IPROG
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bit
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9. Wait for reprogramming to finish
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10. Issue a read from the FPGA programming logic BOOTSTS register, by
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setting CR.BOOTSTS
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11. Read SR register and make sure it returns 0x10001
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-----
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-----
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