... | @@ -313,7 +313,7 @@ consists of the following blocks: |
... | @@ -313,7 +313,7 @@ consists of the following blocks: |
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<td>Control Register</td>
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<td>Control Register</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>[IMGR](xil-multiboot#imgr)</td>
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<td>[SR](xil-multiboot#sr)</td>
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<td align="center">0x004</td>
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<td align="center">0x004</td>
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<td align="center">R/O</td>
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<td align="center">R/O</td>
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<td>Configuration Image Register</td>
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<td>Configuration Image Register</td>
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... | @@ -405,14 +405,14 @@ Notes on the control register: |
... | @@ -405,14 +405,14 @@ Notes on the control register: |
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descriptions)
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descriptions)
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- set the RDCFGREG bit to initiate the read
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- set the RDCFGREG bit to initiate the read
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- the value of the configuration register can be found in the
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- the value of the configuration register can be found in the
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[image register (IMGR)](xil-multiboot#imgr), if the IMGR.VALID
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[image register (SR)](xil-multiboot#sr), if the SR.IMGVALID bit
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bit is set
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is set
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- In order to issue the IPROG command to the FPGA, the IPROG bit first
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- In order to issue the IPROG command to the FPGA, the IPROG bit first
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needs to be unlocked by setting the IPROG\_UNL bit
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needs to be unlocked by setting the IPROG\_UNL bit
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- After the IPROG command is issued, the FPGA will initiate the
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- After the IPROG command is issued, the FPGA will initiate the
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programming sequence
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programming sequence
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### IMGR
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### SR
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*Offset: 0x04**
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*Offset: 0x04**
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... | @@ -425,18 +425,25 @@ Notes on the control register: |
... | @@ -425,18 +425,25 @@ Notes on the control register: |
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<td><b> Description </b></td>
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<td><b> Description </b></td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>31..17</td>
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<td>31..18</td>
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<td><em>Reserved</em></td>
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<td><em>Reserved</em></td>
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<td align="center">X</td>
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<td align="center">X</td>
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<td>Reserved bits read undefined; they should be written as '0'</td>
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<td>Reserved bits read undefined; they should be written as '0'</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>16</td>
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<td>17</td>
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<td>VALID</td>
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<td>WDTO</td>
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<td align="center">0</td>
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<td align="center">0</td>
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<td>Indicates the SR contents are valid, i.e., a read from a configuration register has been performed</td>
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<td>When '1', a watchdog time-out has occured on the MultiBoot FSM<br />
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This bit can be cleared by writing a '1' to it</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>16</td>
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<td>IMGVALID</td>
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<td align="center">0</td>
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<td>Indicates the CFGREGIMG contents are valid, i.e., a read from a configuration register has been performed</td>
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</tr>
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<tr class="odd">
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<td>15..0</td>
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<td>15..0</td>
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<td>CFGREGIMG</td>
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<td>CFGREGIMG</td>
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<td align="center">0</td>
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<td align="center">0</td>
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... | @@ -447,14 +454,14 @@ Notes on the control register: |
... | @@ -447,14 +454,14 @@ Notes on the control register: |
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Notes on the image register:
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Notes on the image register:
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- the IMGR is only valid after read from the FPGA's configuration
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- the SR is only valid after read from the FPGA's configuration
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register has been performed, by setting bit 6 in
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register has been performed, by setting bit 6 in
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[CR](xil-multiboot#cr)
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[CR](xil-multiboot#cr)
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- the VALID bit (bit 16) can be used to see if the current readout of
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- the IMGVALID bit (bit 16) can be used to see if the current readout
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the IMGR is valid
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of the configuration register image is valid
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- the VALID bit is set by the FSM when a read from the configuration
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- the IMGVALID bit is set by the FSM when a read from the
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register has been performed via the ICAP and cleared on
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configuration register has been performed via the ICAP and cleared
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reprogramming
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on reprogramming
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- bits 15..0 are an image of the configuration register (for details,
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- bits 15..0 are an image of the configuration register (for details,
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see the **Configuration Registers** section in
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see the **Configuration Registers** section in
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[\[1\]](/xil-multiboot#References))
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[\[1\]](/xil-multiboot#References))
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... | @@ -738,9 +745,26 @@ In the **Read status register** stage, the FSM performs the steps listed |
... | @@ -738,9 +745,26 @@ In the **Read status register** stage, the FSM performs the steps listed |
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in Table 6-1, p.113 of [\[1\]](/xil-multiboot#References). If the
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in Table 6-1, p.113 of [\[1\]](/xil-multiboot#References). If the
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CR.RDCFGREG bit is set, the FSM will perform this sequence to read the
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CR.RDCFGREG bit is set, the FSM will perform this sequence to read the
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configuration register at the address specified in CR.CFGREGADR. After
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configuration register at the address specified in CR.CFGREGADR. After
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this sequence is complete, the valid bit of the image register
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this sequence is complete, the IMGVALID bit of the status register
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(IMGR.VALID) is set and the value of the configuration register is
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(SR.IMGVALID) is set and the value of the configuration register is
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present in the lower half of the image register (IMGR.CFGREGIMG).
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present in the lower half of the image register (SR.CFGREGIMG).
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The FSM also contains a watchdog that resets the FSM if it stays too
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long outside the **IDLE** state. The watchdog gets reset by the FSM
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while it is in the **IDLE** state; when the FSM is triggered, it goes
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out of the **IDLE** state and the watchdog starts counting. Should the
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FSM stall for more than 512 cycles, the watchdog times out and it resets
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the FSM. At the same time, the WDTO bit in the [SR](xil-multiboot#sr) is
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set.
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The timeout value for the watchdog was selected based on the longest
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time the FSM is expected to stay outside the **IDLE** state. This time
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is spent while in the **SPI transfer** phase and it corresponds to the
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time to send three 8-bit bytes at an SPI clock cycle eight times slower
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than the FSM input clock cycle. This according to simulation results in
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a total of 218 clock cycles spent outside the **IDLE** state. The value
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512 was selected to account for longer delays that can occur in
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hardware.
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-----
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-----
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... | | ... | |