... | @@ -277,11 +277,11 @@ consists of the following blocks: |
... | @@ -277,11 +277,11 @@ consists of the following blocks: |
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<td>Control Register</td>
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<td>Control Register</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>[SR](xil-multiboot#sr)</td>
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<td>[IMGR](xil-multiboot#imgr)</td>
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<td align="center">0x004</td>
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<td align="center">0x004</td>
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<td align="center">R/O</td>
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<td align="center">R/O</td>
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<td align="center">0xXXXXXXXX</td>
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<td align="center">0xXXXXXXXX</td>
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<td>Status Register</td>
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<td>Configuration Image Register</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>[GBBAR](xil-multiboot#gbbar)</td>
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<td>[GBBAR](xil-multiboot#gbbar)</td>
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... | @@ -343,21 +343,47 @@ This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle</ |
... | @@ -343,21 +343,47 @@ This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle</ |
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<td>Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing the IPROG bit</td>
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<td>Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing the IPROG bit</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>15..1</td>
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<td>15..7</td>
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<td><em>Reserved</em></td>
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<td><em>Reserved</em></td>
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<td align="center">X</td>
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<td align="center">X</td>
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<td>Reserved bits read undefined; they should be written as '0'</td>
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<td>Reserved bits read undefined; they should be written as '0'</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>0</td>
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<td>6</td>
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<td>RDBOOTSTS</td>
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<td>RDCFGREG</td>
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<td align="center">0</td>
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<td>Initiate a read from the FPGA configuration register at address CFGREGADR</td>
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</tr>
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<tr class="odd">
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<td>5..0</td>
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<td>CFGREGADR</td>
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<td align="center">0</td>
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<td align="center">0</td>
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<td>Initiate read from FPGA's BOOTSTS register and copy to SR. This step needs to be done prior to reading the SR</td>
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<td>The address of the FPGA configuration register to read</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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### SR
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Notes on the control register:
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- In order to read a configuration register, the following steps are
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needed
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- set the address of the configuration register in the CFGREGADR
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field (see the **Configuration Registers** section in
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[\[1\]](/xil-multiboot#References) for configuration register
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descriptions)
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- set the RDCFGREG bit to initiate the read
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- the value of the configuration register can be found in the
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[image register (IMGR)](xil-multiboot#imgr), if the IMGR.VALID
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bit is set
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- In order to issue the IPROG command to the FPGA, the IPROG bit first
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needs to be unlocked by setting the IPROG\_UNL bit
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- After the IPROG command is issued, the FPGA will initiate the
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programming sequence
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- The status of the FPGA after reprogramming can be checked via the
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BOOTSTS and STAT configuration registers (see the **Configuration
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Registers** section in [\[1\]](/xil-multiboot#References))
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### IMGR
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*Offset: 0x04**
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*Offset: 0x04**
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... | @@ -370,110 +396,38 @@ This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle</ |
... | @@ -370,110 +396,38 @@ This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle</ |
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<td><b> Description </b></td>
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<td><b> Description </b></td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>31</td>
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<td>31..17</td>
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<td>VALID</td>
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<td align="center">0</td>
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<td>Indicates the SR contents are valid, i.e., a read from BOOTSTS has been performed</td>
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</tr>
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<tr class="odd">
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<td>30..16</td>
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<td><em>Reserved</em></td>
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<td align="center">X</td>
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<td>Reserved bits read undefined; they should be written as '0'</td>
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</tr>
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<tr class="even">
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<td>15..12</td>
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<td>STRIKE_CNT</td>
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<td align="center">0</td>
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<td>Strike count</td>
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</tr>
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<tr class="odd">
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<td>11</td>
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<td>CRC_ERROR_1</td>
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<td align="center">0</td>
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<td>CRC error</td>
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</tr>
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<tr class="even">
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<td>10</td>
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<td>ID_ERROR_1</td>
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<td align="center">0</td>
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<td>IDCODE not validated while trying to write FDRI</td>
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</tr>
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<tr class="odd">
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<td>9</td>
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<td>WTO_ERROR_1</td>
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<td align="center">0</td>
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<td>Watchdog time-out error</td>
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</tr>
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<tr class="even">
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<td>8</td>
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<td><em>Reserved</em></td>
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<td align="center">X</td>
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<td>Reserved bits read undefined; they should be written as '0'</td>
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</tr>
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<tr class="odd">
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<td>7</td>
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<td>FALLBACK_1</td>
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<td align="center">0</td>
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<td>1: Fallback to 0 0 address<br />
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0: Normal configuration</td>
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</tr>
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<tr class="even">
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<td>6</td>
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<td>VALID_1</td>
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<td align="center">0</td>
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<td>Status in BOOTSTS is valid</td>
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</tr>
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<tr class="odd">
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<td>5</td>
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<td>CRC_ERROR_0</td>
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<td align="center">0</td>
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<td>CRC error</td>
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</tr>
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<tr class="even">
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<td>4</td>
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<td>ID_ERROR_0</td>
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<td align="center">0</td>
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<td>IDCODE not validated while trying to write FDRI</td>
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</tr>
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<tr class="odd">
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<td>3</td>
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<td>WTO_ERROR_0</td>
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<td align="center">0</td>
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<td>Watchdog time-out error</td>
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</tr>
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<tr class="even">
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<td>2</td>
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<td><em>Reserved</em></td>
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<td><em>Reserved</em></td>
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<td align="center">X</td>
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<td align="center">X</td>
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<td>Reserved bits read undefined; they should be written as '0'</td>
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<td>Reserved bits read undefined; they should be written as '0'</td>
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</tr>
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</tr>
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<tr class="odd">
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<tr class="odd">
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<td>1</td>
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<td>16</td>
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<td>FALLBACK_0</td>
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<td>VALID</td>
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<td align="center">0</td>
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<td align="center">0</td>
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<td>1: Fallback to golden bit stream address<br />
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<td>Indicates the SR contents are valid, i.e., a read from a configuration register has been performed</td>
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0: Normal configuration</td>
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</tr>
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</tr>
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<tr class="even">
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<tr class="even">
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<td>0</td>
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<td>15..0</td>
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<td>VALID_0</td>
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<td>CFGREGIMG</td>
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<td align="center">0</td>
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<td align="center">0</td>
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<td>Status valid</td>
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<td>Image of the FPGA configuration register</td>
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</tr>
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</tr>
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</tbody>
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</tbody>
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</table>
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</table>
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Notes on the status register:
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Notes on the status register:
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- the SR is only valid after read from the FPGA's BOOTSTS register has
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- the IMGR is only valid after read from the FPGA's configuration
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been performed, by setting bit 0 in CR
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register has been performed, by setting bit 0 in CR
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- the VALID bit (bit 31) can be used to see if the current readout of
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- the VALID bit (bit 16) can be used to see if the current readout of
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the SR is valid
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the IMGR is valid
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- the VALID bit is set by the FSM when a read from the BOOTSTS
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- the VALID bit is set by the FSM when a read from the configuration
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register is made via the ICAP and cleared on reprogramming
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register has been performed via the ICAP and cleared on
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- bits 15..0 are an image of the BOOTSTS register (for details, see
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reprogramming
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pages 104 and 131 of [\[1\]](/xil-multiboot#References))
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- bits 15..0 are an image of the configuration register (for details,
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see the **Configuration Registers** section in
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[\[1\]](/xil-multiboot#References))
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### GBBAR
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### GBBAR
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... | | ... | |