... | ... | @@ -142,50 +142,22 @@ needed, or a total of 23 sectors |
|
|
The following flash memory map can be used if the Golden bitstream is
|
|
|
automatically generated:
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td align="center">* Address *</td>
|
|
|
<td align="center">* Bitstream *</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td align="center">0x000000</td>
|
|
|
<td align="center">Header</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td align="center">0x000044</td>
|
|
|
<td align="center">Golden</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td align="center">0x170000</td>
|
|
|
<td align="center">MultiBoot</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|* Address *|* Bitstream *|
|
|
|
|----|----|
|
|
|
|0x000000|Header|
|
|
|
|0x000044|Golden|
|
|
|
|0x170000|MultiBoot|
|
|
|
|
|
|
|
|
|
On the other hand, should it be desired to manually change the Golden
|
|
|
and Header bitstreams, the following address map can be selected:
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td align="center">* Address *</td>
|
|
|
<td align="center">* Bitstream *</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td align="center">0x000000</td>
|
|
|
<td align="center">Header</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td align="center">0x010000</td>
|
|
|
<td align="center">Golden</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td align="center">0x180000</td>
|
|
|
<td align="center">MultiBoot</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|* Address *|* Bitstream *|
|
|
|
|----|----|
|
|
|
|0x000000|Header|
|
|
|
|0x010000|Golden|
|
|
|
|0x180000|MultiBoot|
|
|
|
|
|
|
|
|
|
### Generating the Golden bitstream
|
|
|
|
... | ... | @@ -272,30 +244,13 @@ workarounds. |
|
|
A block diagram of the **xil\_multiboot** module is shown below. It
|
|
|
consists of the following blocks:
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Block </b></td>
|
|
|
<td><b> Description </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td><b> <strong>multiboot_regs</strong> </b></td>
|
|
|
<td>Wishbone interface and registers</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td><b> <strong>multiboot_fsm</strong> </b></td>
|
|
|
<td>Main FSM of the multiboot block</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td><b> <strong>icap_spartan6</strong> </b></td>
|
|
|
<td>Xilinx ICAP IP core</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td><b> <strong>spi_master</strong> </b></td>
|
|
|
<td>SPI master from the bootloader design under the <a href="https://www.ohwr.org/project/svec">SVEC</a> project</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Block**|**Description**|
|
|
|
|----|----|
|
|
|
|** **multiboot_regs** **|Wishbone interface and registers|
|
|
|
|** **multiboot_fsm** **|Main FSM of the multiboot block|
|
|
|
|** **icap_spartan6** **|Xilinx ICAP IP core|
|
|
|
|** **spi_master** **|SPI master from the bootloader design under the [SVEC](https://www.ohwr.org/project/svec) project|
|
|
|
|
|
|
|
|
|
![](/uploads/33a36e7b8449344d15f9df9dc610d6a2/multiboot-bd.png)
|
|
|
|
... | ... | @@ -303,46 +258,14 @@ consists of the following blocks: |
|
|
|
|
|
## Register map
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Register </b></td>
|
|
|
<td align="center">* Offset *</td>
|
|
|
<td align="center">* Access *</td>
|
|
|
<td><b> Description </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>[CR](xil-multiboot#cr)</td>
|
|
|
<td align="center">0x000</td>
|
|
|
<td align="center">R/W</td>
|
|
|
<td>Control Register</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>[SR](xil-multiboot#sr)</td>
|
|
|
<td align="center">0x004</td>
|
|
|
<td align="center">R/O</td>
|
|
|
<td>Configuration Image Register</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>[GBBAR](xil-multiboot#gbbar)</td>
|
|
|
<td align="center">0x008</td>
|
|
|
<td align="center">R/W</td>
|
|
|
<td>Golden Bitstream Base Address Register</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>[MBBAR](xil-multiboot#mbbar)</td>
|
|
|
<td align="center">0x00C</td>
|
|
|
<td align="center">R/W</td>
|
|
|
<td>MultiBoot Bitstream Base Address Register</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>[FAR](xil-multiboot#far)</td>
|
|
|
<td align="center">0x010</td>
|
|
|
<td align="center">R/W</td>
|
|
|
<td>Flash Access Register</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Register**|* Offset *|* Access *|**Description**|
|
|
|
|----|----|----|----|
|
|
|
|[CR](xil-multiboot#cr)|0x000|R/W|Control Register|
|
|
|
|[SR](xil-multiboot#sr)|0x004|R/O|Configuration Image Register|
|
|
|
|[GBBAR](xil-multiboot#gbbar)|0x008|R/W|Golden Bitstream Base Address Register|
|
|
|
|[MBBAR](xil-multiboot#mbbar)|0x00C|R/W|MultiBoot Bitstream Base Address Register|
|
|
|
|[FAR](xil-multiboot#far)|0x010|R/W|Flash Access Register|
|
|
|
|
|
|
|
|
|
The GBBAR and MBBAR are images of the GENERAL1..4 configuration
|
|
|
registers [\[1\]](/xil-multiboot#References) in the Xilinx Spartan-6
|
... | ... | @@ -352,53 +275,16 @@ FPGA. |
|
|
|
|
|
*Offset: 0x00**
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Bits </b></td>
|
|
|
<td><b> Field </b></td>
|
|
|
<td align="center">* Default *</td>
|
|
|
<td><b> Description </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>31..18</td>
|
|
|
<td><em>Reserved</em></td>
|
|
|
<td align="center">X</td>
|
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>17</td>
|
|
|
<td>IPROG</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>When 1, it triggers the FSM to send the IPROG command to the ICAP controller<br />
|
|
|
This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>16</td>
|
|
|
<td>IPROG_UNL</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing the IPROG bit</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>15..7</td>
|
|
|
<td><em>Reserved</em></td>
|
|
|
<td align="center">X</td>
|
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>6</td>
|
|
|
<td>RDCFGREG</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>Initiate a read from the FPGA configuration register at address CFGREGADR</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>5..0</td>
|
|
|
<td>CFGREGADR</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>The address of the FPGA configuration register to read</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Bits**|**Field**|* Default *|**Description**|
|
|
|
|----|----|----|----|
|
|
|
|31..18|Reserved|X|Reserved bits read undefined; they should be written as '0'|
|
|
|
|17|IPROG|0|When 1, it triggers the FSM to send the IPROG command to the ICAP controller
|
|
|
This bit needs to be unlocked by setting the IPROG_UNL bit in a previous cycle|
|
|
|
|16|IPROG_UNL|0|Unlock bit for the IPROG command. This bit needs to be set to 1 prior to writing the IPROG bit|
|
|
|
|15..7|Reserved|X|Reserved bits read undefined; they should be written as '0'|
|
|
|
|6|RDCFGREG|0|Initiate a read from the FPGA configuration register at address CFGREGADR|
|
|
|
|5..0|CFGREGADR|0|The address of the FPGA configuration register to read|
|
|
|
|
|
|
|
|
|
Notes on the control register:
|
|
|
|
... | ... | @@ -421,41 +307,14 @@ Notes on the control register: |
|
|
|
|
|
*Offset: 0x04**
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Bits </b></td>
|
|
|
<td><b> Field </b></td>
|
|
|
<td align="center">* Default *</td>
|
|
|
<td><b> Description </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>31..18</td>
|
|
|
<td><em>Reserved</em></td>
|
|
|
<td align="center">X</td>
|
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>17</td>
|
|
|
<td>WDTO</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>When '1', a watchdog time-out has occured on the MultiBoot FSM<br />
|
|
|
This bit can be cleared by writing a '1' to it</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>16</td>
|
|
|
<td>IMGVALID</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>Indicates the CFGREGIMG contents are valid, i.e., a read from a configuration register has been performed</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>15..0</td>
|
|
|
<td>CFGREGIMG</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>Image of the FPGA configuration register</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Bits**|**Field**|* Default *|**Description**|
|
|
|
|----|----|----|----|
|
|
|
|31..18|Reserved|X|Reserved bits read undefined; they should be written as '0'|
|
|
|
|17|WDTO|0|When '1', a watchdog time-out has occured on the MultiBoot FSM
|
|
|
This bit can be cleared by writing a '1' to it|
|
|
|
|16|IMGVALID|0|Indicates the CFGREGIMG contents are valid, i.e., a read from a configuration register has been performed|
|
|
|
|15..0|CFGREGIMG|0|Image of the FPGA configuration register|
|
|
|
|
|
|
|
|
|
Notes on the image register:
|
|
|
|
... | ... | @@ -480,28 +339,11 @@ This register is an image of the GENERAL3,4 |
|
|
Spartan-6 FPGAs. Its contents are copied to the configuration registers
|
|
|
as part of the configuration sequence of the FPGA.
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Bits </b></td>
|
|
|
<td><b> Field </b></td>
|
|
|
<td align="center">* Default *</td>
|
|
|
<td><b> Description </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>31..24</td>
|
|
|
<td>OPCODE</td>
|
|
|
<td align="center">0x00</td>
|
|
|
<td>Read op-code to be sent to Flash chip</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>23..0</td>
|
|
|
<td>GBA</td>
|
|
|
<td align="center">0x000000</td>
|
|
|
<td>Golden bitstream start address in Flash memory</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Bits**|**Field**|* Default *|**Description**|
|
|
|
|----|----|----|----|
|
|
|
|31..24|OPCODE|0x00|Read op-code to be sent to Flash chip|
|
|
|
|23..0|GBA|0x000000|Golden bitstream start address in Flash memory|
|
|
|
|
|
|
|
|
|
*Guidelines on selecting a GBBAR:**
|
|
|
|
... | ... | @@ -520,28 +362,11 @@ This register is an image of the GENERAL1,2 |
|
|
Spartan-6 FPGAs. Its contents are copied to the configuration registers
|
|
|
as part of the configuration sequence of the FPGA.
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Bits </b></td>
|
|
|
<td><b> Field </b></td>
|
|
|
<td align="center">* Default *</td>
|
|
|
<td><b> Description </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>31..24</td>
|
|
|
<td>OPCODE</td>
|
|
|
<td align="center">0x00</td>
|
|
|
<td>Read op-code to be sent to Flash chip</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>23..0</td>
|
|
|
<td>MBA</td>
|
|
|
<td align="center">0x000000</td>
|
|
|
<td>MultiBoot bitstream start address in Flash memory</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Bits**|**Field**|* Default *|**Description**|
|
|
|
|----|----|----|----|
|
|
|
|31..24|OPCODE|0x00|Read op-code to be sent to Flash chip|
|
|
|
|23..0|MBA|0x000000|MultiBoot bitstream start address in Flash memory|
|
|
|
|
|
|
|
|
|
*Guidelines on selecting an MBBAR:**
|
|
|
|
... | ... | @@ -571,76 +396,29 @@ done at the same time via one write to the FAR): |
|
|
the order DATA \[0\], DATA \[1\], DATA \[2\]), and the DATA fields
|
|
|
contain NBYTES+1 bytes read from the flash chip.
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Bits </b></td>
|
|
|
<td><b> Field </b></td>
|
|
|
<td align="center">* Default *</td>
|
|
|
<td><b> Description </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>31..29</td>
|
|
|
<td><em>Reserved</em></td>
|
|
|
<td align="center">X</td>
|
|
|
<td>Reserved bits read undefined; they should be written as '0'</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>28</td>
|
|
|
<td>READY</td>
|
|
|
<td align="center">1</td>
|
|
|
<td>1: SPI transfer is ready (NBYTES sent and received)<br />
|
|
|
0: SPI transfer in progress</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>27</td>
|
|
|
<td>CS</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>Chip select bit. <em>Inverted with respect to SPI chip select, which is normally active low.</em><br />
|
|
|
1: Selects the Flash chip (CS pin = 0)<br />
|
|
|
0: Flash chip not selected (CS pin = 1)</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>26</td>
|
|
|
<td>XFER</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>1: Start sending NBYTES over SPI<br />
|
|
|
0: No effect<br />
|
|
|
This bit clears itself automatically</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>25..24</td>
|
|
|
<td>NBYTES</td>
|
|
|
<td align="center">0</td>
|
|
|
<td>Number of bytes to send during one transfer<br />
|
|
|
0: send DATA [0]<br />
|
|
|
1: send DATA [0], DATA [1]<br />
|
|
|
2: send DATA [0], DATA [1], DATA [2]<br />
|
|
|
3: <em>Reserved</em></td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>23..16</td>
|
|
|
<td>DATA [2]</td>
|
|
|
<td align="center">0x00</td>
|
|
|
<td>Write this register with the value of data byte 2<br />
|
|
|
After an SPI transfer, this register contains the value of data byte 2 read from the flash</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td>15..8</td>
|
|
|
<td>DATA [1]</td>
|
|
|
<td align="center">0x00</td>
|
|
|
<td>Write this register with the value of data byte 1<br />
|
|
|
After an SPI transfer, this register contains the value of data byte 1 read from the flash</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td>7..0</td>
|
|
|
<td>DATA [0]</td>
|
|
|
<td align="center">0x00</td>
|
|
|
<td>Write this register with the value of data byte 0<br />
|
|
|
After an SPI transfer, this register contains the value of data byte 0 read from the flash</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Bits**|**Field**|* Default *|**Description**|
|
|
|
|----|----|----|----|
|
|
|
|31..29|Reserved|X|Reserved bits read undefined; they should be written as '0'|
|
|
|
|28|READY|1|1: SPI transfer is ready (NBYTES sent and received)
|
|
|
0: SPI transfer in progress|
|
|
|
|27|CS|0|Chip select bit. Inverted with respect to SPI chip select, which is normally active low.
|
|
|
1: Selects the Flash chip (CS pin = 0)
|
|
|
0: Flash chip not selected (CS pin = 1)|
|
|
|
|26|XFER|0|1: Start sending NBYTES over SPI
|
|
|
0: No effect
|
|
|
This bit clears itself automatically|
|
|
|
|25..24|NBYTES|0|Number of bytes to send during one transfer
|
|
|
0: send DATA [0]
|
|
|
1: send DATA [0], DATA [1]
|
|
|
2: send DATA [0], DATA [1], DATA [2]
|
|
|
3: Reserved|
|
|
|
|23..16|DATA [2]|0x00|Write this register with the value of data byte 2
|
|
|
After an SPI transfer, this register contains the value of data byte 2 read from the flash|
|
|
|
|15..8|DATA [1]|0x00|Write this register with the value of data byte 1
|
|
|
After an SPI transfer, this register contains the value of data byte 1 read from the flash|
|
|
|
|7..0|DATA [0]|0x00|Write this register with the value of data byte 0
|
|
|
After an SPI transfer, this register contains the value of data byte 0 read from the flash|
|
|
|
|
|
|
|
|
|
The example below shows the setting of the FAR register for different
|
|
|
number of data bytes sent to the chip.
|
... | ... | @@ -682,34 +460,17 @@ understanding. |
|
|
The following table describes these phases. More involved descriptions
|
|
|
on each phase are given below.
|
|
|
|
|
|
<table>
|
|
|
<tbody>
|
|
|
<tr class="odd">
|
|
|
<td><b> Phase </b></td>
|
|
|
<td><b> Description </b></td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td><strong>IDLE</strong></td>
|
|
|
<td>Wait for one of the following control bits to be set:<br />
|
|
|
CR.RDCFGREG<br />
|
|
|
CR.IPROG (after CR.IPROG_UNL)<br />
|
|
|
FAR.XFER</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td><strong>SPI transfer</strong></td>
|
|
|
<td>Shift out NBYTES of the three DATA fields in the FAR register, and simultaneously shift in data received from the flash<br />
|
|
|
When NBYTES have been sent, FAR.READY is written high and the FSM returns to IDLE</td>
|
|
|
</tr>
|
|
|
<tr class="even">
|
|
|
<td><strong>IPROG</strong></td>
|
|
|
<td>IPROG sequence (Table 7-1, p.130 [[1]](/xil-multiboot#References))</td>
|
|
|
</tr>
|
|
|
<tr class="odd">
|
|
|
<td><strong>Read status register</strong></td>
|
|
|
<td>Configuration register readout sequence (Table 6-1, p.113 [[1]](/xil-multiboot#References))</td>
|
|
|
</tr>
|
|
|
</tbody>
|
|
|
</table>
|
|
|
|**Phase**|**Description**|
|
|
|
|----|----|
|
|
|
|**IDLE**|Wait for one of the following control bits to be set:
|
|
|
CR.RDCFGREG
|
|
|
CR.IPROG (after CR.IPROG_UNL)
|
|
|
FAR.XFER|
|
|
|
|**SPI transfer**|Shift out NBYTES of the three DATA fields in the FAR register, and simultaneously shift in data received from the flash
|
|
|
When NBYTES have been sent, FAR.READY is written high and the FSM returns to IDLE|
|
|
|
|**IPROG**|IPROG sequence (Table 7-1, p.130 [[1]](/xil-multiboot#References))|
|
|
|
|**Read status register**|Configuration register readout sequence (Table 6-1, p.113 [[1]](/xil-multiboot#References))|
|
|
|
|
|
|
|
|
|
On reset and when not performing any work, the FSM is in the **IDLE**
|
|
|
state. It waits in this state until one (and only one) of these control
|
... | ... | @@ -802,3 +563,4 @@ Design](http://www.xilinx.com/support/documentation/boards_and_kits/xtp059.pdf) |
|
|
|
|
|
Theodor-Adrian Stana, Oct. 2013
|
|
|
|
|
|
|