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# Xilinx MultiBoot module
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This page describes the **xil\_multiboot** module, a VHDL module aiding
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in remotely reprogramming a Xilinx FPGA. The module will be capable of
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writing bitstreams for Xilinx FPGAs **only** and will contain (at least
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at the beginning) Xilinx IP modules.
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This page describes the **xil\_multiboot** module, a VHDL module for
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remote reprogramming a Xilinx FPGA. The module will be capable of
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writing bitstreams for Xilinx FPGAs **only** and will contain Xilinx IP
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modules.
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Its main features are:
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- receives a bitstream sent via Wishbone
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- writes the bitstream to an external Flash chip
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- issues a programming command to the Xilinx FPGA, which starts
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reprogramming the FPGA with the new bitstream
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- software controls operation of the module:
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- Wishbone interface implements registers for control and status
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readout
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- writing FPGA bitstream data to the flash chip
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- issuing reprogramming command to the FPGA (via Xilinx ICAP
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[\[1\]](/xil-multiboot#References))
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- reading boot status register from the FPGA configuration logic
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(via Xilinx ICAP [\[1\]](/xil-multiboot#References))
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- a finite-state machine (FSM) controls writing to the flash chip and
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sending the IPROG command to the FPGA
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- modular, easily modifiable design
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- flash chip is controlled by software, so virtually any SPI flash
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chip is supported
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- Wishbone interface can easily be replaced by some other
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interconnect (e.g., AXI) by implementing the **multiboot\_regs**
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module
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-----
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... | ... | @@ -43,6 +55,10 @@ increments every time there is an error: |
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- if it is 6..8, the header bitstream gets loaded
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- if it is 9, configuration is halted
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This strike count can **only be reset** by power-down or pulling low the
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special PROGRAM\_B pin of the FPGA, so once the strike count hits three,
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one cannot go back into reprogramming the MultiBoot bitstream.
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-----
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## Workflow
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... | ... | @@ -61,13 +77,14 @@ In order to remotely reprogram a Xilinx FPGA using the |
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command op-code into the MBBAR register
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6. Write the golden bitstream start address and flash chip read command
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op-code into the GBBAR register
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7. Unlock the IPROG bit in the FPGA by setting CR.IPROG\_UNL bit
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8. Issue a reprogramming command to the FPGA by setting to the CR.IPROG
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7. Unlock the IPROG bit in the FPGA by setting the CR.IPROG\_UNL bit
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8. Issue a reprogramming command to the FPGA by setting the CR.IPROG
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bit
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9. Wait for reprogramming to finish
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10. Issue a read from the FPGA programming logic BOOTSTS register, by
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setting CR.BOOTSTS
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11. Read SR register and make sure it returns 0x10001
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11. Read SR register and make sure no error bits in the BOOTSTS image
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are set
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-----
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... | ... | @@ -169,9 +186,9 @@ the golden bitstream during design implementation: |
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All this can be done from the GUI of Xilinx ISE:
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- Right-click **Generate Programming File** in the ISE processes pane
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- In the "General Options" tab, select **-g reset\_on\_error**
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- In the **General Options** tab, tick **-g reset\_on\_error**
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- In the **Configuration Options** tab:
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- Tick "Place MultiBoot Settings into Bitstream"
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- Tick **Place MultiBoot Settings into Bitstream**
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- Set **-g next\_config\_reboot** to **Enable**
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- Set **-g next\_config\_addr** to the MultiBoot bitstream address
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- Tick **-g next\_config\_new\_mode**
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... | ... | @@ -188,34 +205,12 @@ of two ways: |
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- If running from the ISE GUI:
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- Right-click **Generate Programming File** in the ISE processes
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pane
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- In the **General Options** tab, select **-g reset\_on\_error**
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- In the **General Options** tab, tick **-g reset\_on\_error**
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- Click **OK**
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-----
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## Design specification
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Some features of the **xil\_multiboot** module are:
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- provides an interface (via [FAR](xil-multiboot#far) register) to
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write FPGA bitstream data to an attached flash memory chip
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- registers (see [register map](xil-multiboot#register-map))
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accessible from software are used to control operation of the
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module:
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- writing the bitstream data to the flash chip
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- issuing reprogramming command to the FPGA
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- reading boot status register from FPGA configuration logic
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- uses the Xilinx ICAP primitive to issue reprogramming of the FPGA
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(IPROG command [\[1\]](/xil-multiboot#References))
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- the FPGA then reconfigures itself from the attached flash
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- implements an FSM to control writing to the flash chip and send the
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IPROG command to the FPGA
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- modular, easily modifiable design
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- flash chip is controlled by software, so virtually any SPI flash
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chip is supported
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- Wishbone interface can easily be replaced by some other
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interconnect (e.g., AXI) by implementing the **multiboot\_regs**
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module
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## Architecture
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A block diagram of the **xil\_multiboot** module is shown below. It
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consists of the following blocks:
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