CarrIer for RFoWR-based Timing sYstems (CITY)
Project description
This card can be used to distribute RF signals over a White Rabbit network.
This board has been developed in order to be used for the ESRF accelerators timing system:
- Bunch injection/extraction, Storage Ring filling
- Beam synchronous triggers for accelerators diagnostic and beamlines experiments
CITY is based on two main design:
It is a standalone module enclosed in a 19"1U rack.
Main features
- XC7Z030 controller, SoC with Kintex-7 logic (called PL, i.e. Programmable Logic) and Dual ARM Cortex-A9 MPCore at 1 GHz (called PS, i.e. Processing System)
- 2x Low-Pin Count FMC slots
- FMC1 connectivity: Vadj fixed to 2.5V, 34 differential pairs, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
- FMC2 connectivity: Vadj fixed to 1.8V, 34 differential pairs, JTAG, I2C
- FPGA configuration
- From QSPI flash, Ethernet (through U-Boot bootloader) or MicroSD card
- Clocking resources:
- SoC:
- 1x 33.33 MHz fixed oscillator, SoC main clock (clock distribution to PL possible)
- WR domain:
- 1x 25 MHz TCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x 20 MHz VCXO controlled by a DAC with SPI interface (AD5662, used by White Rabbit PTP core)
- 1x AD9516 frequency synthesizer/fanout: 125MHz WR for WR-PTP core & 500MHz for RFoWR
- RF domain:
- 1x ~10-800MHz Programmable VCXO (Si571, custom part: 352MHz center frequency)
- 1x AD9510 frequency synthesizer/fanout
- SoC:
- On-board memories
- 2x 512 MByte (4 Gbit) DDR3L (MT41K256M16HA-125:E)
- 2x 128 Mbit QSPI flash for FPGA bitstream and Linux kernel & root file system storage (S25FL128SAGMFIR01)
- Miscellaneous
- UCD90120ARGC power controller (programmable over JTAG) to survey power rails and manage power-on and power-off sequence
- Xilinx-style JTAG connector
- Front panel
- 1x SMA for RF input (mode master)
- 1x SMA for RF output (synthesized, slave mode)
- 1x SMA for user clock output (DDS|[WR|RF]/N clock multiplexed)
- 4x LEMO-00 digital input (optional 50 Ohm termination, configurable input voltage threshold)
- 12x LEMO-00 digital outputs (6 of them have fine delay tuning @10ps steps)
- 1x programmable LED (module status)
- 2x LED for WR & RF valid status
- Back panel
- 1x LEMO connector for WR PPS output
- 1x BNC connector for WR 10MHz output
- 1x RJ45 port for 10/100/1000 Mbps Ethernet
- 1x Micro-USB connector (FT232) for UART console
- 1x Push button for POR Reset
- 1x SFP port for WR link
- 1x SFP port for GTX user port
- 10-layer PCB
Prototypes test
February 2020: the board prototypes have been tested and debugged. Issues encountered have been created in Issues category of this repository. Main features tested:
- Power supplies
- Zynq PS (baremetal, Linux)
- Boot peripheral (QSPI, MicroSD, JTAG)
- Main buses (I2C, SPI)
- Reset buttons
- WR link and synchronization
- RFoWR synchronization in both Master & Slave modes with a 352MHz reference input frequency.
- Outputs stages (TTL basic and fine-delayed, RF reconstructed, PPS, 10MHz...)
Releases
PCB project
- V2: CITY-V2-0.tar.gz
Enclosure mechanics
To be added.
Gateware
See in this repository. Not yet available.
Project information
- Users
- Frequently Asked Questions
- Licenced under CERN OHL V1.2
Contacts
Commercial producers
- not commercially available yet
General questions about project
- Antonin Broquet - ESRF
Status
Date | Event |
---|---|
10-09-2019 | Launch manufacturing of 2 board prototypes. |
12-09-2019 | ohwr pages started. |
17-03-2020 | CITY prototypes tested and debugged. V2 ready. |
15-10-2020 | 4 boards CITY V2 received. |
08-04-2021 | CITY V2 minor fix applied and released. Manufacturing files setup on going (assembly, configuration and tests procedures, mechanics, PCB, cabling schema, etc...). Prepare small batch (10 units) order. |
17 March 2020