Zynq carrier for RFoWR based application (CITY)
Project description
This board, based on the FASEC Zynq SoC design , is intended to be used for application requiring signals synchronized to an RF master source distribution over a White Rabbit network. It mainly provides:
- WR connectivity
- RFoWR: based on FMC DAC 12b 1cha DDS
- 12 TTL outputs (6 of them have fine delay unit and RF resynchronization)
- 4 TTL inputs
- 2 FMC slots
Below is only a template. Please update using the recommended setup and usage guide
Main Features
- 4-lane PCIe (Gennum GN4124) obsolete component, not available anymore
- 1x Xilinx Spartan6 FPGA (XC6SLX45T-3FGG484C) (PCI Device ID: 0x18D)
- special versions with XC6SLX100T and XC6SLX150T available
- FMC slot with low pin count (LPC) connector
- Vadj fixed to 2.5V
- FMC connectivity: all 34 differential pairs connected, 1 GTP transceiver with clock, 2 clock pairs, JTAG, I2C
- No dedicated clock signals from Carrier to FMC (only available on HPC pins)
- Stand-alone features
- External 12V power supply connector
- mini USB connector
- 4 LEDs
- 2 buttons
- Power consumption: 5-12 Watt, depending on application
- Optimised for cost
- 6-layer PCB
- Optional cooling fan for the mezzanine.
Project information
- Official production documentation: EDMS EDA-02189
- Users
- Software
- Frequently Asked Questions
- Licenced under CERN OHL V1.2
Contacts
Commercial producers
- not commercially available yet
General questions about project
- Antonin Broquet - ESRF
Status
Date | Event |
---|---|
12-09-2019 | Start working on project. Collecting main specifications. |
12-09-2019 | ohwr pages started. |
12 September 2019