... | @@ -214,8 +214,8 @@ designs. |
... | @@ -214,8 +214,8 @@ designs. |
|
#### Q: An ASIC design is licensed under CERN-OHL-S or CERN-OHL-L. What are the implications regarding proprietary primitives and macros used in the design?
|
|
#### Q: An ASIC design is licensed under CERN-OHL-S or CERN-OHL-L. What are the implications regarding proprietary primitives and macros used in the design?
|
|
|
|
|
|
Because of the way primitive libraries (e.g. the so-called
|
|
Because of the way primitive libraries (e.g. the so-called
|
|
[PDKs](https://en.wikipedia.org/wikis/Process_design_kit) and [standard
|
|
[PDKs](https://en.wikipedia.org/wiki/Process_design_kit) and [standard
|
|
cell](https://en.wikipedia.org/wikis/Standard_cell) libraries) are
|
|
cell](https://en.wikipedia.org/wiki/Standard_cell) libraries) are
|
|
distributed in the ASIC design world, things are actually quite
|
|
distributed in the ASIC design world, things are actually quite
|
|
different from the FPGA case. Wording in CERN-OHL-S does not exclude
|
|
different from the FPGA case. Wording in CERN-OHL-S does not exclude
|
|
these primitive libraries from the distribution obligations. Not
|
|
these primitive libraries from the distribution obligations. Not
|
... | | ... | |