03-09-2012: Reception of the First Batch ☜
added by Evangelia Gousiou on 2012-09-03 17:10:42.772118
We have just received, according to schedule, 4992 A3P400-PQG208X6 (X6 = single lot date code) devices from the same wafer lot!
30-07-2012: Microsemi First Articles validated ✓
added by Evangelia Gousiou on 2012-07-30 15:04:24.078681
For the validation, we have:
1) Run nanoFIP JTAG VERIFY cycles: one of the boards was acting as the target TAP, and another was receiving JTAG frames corresponding to the VERIFY_6A11.svf firmware.
The cycles were completed successfully! Also for confirmation a different VERIFY firmware was sent and the JTAG cycles failed.
2) Kept the boards (each one with a different configuration in terms of speed, var size, model/constructor etc) running in loopback mode for 3 days, with the heaters at 100% (temperature measured on surface by the sensor: 40oC). No error occurred!
_* Note: The following NFTC boads are housing the First Article
31.25 KHz: 201104-010
1.00 MHz: 201104-007, 201104-016, 201104-019
2.50 MHz: 201104-011_
23-07-2012: Microsemi First Articles arrived ☜
added by Evangelia Gousiou on 2012-07-26 16:38:48.012150
We just received from Microsemi 5 first In House Programmed ProASIC3
FPGAs (according to the Microsemi/ Actel First Article
They are being soldered on 5 NFTC testing boards , they will be tested in our lab and then the green light for the IHP of 5'000 devices will be given.
12-06-2012: ProASIC3 components purchase $-)
added by Evangelia Gousiou on 2012-07-26 16:26:21.856806
2 x (5'000 A3P400-PQG208 devices from the same wafer lot) have been purchased!
The first batch of 5'000 devices is expected at the end of September
The second batch of 5'000 devices, all programmed as nanoFIPs (ohwr.org v254 checksum 6A11) and engraved with the nanoFIP logo, are expected at the end of November 2012.
30-01-2012: Radiation test results: Successful ✓
added by Evangelia Gousiou on 2012-07-26 16:19:14.195045
16-12-2011: Large scale nanoFIP radiation tests
added by Evangelia Gousiou on 2011-12-21 17:14:34.550890
Follow us on twitter ~:<
14-11-2011: Second nanoFIP code review ongoing
added by Evangelia Gousiou on 2011-11-15 13:52:19.460841
Four designer-experts are looking into the nanoFIp code.
The review started on Monday Nov 14th at 11h00 and will be completed on Thursday 17th at 12h00.
Review folder here.
31-10-2011: nanoFIP-FielDrive-FieldTR EMC tests
added by Evangelia Gousiou on 2011-11-15 13:49:40.605985
Tests for the compliance of the nanoFIP-FielDrive-FieldTR with the EMC
norm IEC 61000 4-4.
Test Report available here.
24-08-2011: nanoFIP exceeds 10K JTAG cycles over summer ☼
added by Evangelia Gousiou on 2011-08-24 11:33:08.325232
10 nanoFIP chips were left running continuously the last 3 weeks programming and verifying Actel ProASIC3 A3P250 FPGAs through JTAG.
- Each one of the 2 nanoFIPs running at 2.5 Mbps has completed successfully more than 10000 programming/ verification cycles.
- Each one of the 7 nanoFIPs running at 1 Mbps has completed successfully more than 2000 programming/ verification cycles.
- Finally, 1 nanoFIP running at 31.25 Kbps has completed successfully around 1000 programming/ verification cycles.
08-07-2011: nanoFIP reprograms Xilinx & Actel FPGAs
added by Evangelia Gousiou on 2011-07-08 17:20:59.779769
We are moving towards the completion of the nanoFIP JTAG controller
nanoFIP is now able to receive WorldFIP frames that are translated into JTAG instructions for the reprogramming of other FPGAs.
For the moment we have tested the implementations with Actel ProASIC3 and Xilinx Virtex5 FPGAs.
17-06-2011: Start-up of JTAG developments
added by Evangelia Gousiou on 2011-06-17 14:31:57.754515
In collaboration with Stephen Page (TE-EPC) we are working on the JTAG extension of the nanoFIP chip! This extension will give to the user the possibility of reprogramming another FPGA through WorldFIP.
20-05-2011: nanoFIP wiki pages revamped
added by Evangelia Gousiou on 2011-05-20 17:59:19.989687
We have updated our wiki pages! We hope you will have an easier
please report any inconvenience or broken link!
09-05-2011: 6th WorldFIP insourcing meeting
added by Evangelia Gousiou on 2011-05-13 11:25:29.112155
Presentation of nanoFIP's progress
followed by a discussion with the users.
20-04-2011: 19 nanoFIP agents running continuously..>>
added by Evangelia Gousiou on 2011-05-11 18:34:57.191773
19 NFTC boards have been received and are all running continuously in our lab!
17-04-2011: /!\ Two nanoFIPs and a FIELDRIVE at PSI /!\
added by Evangelia Gousiou on 2011-05-11 18:30:39.220533
01-04-2011: Preparations for the radiation tests at PSI
added by Evangelia Gousiou on 2011-03-31 18:55:39.526099
Preparations for nanoFIP's radiation tests!
We have decided to do the tests in two parts. A first test of 1-2 boards will take place at 15-17 April and 8-9 more boards are planned for the end of May.
Test plan under construction.
11-03-2011: Playing with the tools!
added by Evangelia Gousiou on 2011-03-11 15:30:02.890064
We are currently working on the synthesis and PnR of nanoFIP, checking on both Synplify and Precision Rad-Tol.
28-01-2011: VHDL code review held
added by Erik van der Bij on 2011-01-28 10:27:26.724240
Five CERN engineers have spent in total over nine days of work to review the VHDL code of the NanoFIP design. The total code of the design amounts to 10750 lines (including extensive comments and empty lines) in thirty files. During the review suggestions were made that make the design more robust to possible glitches on the cable and that make it less prone to block under extreme cases that may occur because of radiation or use that is outside of the specifications. The implementation of the suggested improvements will result in a more robust design that is now understood by several engineers. It has to be noted that the design already has been used in working hardware and that extensive simulations have been made. Regression tests will be made after the code changes triggered by the review.
18-01-2011: more than 24 million cycles!
added by Evangelia Gousiou on 2011-01-06 11:08:36.048466
From Tuesday 21 Dec 2010 until Wednesday 5th Jan 2011, nanoFIP has been running without a single error!
20-12-2010: nanoFIP & XMAS *<]:-})
added by Evangelia Gousiou on 2010-12-20 17:34:46.502531
During Christmas nanoFIP will be running:
- in loopback memory mode
- with var size 124 bytes
- with macrocycle 100 ms
- with cable length >1 klm.
All the equipment is under UPS to avoid problems from small power cuts.
Since last Friday and until Tuesday we are having the dry run of the test (before the big break) and everything is working as expected!
added by Evangelia Gousiou on 2010-12-20 17:26:58.546174
Using the DAT_I and DAT_O pins of the test board and with nanoFIP in
stand-alone mode, we have managed to create a nanoFIPDIAG running with
the standard software.
After more than 3 complete days in the same segment with a cryo crate, we have seen no errors!
26-11-2010: 5th WorldFIP insourcing meeting
added by Evangelia Gousiou on 2010-12-02 15:04:54.673666
Presentation of nanoFIP's progress followed by a
discussion with the users.
19-10-2010: nanoFIP chip working
added by Erik van der Bij on 2010-10-19 08:43:03.357336
The design of the nanoFIP chip is working. Tests are progressing very smoothly thanks to the extensive simulation models written by G. Penacoba. The actual hardware is tested on the NanoFIP test board that talks to other equipment in CERN's WorldFIP laboratory that is run by J. Palluel. While the VHDL code is being optimised the tests are on-going. Soon a VHDL code review will be held.
17-06-2010: Simulation work started
added by Erik van der Bij on 2010-06-17 11:40:40.705452
Simulation work (WP6) has started to debug the NanoFIP design. The testbench is written by an independent person from the author of the CernFIP code. Already some flaws were found in CRC calculations and some issues that are not clear in the manual were spotted.
14-04-2010: Package type of nanoFIP defined
added by Erik van der Bij on 2010-04-14 16:42:53.355730
The package type of the nanoFIP has been defined and will be a PQFP with 208 pins. This 28x28mm2 large package with a 0.5mm pitch between pins is easy to assemble and repair. The pinout has been designed for ease of routing too (e.g. Wishbone bus on one side, FielDrive signals together).
added by Anonymous on 2009-03-09 10:36:07.186002
Minutes of kick-off meeting
added by Anonymous on 2009-04-09 10:35:33.719671
Minutes of 2nd meeting
added by Anonymous on 2009-06-11 10:34:41.496023
Minutes of 3rd meeting
Meeting with PH-ESE
added by Anonymous on 2009-11-27 10:33:32.812111
Meeting with PH-ESE Microelectronics on possibility to re-spin original !MicroFIP design
4th WorldFIP insourcing meeting
added by Anonymous on 2009-12-11 10:32:57.906877
4th WorldFIP insourcing meeting
Presentation Chamonix 2010
added by Anonymous on 2010-01-27 10:32:24.396428
Presentation Is the WorldFIP a reliable Rad-hard Fieldbus on long term? at the "LHC Performance Workshop - Chamonix 2010"