| ... | ... | @@ -8,9 +8,64 @@ replacement is called *nanoFIP*. |
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## Detailed project information
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The project is organized in work packages. The work packages are:
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The project is organized in work packages. The work packages along with
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their status are described in the following table:
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<table>
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<tbody>
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<tr class="odd">
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<td>Work Package</td>
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<td>Description</td>
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<td>Status</td>
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</tr>
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<tr class="even">
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<td>WP1</td>
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<td>[Alstom MicroFIP preliminary VHDL code interpretation](https://www.ohwr.org/project/cern-fip/wikis/WP1)</td>
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<td>Done</td>
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</tr>
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<tr class="odd">
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<td>WP2</td>
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<td>[Write project management doc for insourcing of MicroFIP](https://www.ohwr.org/project/cern-fip/wikis/WP2)</td>
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<td>Done</td>
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</tr>
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<tr class="even">
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<td>WP3</td>
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<td>[Write functional specification of MicroFIP replacement](https://www.ohwr.org/project/cern-fip/wikis/WP3)</td>
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<td>Done</td>
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</tr>
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<tr class="odd">
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<td>WP4</td>
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<td>[Rewrite and extend Alstom MicroFIP VHDL code](https://www.ohwr.org/project/cern-fip/wikis/WP4)</td>
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<td>Cancelled</td>
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</tr>
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<tr class="even">
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<td>WP5</td>
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<td>[Write project management doc for insourcing of MicroFIP](https://www.ohwr.org/project/cern-fip/wikis/WP5)</td>
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<td>Done</td>
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</tr>
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<tr class="odd">
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<td>WP6</td>
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<td>[VHDL Testbench creation and simulation of nanoFIP](https://www.ohwr.org/project/cern-fip/wikis/WP6)</td>
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<td>Done</td>
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</tr>
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<tr class="even">
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<td>WP7</td>
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<td>[Stand-alone mode test board design and test](https://www.ohwr.org/project/cern-fip/wikis/WP7)</td>
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<td>Combined with WP8</td>
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</tr>
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<tr class="odd">
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<td>WP8</td>
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<td>[Design board for functional and radiation test](https://www.ohwr.org/project/cern-fip/wikis/WP8)</td>
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<td>Done</td>
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</tr>
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<tr class="even">
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<td>WP9</td>
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<td>[Radiation tests](https://www.ohwr.org/project/cern-fip/wikis/WP9)</td>
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<td>In Progress</td>
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</tr>
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</tbody>
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</table>
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- WP1. Alstom MicroFIP preliminary VHDL code interpretation
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- WP2. Write project management doc for insourcing of MicroFIP
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- WP3. Write functional specification of MicroFIP replacement
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- WP4. Rewrite and extend Alstom MicroFIP VHDL code - *WP1 concluded
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| ... | ... | @@ -18,8 +73,6 @@ The project is organized in work packages. The work packages are: |
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- WP5. Write new NanoFIP VHDL code
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- WP6. VHDL Testbench creation and simulation of NanoFIP
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- WP7. Stand-alone mode test board design and test
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- WP8. Design board for functional and radiation test
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- WP9. Radiation tests
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Note that for the development of the FPGA replacement that either WP4
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*or* WP5 will be needed. The decision between the adaptation of existing
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