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@@ -8,9 +8,64 @@ replacement is called *nanoFIP*.
 
 ## Detailed project information
 
-The project is organized in work packages. The work packages are:
+The project is organized in work packages. The work packages along with
+their status are described in the following table:
+
+<table>
+<tbody>
+<tr class="odd">
+<td>Work Package</td>
+<td>Description</td>
+<td>Status</td>
+</tr>
+<tr class="even">
+<td>WP1</td>
+<td>[Alstom MicroFIP preliminary VHDL code interpretation](https://www.ohwr.org/project/cern-fip/wikis/WP1)</td>
+<td>Done</td>
+</tr>
+<tr class="odd">
+<td>WP2</td>
+<td>[Write project management doc for insourcing of MicroFIP](https://www.ohwr.org/project/cern-fip/wikis/WP2)</td>
+<td>Done</td>
+</tr>
+<tr class="even">
+<td>WP3</td>
+<td>[Write functional specification of MicroFIP replacement](https://www.ohwr.org/project/cern-fip/wikis/WP3)</td>
+<td>Done</td>
+</tr>
+<tr class="odd">
+<td>WP4</td>
+<td>[Rewrite and extend Alstom MicroFIP VHDL code](https://www.ohwr.org/project/cern-fip/wikis/WP4)</td>
+<td>Cancelled</td>
+</tr>
+<tr class="even">
+<td>WP5</td>
+<td>[Write project management doc for insourcing of MicroFIP](https://www.ohwr.org/project/cern-fip/wikis/WP5)</td>
+<td>Done</td>
+</tr>
+<tr class="odd">
+<td>WP6</td>
+<td>[VHDL Testbench creation and simulation of nanoFIP](https://www.ohwr.org/project/cern-fip/wikis/WP6)</td>
+<td>Done</td>
+</tr>
+<tr class="even">
+<td>WP7</td>
+<td>[Stand-alone mode test board design and test](https://www.ohwr.org/project/cern-fip/wikis/WP7)</td>
+<td>Combined with WP8</td>
+</tr>
+<tr class="odd">
+<td>WP8</td>
+<td>[Design board for functional and radiation test](https://www.ohwr.org/project/cern-fip/wikis/WP8)</td>
+<td>Done</td>
+</tr>
+<tr class="even">
+<td>WP9</td>
+<td>[Radiation tests](https://www.ohwr.org/project/cern-fip/wikis/WP9)</td>
+<td>In Progress</td>
+</tr>
+</tbody>
+</table>
 
-  - WP1. Alstom MicroFIP preliminary VHDL code interpretation
   - WP2. Write project management doc for insourcing of MicroFIP
   - WP3. Write functional specification of MicroFIP replacement
   - WP4. Rewrite and extend Alstom MicroFIP VHDL code - *WP1 concluded
@@ -18,8 +73,6 @@ The project is organized in work packages. The work packages are:
   - WP5. Write new NanoFIP VHDL code
   - WP6. VHDL Testbench creation and simulation of NanoFIP
   - WP7. Stand-alone mode test board design and test
-  - WP8. Design board for functional and radiation test
-  - WP9. Radiation tests
 
 Note that for the development of the FPGA replacement that either WP4
 *or* WP5 will be needed. The decision between the adaptation of existing