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@@ -32,8 +32,6 @@ developed.
 
 ### [WP1. Alstom MicroFIP preliminary VHDL code interpretation](WP1) - Done
 
-[WP1 wiki page](WP1)
-
   - Verify code with Modelsim, Synplicity Synplify, Mentor Precision and
     Actel (without simulation)
   - Deliverables
@@ -49,8 +47,6 @@ manweeks
 
 ### [WP2. Write project management doc for insourcing of MicroFIP](WP2) - Done
 
-[WP2 wiki page](WP2)
-
   - Deliverable
       - Document describing
           - Reference documentation
@@ -66,8 +62,6 @@ manweeks
 
 ### [WP3. Write functional specification of MicroFIP replacement](WP3) - Done
 
-[WP3 wiki page](WP3)
-
   - Collect detailed information on how the current MicroFIP is used in
     CERN’s applications and which operation modes are not used.
   - Deliverable
@@ -101,8 +95,6 @@ manweeks
 
 ### [WP5. Write new NanoFIP VHDL code](WP5) - In progress
 
-[WP5 wiki page](WP5)
-
   - Write technical specifications - based on the functional
     specification written as part of WP3
   - Write new compatible MicroFIP VHDL with zero use of Alstom code
@@ -123,8 +115,6 @@ done**
 
 ### [WP6. VHDL Testbench creation and simulation of NanoFIP](WP6) - In progress
 
-[WP6 wiki page](WP6)
-
   - Write VHDL testbenches that allow to test the MicroFIP
       - FielDrive emulator (needed for MicroFIP stand-alone mode)
       - Processor bus emulator (needed for MicroFIP in microcontrolled