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### [WP1. Alstom MicroFIP preliminary VHDL code interpretation](WP1) - Done
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[WP1 wiki page](WP1)
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- Verify code with Modelsim, Synplicity Synplify, Mentor Precision and
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Actel (without simulation)
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- Deliverables
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### [WP2. Write project management doc for insourcing of MicroFIP](WP2) - Done
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[WP2 wiki page](WP2)
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- Deliverable
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- Document describing
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- Reference documentation
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### [WP3. Write functional specification of MicroFIP replacement](WP3) - Done
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[WP3 wiki page](WP3)
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- Collect detailed information on how the current MicroFIP is used in
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CERN’s applications and which operation modes are not used.
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- Deliverable
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| ... | ... | @@ -101,8 +95,6 @@ manweeks |
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### [WP5. Write new NanoFIP VHDL code](WP5) - In progress
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[WP5 wiki page](WP5)
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- Write technical specifications - based on the functional
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specification written as part of WP3
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- Write new compatible MicroFIP VHDL with zero use of Alstom code
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| ... | ... | @@ -123,8 +115,6 @@ done** |
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### [WP6. VHDL Testbench creation and simulation of NanoFIP](WP6) - In progress
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[WP6 wiki page](WP6)
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- Write VHDL testbenches that allow to test the MicroFIP
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- FielDrive emulator (needed for MicroFIP stand-alone mode)
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- Processor bus emulator (needed for MicroFIP in microcontrolled
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