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@@ -36,12 +36,12 @@ package along with its status is described in the following table:
 <tr class="odd">
 <td>WP4</td>
 <td>[Rewrite and extend Alstom MicroFIP VHDL code](https://www.ohwr.org/project/cern-fip/wikis/WP4)</td>
-<td>Cancelled <em><span class="*"></span></em></td>
+<td>Cancelled <em><span style="text-align:left;">*&gt;</span></em></td>
 </tr>
 <tr class="even">
 <td>WP5</td>
 <td>[Write new nanoFIP VHDL code](https://www.ohwr.org/project/cern-fip/wikis/WP5)</td>
-<td>Done <em><span class="*"></span></em></td>
+<td>Done <em><span style="text-align:left;">*&gt;</span></em></td>
 </tr>
 <tr class="odd">
 <td>WP6</td>
@@ -66,8 +66,8 @@ package along with its status is described in the following table:
 </tbody>
 </table>
 
-\_For the development of the FPGA replacement either WP4 or WP5 will be
-needed.  
+\_\<\*\>For the development of the FPGA replacement either WP4 or WP5
+will be needed.  
 The decision between the **adaptation of existing VHDL code** (WP4) or  
 the **development of completely new code** (WP5) will be made based on
 the results of WP1, WP2 and WP3.\_