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...@@ -6,78 +6,20 @@ FPGA-based replacement for the MicroFIP chip, a WorldFIP agent. ...@@ -6,78 +6,20 @@ FPGA-based replacement for the MicroFIP chip, a WorldFIP agent.
This FPGA replacement is called This FPGA replacement is called
https://www.ohwr.org/600 https://www.ohwr.org/600
The nanoFIP is an Actel FPGA component implementing the \- \> nanoFIP is an **Actel FPGA** component implementing the
[WorldFIP](WorldFIP) protocol that can be used in field devices. [WorldFIP](WorldFIP) protocol that can be used in field devices.
The component is developed as part of the [WorldFIP insourcing \- \> It is designed to be **radiation tolerant** by using different
project](https://www.ohwr.org/project/cern-fip) and is designed to be single event upset mitigation techniques such as
radiation tolerant Triple Module Redundancy and fail-safe state machines. To improve the
by using different single event upset mitigation techniques such as radiation tolerance, the nanoFIP implements
triple module redundancy. To improve the radiation tolerance, a minimal **subset of the WorldFIP services**.
the nanoFIP implements a minimal subset of the WorldFIP services.
WorldFIP variables are transferred either directly on 16-bit I/O ports
or via a triplicated memory included in the nanoFIP component.
The device is used in conjunction with a [FielDrive](FielDrive) driver
chip and [FieldTR](FieldTR) insulating transformer, both available from
the company ALSTOM.
----- \- \> The device is used in conjunction with a [FielDrive](FielDrive)
driver chip and [FieldTR](FieldTR) insulating transformer,
both available from the company ALSTOM.
The project has been organized in work packages. The description of each -----
package along with its status is described in the following table:
<table> The project has been organized in [work packages](WorkPackages).
<tbody>
<tr class="odd">
<td><strong>Work Package</strong></td>
<td><strong>Description</strong></td>
<td><strong>Status</strong></td>
</tr>
<tr class="even">
<td>WP1</td>
<td>[Alstom MicroFIP preliminary VHDL code interpretation](https://www.ohwr.org/project/cern-fip/wikis/WP1)</td>
<td>Done</td>
</tr>
<tr class="odd">
<td>WP2</td>
<td>[Write project management doc for insourcing of MicroFIP](https://www.ohwr.org/project/cern-fip/wikis/WP2)</td>
<td>Done</td>
</tr>
<tr class="even">
<td>WP3</td>
<td>[Write functional specification of MicroFIP replacement](https://www.ohwr.org/project/cern-fip/wikis/WP3)</td>
<td>Done</td>
</tr>
<tr class="odd">
<td>WP4</td>
<td>[Rewrite and extend Alstom MicroFIP VHDL code](https://www.ohwr.org/project/cern-fip/wikis/WP4)</td>
<td>Cancelled</td>
</tr>
<tr class="even">
<td>WP5</td>
<td>[Write new nanoFIP VHDL code](https://www.ohwr.org/project/cern-fip/wikis/WP5)</td>
<td>Done</td>
</tr>
<tr class="odd">
<td>WP6</td>
<td>[VHDL Testbench creation and simulation of nanoFIP](https://www.ohwr.org/project/cern-fip/wikis/WP6)</td>
<td>Done</td>
</tr>
<tr class="even">
<td>WP7</td>
<td>[Stand-alone mode test board design and test](https://www.ohwr.org/project/cern-fip/wikis/WP7)</td>
<td>Combined with WP8</td>
</tr>
<tr class="odd">
<td>WP8</td>
<td>[Design board for functional and radiation test](https://www.ohwr.org/project/cern-fip/wikis/WP8)</td>
<td>Done</td>
</tr>
<tr class="even">
<td>WP9</td>
<td>[Radiation tests](https://www.ohwr.org/project/cern-fip/wikis/WP9)</td>
<td>In Progress</td>
</tr>
</tbody>
</table>