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Beam Positoning Monitor - Gateware
Commit c9217ac1 authored by Lucas Russo's avatar Lucas Russo
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*~
*.swp
*.orig
.gitmodules 0 → 100644
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[submodule "hdl/ip_cores/general-cores"]
path = hdl/ip_cores/general-cores
url = git://ohwr.org/hdl-core-lib/general-cores.git
README 0 → 100644
View file @ c9217ac1
Repository containing the Beam Position Monitor FPGA firmware and
software.
==========================================================
hdl/Manifest.py 0 → 100644
View file @ c9217ac1
modules = { "local": [
"modules/custom_wishbone",
"modules/custom_common",
"ip_cores/general-cores",
"platform/virtex6/chipscope"] };
hdl/README 0 → 100644
View file @ c9217ac1
Folder containing all the BPM FPGA firmware and related tests
==========================================================
general-cores @ 065d6958
Subproject commit 065d69583659890a1180a024e937bc66f7340d72
hdl/modules/custom_common/Manifest.py 0 → 100644
View file @ c9217ac1
modules = { "local" : ["reset_synch"] };
files = [ "custom_common_pkg.vhd" ];
hdl/modules/custom_common/custom_common_pkg.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
package custom_common_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component reset_synch
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end component;
end custom_common_pkg;
hdl/modules/custom_common/reset_synch/reset_synch.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity reset_synch is
port
(
clk_i : in std_logic;
arst_n_i : in std_logic;
rst_n_o : out std_logic
);
end reset_synch;
architecture rtl of reset_synch is
signal s_ff : std_logic;
begin
process(clk_i, arst_n_i)
begin
if arst_n_i = '0' then
s_ff <= '0';
rst_n_o <= '0';
elsif rising_edge(clk_i) then
s_ff <= '1';
rst_n_o <= s_ff;
end if;
end process;
end rtl;
hdl/modules/custom_wishbone/Manifest.py 0 → 100644
View file @ c9217ac1
modules = { "local" : [
# "wb_irq_mngr",
# "wb_dma_interface" ,
"wb_stream",
"wb_fmc150"
] };
files = [ "custom_wishbone_pkg.vhd" ];
hdl/modules/custom_wishbone/custom_wishbone_pkg.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.wishbone_pkg.all;
package custom_wishbone_pkg is
--------------------------------------------------------------------
-- Records
--------------------------------------------------------------------
type t_wishbone_dflow_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wishbone_address;
sel : t_wishbone_byte_select;
cti : t_wishbone_cycle_type;
bte : t_wishbone_burst_type;
we : std_logic;
dat : t_wishbone_data;
end record t_wishbone_dflow_master_out;
subtype t_wishbone_dflow_slave_in is t_wishbone_dflow_master_out;
type t_wishbone_dflow_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
int : std_logic;
dat : t_wishbone_data;
end record t_wishbone_dflow_slave_out;
subtype t_wishbone_dflow_master_in is t_wishbone_dflow_slave_out;
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component wb_dma_interface
generic(
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end component;
component xwb_dma_interface
generic(
-- Three 32-bit data input. LSB bits are valid.
--C_NBITS_VALID_INPUT : natural := 128;
--C_NBITS_DATA_INPUT : natural := 128;
--C_OVF_COUNTER_SIZE : natural := 10
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end component;
component dma_status_reg_synch
generic
(
C_NUM_REG : integer := 10;
C_SLV_DWIDTH : integer := 32;
C_STATUS_REG_IDX : natural := 1
);
port
(
bus_clk_i : in std_logic;
bus_rst_n_i : in std_logic;
bus_reg_read_sel_i : in std_logic_vector(C_NUM_REG-1 downto 0);
bus_reg_write_sel_i : in std_logic_vector(C_NUM_REG-1 downto 0);
bus_2_ip_data_i : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
dma_complete_i : in std_logic;
dma_ovf_i : in std_logic;
dma_complete_synch_o : out std_logic;
dma_ovf_synch_o : out std_logic
);
end component;
end custom_wishbone_pkg;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/Manifest.py 0 → 100644
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files = [ "wb_dma_interface.vhd",
"xwb_dma_interface.vhd",
# "wb_dma_iface_ctl/xdma_ctl_regs_pkg.vhd",
# "wb_dma_iface_ctl/xdma_ctl_iface.vhd"
];
hdl/modules/custom_wishbone/wb_dma_interface_FIX/dma_status_reg_synch.vhd 0 → 100755
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------------------------------------------------------------------------------
-- dma_status_reg_synch.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.dma_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity dma_status_reg_synch is
generic
(
C_NUM_REG : integer := 10;
C_SLV_DWIDTH : integer := 32;
C_STATUS_REG_IDX : natural := 1
);
port
(
bus_clk_i : in std_logic;
bus_rst_n_i : in std_logic;
bus_reg_read_sel_i : in std_logic_vector(C_NUM_REG-1 downto 0);
bus_reg_write_sel_i : in std_logic_vector(C_NUM_REG-1 downto 0);
bus_2_ip_data_i : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
dma_complete_i : in std_logic;
dma_ovf_i : in std_logic;
dma_complete_synch_o : out std_logic;
dma_ovf_synch_o : out std_logic
);
end entity dma_status_reg_synch;
architecture IMP of dma_status_reg_synch is
-- DMA status synch regs
signal s_dma_complete_d1 : std_logic;
signal s_dma_complete_d2 : std_logic;
signal s_dma_complete_d3 : std_logic;
signal s_dma_complete_status : std_logic;
signal s_dma_ovf_d1 : std_logic;
signal s_dma_ovf_d2 : std_logic;
signal s_dma_ovf_status : std_logic;
-- Glue logic
signal dma_complete_synch_glue : std_logic;
signal dma_ovf_synch_glue : std_logic;
begin
-- Glue logic
dma_complete_synch_o <= dma_complete_synch_glue;
dma_ovf_synch_o <= dma_ovf_synch_glue;
p_dma_status_synch : process(bus_clk_i) is
begin
if rising_edge(bus_clk_i) then
if bus_rst_n_i = '0' then
s_dma_complete_d1 <= '0';
s_dma_complete_d2 <= '0';
s_dma_complete_d3 <= '0';
s_dma_complete_status <= '0';
s_dma_ovf_d1 <= '0';
s_dma_ovf_d2 <= '0';
s_dma_ovf_status <= '0';
else
s_dma_complete_d1 <= dma_complete_i;
s_dma_complete_d2 <= s_dma_complete_d1;
s_dma_complete_d3 <= s_dma_complete_d2;
-- Every dma_complete toggle is recognized as a dma_complete
s_dma_complete_status <= s_dma_complete_d3 xor s_dma_complete_d2;
s_dma_ovf_d1 <= dma_ovf_i;
s_dma_ovf_d2 <= s_dma_ovf_d1;
s_dma_ovf_status <= s_dma_ovf_d2;
end if;
end if;
end process p_dma_status_synch;
-- DMA Status set and clear software accessible regs
-- If a condition is detected, set the bit accordingly.
-- Otherwise, wait for "user" to clear the bit.
-- This is done in order to ensure that the user can detected
-- the condition.
p_dma_status_reg : process(bus_clk_i) is
begin
if rising_edge(bus_clk_i) then
if bus_rst_n_i = '0' then
dma_complete_synch_glue <= '0';
dma_ovf_synch_glue <= '0';
else
if s_dma_complete_status = '1' then
dma_complete_synch_glue <= '1';
elsif bus_reg_write_sel_i = std_logic_vector(to_unsigned(2**(C_NUM_REG-1-C_STATUS_REG_IDX), C_NUM_REG)) and dma_complete_synch_glue = '1' then
dma_complete_synch_glue <= bus_2_ip_data_i(0);
end if;
if s_dma_ovf_status = '1' then
dma_ovf_synch_glue <= '1';
elsif bus_reg_write_sel_i = std_logic_vector(to_unsigned(2**(C_NUM_REG-1-C_STATUS_REG_IDX), C_NUM_REG)) and dma_ovf_synch_glue = '1' then
dma_ovf_synch_glue <= bus_2_ip_data_i(1);
end if;
end if;
end if;
end process p_dma_status_reg;
end IMP;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_dma_interface_FIX/doc/wb_dma_ctl_iface.html 0 → 100644
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<HTML>
<HEAD>
<TITLE>wb_dma_ctl_iface</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
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.tr_even { background: #f0eff0; }
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-->
</STYLE>
</HEAD>
<BODY>
<h1 class="heading">wb_dma_ctl_iface</h1>
<h3>Wishbone DMA Streaming Control Interface</h3>
<p>Simple Wishbone DMA interface for controlling the DMA Streaming peripheral</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Control/Status register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Transaction Counter</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#CTL">Control/Status register</a>
</td>
<td class="td_code">
dma_ctl_iface_ctl
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#TR_CNTR">Transaction Counter</a>
</td>
<td class="td_code">
dma_ctl_iface_tr_cntr
</td>
<td class="td_code">
TR_CNTR
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Control/Status register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_ctl_iface_ctl_start_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_adr_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_ctl_iface_ctl_done_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_ctl_iface_ctl_ovf_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Transaction Counter:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_ctl_iface_tr_cntr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CTL"></a>
<h3><a name="sect_3_1">3.1. Control/Status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_ctl_iface_ctl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
A register defining the Control and Status of the core.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
OVF
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DONE
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
START
</td>
</tr>
</table>
<ul>
<li><b>
START
</b>[<i>read/write</i>]: Start Transaction
<br>write 1: starts the DMA transaction.<br> write 0: no effect
<li><b>
DONE
</b>[<i>read-only</i>]: DMA complete
<br>read 1: the DMA has completed the transaction<br> read 0: DMA transaction still in progress
<li><b>
OVF
</b>[<i>read-only</i>]: DMA overflow
<br>read 1: the DMA overflow detected<br> read 0: No overflow detected
</ul>
<a name="TR_CNTR"></a>
<h3><a name="sect_3_2">3.2. Transaction Counter</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_ctl_iface_tr_cntr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TR_CNTR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
Register holding the word count to be transfered to DMA
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TR_CNTR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TR_CNTR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TR_CNTR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TR_CNTR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TR_CNTR
</b>[<i>read/write</i>]: Transactions Counter
<br>Stores the words to be transfered to DMA
</ul>
</BODY>
</HTML>
hdl/modules/custom_wishbone/wb_dma_interface_FIX/doc/wb_xdma_interface.html 0 → 100644
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<HTML>
<HEAD>
<TITLE>wb_dma_interface_port</TITLE>
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<h1 class="heading">wb_dma_interface_port</h1>
<h3>Wishbone DMA Streaming Interface</h3>
<p>Simple Wishbone DMA interface for peripherals which want to stream data to a DMA</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Control/Status register</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Transaction Counter</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#CTL">Control/Status register</a>
</td>
<td class="td_code">
dma_iface_ctl
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#TR_CNTR">Transaction Counter</a>
</td>
<td class="td_code">
dma_iface_tr_cntr
</td>
<td class="td_code">
TR_CNTR
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
FIFOREG
</td>
<td >
<A href="#FIFO_C2B_R0">FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0</a>
</td>
<td class="td_code">
dma_iface_fifo_c2b_r0
</td>
<td class="td_code">
FIFO_C2B_R0
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
FIFOREG
</td>
<td >
<A href="#FIFO_C2B_R1">FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1</a>
</td>
<td class="td_code">
dma_iface_fifo_c2b_r1
</td>
<td class="td_code">
FIFO_C2B_R1
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#FIFO_C2B_CSR">FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register</a>
</td>
<td class="td_code">
dma_iface_fifo_c2b_csr
</td>
<td class="td_code">
FIFO_C2B_CSR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x5
</td>
<td >
FIFOREG
</td>
<td >
<A href="#FIFO_B2C_R0">FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0</a>
</td>
<td class="td_code">
dma_iface_fifo_b2c_r0
</td>
<td class="td_code">
FIFO_B2C_R0
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x6
</td>
<td >
REG
</td>
<td >
<A href="#FIFO_B2C_CSR">FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register</a>
</td>
<td class="td_code">
dma_iface_fifo_b2c_csr
</td>
<td class="td_code">
FIFO_B2C_CSR
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Control/Status register:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_ctl_start_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[2:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_ctl_done_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_ctl_ovf_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Transaction Counter:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_tr_cntr_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FIFO C2B (Core -> DMA) synchronization:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_c2b_wr_req_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_c2b_wr_full_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_c2b_wr_empty_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_c2b_wr_usedw_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_c2b_data_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_c2b_last_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FIFO B2C (Bus -> Core) synchronization:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_b2c_rd_req_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_b2c_rd_full_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_b2c_rd_empty_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_b2c_rd_usedw_o[7:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
dma_iface_fifo_b2c_data_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="CTL"></a>
<h3><a name="sect_3_1">3.1. Control/Status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_iface_ctl
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CTL
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<p>
A register defining the Control and Status of the core.
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
OVF
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DONE
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
START
</td>
</tr>
</table>
<ul>
<li><b>
START
</b>[<i>read/write</i>]: Start Transaction
<br>write 1: starts the DMA transaction.<br> write 0: no effect
<li><b>
DONE
</b>[<i>read-only</i>]: DMA complete
<br>read 1: the DMA has completed the transaction<br> read 0: DMA transaction still in progress
<li><b>
OVF
</b>[<i>read-only</i>]: DMA overflow
<br>read 1: the DMA overflow detected<br> read 0: No overflow detected
</ul>
<a name="TR_CNTR"></a>
<h3><a name="sect_3_2">3.2. Transaction Counter</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_iface_tr_cntr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
TR_CNTR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<p>
Register holding the word count to be transfered to DMA
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TR_CNTR[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TR_CNTR[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TR_CNTR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
TR_CNTR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
TR_CNTR
</b>[<i>read/write</i>]: Transactions Counter
<br>Stores the words to be transfered to DMA
</ul>
<a name="FIFO_C2B_R0"></a>
<h3><a name="sect_3_3">3.3. FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_iface_fifo_c2b_r0
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FIFO_C2B_R0
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
DATA
</b>[<i>read-only</i>]: Output FIFO data value
<br>Value of data word synchronized to the core clock
</ul>
<a name="FIFO_C2B_R1"></a>
<h3><a name="sect_3_4">3.4. FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_iface_fifo_c2b_r1
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FIFO_C2B_R1
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
LAST
</td>
</tr>
</table>
<ul>
<li><b>
LAST
</b>[<i>read-only</i>]: Transaction Last Data
<br>0: Current entry is not the last transaction data<br> 1: Current entry is the last transaction data
</ul>
<a name="FIFO_C2B_CSR"></a>
<h3><a name="sect_3_5">3.5. FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_iface_fifo_c2b_csr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FIFO_C2B_CSR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EMPTY
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FULL
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
USEDW[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FULL
</b>[<i>read-only</i>]: FIFO full flag
<br>1: FIFO 'FIFO C2B (Core -> DMA) synchronization' is full<br>0: FIFO is not full
<li><b>
EMPTY
</b>[<i>read-only</i>]: FIFO empty flag
<br>1: FIFO 'FIFO C2B (Core -> DMA) synchronization' is empty<br>0: FIFO is not empty
<li><b>
USEDW
</b>[<i>read-only</i>]: FIFO counter
<br>Number of data records currently being stored in FIFO 'FIFO C2B (Core -> DMA) synchronization'
</ul>
<a name="FIFO_B2C_R0"></a>
<h3><a name="sect_3_6">3.6. FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_iface_fifo_b2c_r0
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FIFO_B2C_R0
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x14
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
DATA
</b>[<i>write-only</i>]: Input FIFO data value
<br>Value of data word synchronized to the core clock
</ul>
<a name="FIFO_B2C_CSR"></a>
<h3><a name="sect_3_7">3.7. FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
dma_iface_fifo_b2c_csr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x6
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FIFO_B2C_CSR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x18
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EMPTY
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FULL
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
USEDW[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
FULL
</b>[<i>read-only</i>]: FIFO full flag
<br>1: FIFO 'FIFO B2C (Bus -> Core) synchronization' is full<br>0: FIFO is not full
<li><b>
EMPTY
</b>[<i>read-only</i>]: FIFO empty flag
<br>1: FIFO 'FIFO B2C (Bus -> Core) synchronization' is empty<br>0: FIFO is not empty
<li><b>
USEDW
</b>[<i>read-only</i>]: FIFO counter
<br>Number of data records currently being stored in FIFO 'FIFO B2C (Bus -> Core) synchronization'
</ul>
</BODY>
</HTML>
hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_registers_pkg.vhd 0 → 100644
View file @ c9217ac1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone DMA Streaming Interface
---------------------------------------------------------------------------------------
-- File : xdma_interface_registers_pkg.vhd
-- Author : auto-generated by wbgen2 from xdma_interface_wb.wb
-- Created : Thu Sep 27 15:39:56 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xdma_interface_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
package dma_iface_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_dma_iface_in_registers is record
ctl_done_i : std_logic;
ctl_ovf_i : std_logic;
fifo_c2b_wr_req_i : std_logic;
fifo_c2b_data_i : std_logic_vector(31 downto 0);
fifo_c2b_last_i : std_logic;
fifo_b2c_rd_req_i : std_logic;
end record;
constant c_dma_iface_in_registers_init_value: t_dma_iface_in_registers := (
ctl_done_i => '0',
ctl_ovf_i => '0',
fifo_c2b_wr_req_i => '0',
fifo_c2b_data_i => (others => '0'),
fifo_c2b_last_i => '0',
fifo_b2c_rd_req_i => '0'
);
-- Output registers (WB slave -> user design)
type t_dma_iface_out_registers is record
ctl_start_o : std_logic;
tr_cntr_o : std_logic_vector(31 downto 0);
fifo_c2b_wr_full_o : std_logic;
fifo_c2b_wr_empty_o : std_logic;
fifo_c2b_wr_usedw_o : std_logic_vector(7 downto 0);
fifo_b2c_rd_full_o : std_logic;
fifo_b2c_rd_empty_o : std_logic;
fifo_b2c_rd_usedw_o : std_logic_vector(7 downto 0);
fifo_b2c_data_o : std_logic_vector(31 downto 0);
end record;
constant c_dma_iface_out_registers_init_value: t_dma_iface_out_registers := (
ctl_start_o => '0',
tr_cntr_o => (others => '0'),
fifo_c2b_wr_full_o => '0',
fifo_c2b_wr_empty_o => '0',
fifo_c2b_wr_usedw_o => (others => '0'),
fifo_b2c_rd_full_o => '0',
fifo_b2c_rd_empty_o => '0',
fifo_b2c_rd_usedw_o => (others => '0'),
fifo_b2c_data_o => (others => '0')
);
function "or" (left, right: t_dma_iface_in_registers) return t_dma_iface_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body dma_iface_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_dma_iface_in_registers) return t_dma_iface_in_registers is
variable tmp: t_dma_iface_in_registers;
begin
tmp.ctl_done_i := f_x_to_zero(left.ctl_done_i) or f_x_to_zero(right.ctl_done_i);
tmp.ctl_ovf_i := f_x_to_zero(left.ctl_ovf_i) or f_x_to_zero(right.ctl_ovf_i);
tmp.fifo_c2b_wr_req_i := f_x_to_zero(left.fifo_c2b_wr_req_i) or f_x_to_zero(right.fifo_c2b_wr_req_i);
tmp.fifo_c2b_data_i := f_x_to_zero(left.fifo_c2b_data_i) or f_x_to_zero(right.fifo_c2b_data_i);
tmp.fifo_c2b_last_i := f_x_to_zero(left.fifo_c2b_last_i) or f_x_to_zero(right.fifo_c2b_last_i);
tmp.fifo_b2c_rd_req_i := f_x_to_zero(left.fifo_b2c_rd_req_i) or f_x_to_zero(right.fifo_b2c_rd_req_i);
return tmp;
end function;
end package body;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_regs.h 0 → 100644
View file @ c9217ac1
/*
Register definitions for slave core: Wishbone DMA Streaming Interface
* File : xdma_interface_regs.h
* Author : auto-generated by wbgen2 from xdma_interface_wb.wb
* Created : Thu Sep 27 15:39:56 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xdma_interface_wb.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_XDMA_INTERFACE_WB_WB
#define __WBGEN2_REGDEFS_XDMA_INTERFACE_WB_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Control/Status register */
/* definitions for field: Start Transaction in reg: Control/Status register */
#define DMA_IFACE_CTL_START WBGEN2_GEN_MASK(0, 1)
/* definitions for field: DMA complete in reg: Control/Status register */
#define DMA_IFACE_CTL_DONE WBGEN2_GEN_MASK(1, 1)
/* definitions for field: DMA overflow in reg: Control/Status register */
#define DMA_IFACE_CTL_OVF WBGEN2_GEN_MASK(2, 1)
/* definitions for register: Transaction Counter */
/* definitions for register: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0 */
/* definitions for field: Output FIFO data value in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0 */
#define DMA_IFACE_FIFO_C2B_R0_DATA_MASK WBGEN2_GEN_MASK(0, 32)
#define DMA_IFACE_FIFO_C2B_R0_DATA_SHIFT 0
#define DMA_IFACE_FIFO_C2B_R0_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DMA_IFACE_FIFO_C2B_R0_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1 */
/* definitions for field: Transaction Last Data in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1 */
#define DMA_IFACE_FIFO_C2B_R1_LAST WBGEN2_GEN_MASK(0, 1)
/* definitions for register: FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
#define DMA_IFACE_FIFO_C2B_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
#define DMA_IFACE_FIFO_C2B_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
#define DMA_IFACE_FIFO_C2B_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DMA_IFACE_FIFO_C2B_CSR_USEDW_SHIFT 0
#define DMA_IFACE_FIFO_C2B_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DMA_IFACE_FIFO_C2B_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
/* definitions for register: FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0 */
/* definitions for field: Input FIFO data value in reg: FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0 */
#define DMA_IFACE_FIFO_B2C_R0_DATA_MASK WBGEN2_GEN_MASK(0, 32)
#define DMA_IFACE_FIFO_B2C_R0_DATA_SHIFT 0
#define DMA_IFACE_FIFO_B2C_R0_DATA_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define DMA_IFACE_FIFO_B2C_R0_DATA_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
/* definitions for field: FIFO full flag in reg: FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
#define DMA_IFACE_FIFO_B2C_CSR_FULL WBGEN2_GEN_MASK(16, 1)
/* definitions for field: FIFO empty flag in reg: FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
#define DMA_IFACE_FIFO_B2C_CSR_EMPTY WBGEN2_GEN_MASK(17, 1)
/* definitions for field: FIFO counter in reg: FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
#define DMA_IFACE_FIFO_B2C_CSR_USEDW_MASK WBGEN2_GEN_MASK(0, 8)
#define DMA_IFACE_FIFO_B2C_CSR_USEDW_SHIFT 0
#define DMA_IFACE_FIFO_B2C_CSR_USEDW_W(value) WBGEN2_GEN_WRITE(value, 0, 8)
#define DMA_IFACE_FIFO_B2C_CSR_USEDW_R(reg) WBGEN2_GEN_READ(reg, 0, 8)
PACKED struct DMA_IFACE_WB {
/* [0x0]: REG Control/Status register */
uint32_t CTL;
/* [0x4]: REG Transaction Counter */
uint32_t TR_CNTR;
/* [0x8]: REG FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0 */
uint32_t FIFO_C2B_R0;
/* [0xc]: REG FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1 */
uint32_t FIFO_C2B_R1;
/* [0x10]: REG FIFO 'FIFO C2B (Core -> DMA) synchronization' control/status register */
uint32_t FIFO_C2B_CSR;
/* [0x14]: REG FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0 */
uint32_t FIFO_B2C_R0;
/* [0x18]: REG FIFO 'FIFO B2C (Bus -> Core) synchronization' control/status register */
uint32_t FIFO_B2C_CSR;
};
#endif
hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_wb.vhd 0 → 100644
View file @ c9217ac1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone DMA Streaming Interface
---------------------------------------------------------------------------------------
-- File : xdma_interface_wb.vhd
-- Author : auto-generated by wbgen2 from xdma_interface_wb.wb
-- Created : Thu Sep 27 15:39:56 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xdma_interface_wb.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
use work.dma_iface_wbgen2_pkg.all;
entity wb_dma_interface_port is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
data_clk_i : in std_logic;
dma_clk_i : in std_logic;
regs_i : in t_dma_iface_in_registers;
regs_o : out t_dma_iface_out_registers
);
end wb_dma_interface_port;
architecture syn of wb_dma_interface_port is
signal dma_iface_ctl_start_int : std_logic ;
signal dma_iface_ctl_start_int_delay : std_logic ;
signal dma_iface_ctl_start_sync0 : std_logic ;
signal dma_iface_ctl_start_sync1 : std_logic ;
signal dma_iface_ctl_start_sync2 : std_logic ;
signal dma_iface_ctl_done_sync0 : std_logic ;
signal dma_iface_ctl_done_sync1 : std_logic ;
signal dma_iface_ctl_ovf_sync0 : std_logic ;
signal dma_iface_ctl_ovf_sync1 : std_logic ;
signal dma_iface_tr_cntr_int : std_logic_vector(31 downto 0);
signal dma_iface_tr_cntr_swb : std_logic ;
signal dma_iface_tr_cntr_swb_delay : std_logic ;
signal dma_iface_tr_cntr_swb_s0 : std_logic ;
signal dma_iface_tr_cntr_swb_s1 : std_logic ;
signal dma_iface_tr_cntr_swb_s2 : std_logic ;
signal dma_iface_fifo_c2b_rst_n : std_logic ;
signal dma_iface_fifo_c2b_in_int : std_logic_vector(32 downto 0);
signal dma_iface_fifo_c2b_out_int : std_logic_vector(32 downto 0);
signal dma_iface_fifo_c2b_rdreq_int : std_logic ;
signal dma_iface_fifo_c2b_rdreq_int_d0 : std_logic ;
signal dma_iface_fifo_b2c_rst_n : std_logic ;
signal dma_iface_fifo_b2c_in_int : std_logic_vector(31 downto 0);
signal dma_iface_fifo_b2c_out_int : std_logic_vector(31 downto 0);
signal dma_iface_fifo_b2c_wrreq_int : std_logic ;
signal dma_iface_fifo_c2b_full_int : std_logic ;
signal dma_iface_fifo_c2b_empty_int : std_logic ;
signal dma_iface_fifo_c2b_usedw_int : std_logic_vector(7 downto 0);
signal dma_iface_fifo_b2c_full_int : std_logic ;
signal dma_iface_fifo_b2c_empty_int : std_logic ;
signal dma_iface_fifo_b2c_usedw_int : std_logic_vector(7 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
dma_iface_ctl_start_int <= '0';
dma_iface_ctl_start_int_delay <= '0';
dma_iface_tr_cntr_int <= "00000000000000000000000000000000";
dma_iface_tr_cntr_swb <= '0';
dma_iface_tr_cntr_swb_delay <= '0';
dma_iface_fifo_c2b_rdreq_int <= '0';
dma_iface_fifo_b2c_wrreq_int <= '0';
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
dma_iface_fifo_b2c_wrreq_int <= '0';
ack_in_progress <= '0';
else
dma_iface_ctl_start_int <= dma_iface_ctl_start_int_delay;
dma_iface_ctl_start_int_delay <= '0';
dma_iface_tr_cntr_swb <= dma_iface_tr_cntr_swb_delay;
dma_iface_tr_cntr_swb_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
dma_iface_ctl_start_int <= wrdata_reg(0);
dma_iface_ctl_start_int_delay <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= dma_iface_ctl_done_sync1;
rddata_reg(2) <= dma_iface_ctl_ovf_sync1;
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
dma_iface_tr_cntr_int <= wrdata_reg(31 downto 0);
dma_iface_tr_cntr_swb <= '1';
dma_iface_tr_cntr_swb_delay <= '1';
end if;
rddata_reg(31 downto 0) <= dma_iface_tr_cntr_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
end if;
if (dma_iface_fifo_c2b_rdreq_int_d0 = '0') then
dma_iface_fifo_c2b_rdreq_int <= not dma_iface_fifo_c2b_rdreq_int;
else
rddata_reg(31 downto 0) <= dma_iface_fifo_c2b_out_int(31 downto 0);
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end if;
when "011" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= dma_iface_fifo_c2b_out_int(32);
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dma_iface_fifo_c2b_full_int;
rddata_reg(17) <= dma_iface_fifo_c2b_empty_int;
rddata_reg(7 downto 0) <= dma_iface_fifo_c2b_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
dma_iface_fifo_b2c_in_int(31 downto 0) <= wrdata_reg(31 downto 0);
dma_iface_fifo_b2c_wrreq_int <= '1';
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(16) <= dma_iface_fifo_b2c_full_int;
rddata_reg(17) <= dma_iface_fifo_b2c_empty_int;
rddata_reg(7 downto 0) <= dma_iface_fifo_b2c_usedw_int;
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Start Transaction
process (data_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.ctl_start_o <= '0';
dma_iface_ctl_start_sync0 <= '0';
dma_iface_ctl_start_sync1 <= '0';
dma_iface_ctl_start_sync2 <= '0';
elsif rising_edge(data_clk_i) then
dma_iface_ctl_start_sync0 <= dma_iface_ctl_start_int;
dma_iface_ctl_start_sync1 <= dma_iface_ctl_start_sync0;
dma_iface_ctl_start_sync2 <= dma_iface_ctl_start_sync1;
regs_o.ctl_start_o <= dma_iface_ctl_start_sync2 and (not dma_iface_ctl_start_sync1);
end if;
end process;
-- DMA complete
-- synchronizer chain for field : DMA complete (type RO/WO, dma_clk_i -> clk_sys_i)
process (dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_iface_ctl_done_sync0 <= '0';
dma_iface_ctl_done_sync1 <= '0';
elsif rising_edge(dma_clk_i) then
dma_iface_ctl_done_sync0 <= regs_i.ctl_done_i;
dma_iface_ctl_done_sync1 <= dma_iface_ctl_done_sync0;
end if;
end process;
-- DMA overflow
-- synchronizer chain for field : DMA overflow (type RO/WO, dma_clk_i -> clk_sys_i)
process (dma_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_iface_ctl_ovf_sync0 <= '0';
dma_iface_ctl_ovf_sync1 <= '0';
elsif rising_edge(dma_clk_i) then
dma_iface_ctl_ovf_sync0 <= regs_i.ctl_ovf_i;
dma_iface_ctl_ovf_sync1 <= dma_iface_ctl_ovf_sync0;
end if;
end process;
-- Transactions Counter
-- asynchronous std_logic_vector register : Transactions Counter (type RW/RO, data_clk_i <-> clk_sys_i)
process (data_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_iface_tr_cntr_swb_s0 <= '0';
dma_iface_tr_cntr_swb_s1 <= '0';
dma_iface_tr_cntr_swb_s2 <= '0';
regs_o.tr_cntr_o <= "00000000000000000000000000000000";
elsif rising_edge(data_clk_i) then
dma_iface_tr_cntr_swb_s0 <= dma_iface_tr_cntr_swb;
dma_iface_tr_cntr_swb_s1 <= dma_iface_tr_cntr_swb_s0;
dma_iface_tr_cntr_swb_s2 <= dma_iface_tr_cntr_swb_s1;
if ((dma_iface_tr_cntr_swb_s2 = '0') and (dma_iface_tr_cntr_swb_s1 = '1')) then
regs_o.tr_cntr_o <= dma_iface_tr_cntr_int;
end if;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO C2B (Core -> DMA) synchronization
dma_iface_fifo_c2b_in_int(31 downto 0) <= regs_i.fifo_c2b_data_i;
dma_iface_fifo_c2b_in_int(32) <= regs_i.fifo_c2b_last_i;
dma_iface_fifo_c2b_rst_n <= rst_n_i;
dma_iface_fifo_c2b_INST : wbgen2_fifo_async
generic map (
g_size => 256,
g_width => 33,
g_usedw_size => 8
)
port map (
wr_req_i => regs_i.fifo_c2b_wr_req_i,
wr_full_o => regs_o.fifo_c2b_wr_full_o,
wr_empty_o => regs_o.fifo_c2b_wr_empty_o,
wr_usedw_o => regs_o.fifo_c2b_wr_usedw_o,
rd_full_o => dma_iface_fifo_c2b_full_int,
rd_empty_o => dma_iface_fifo_c2b_empty_int,
rd_usedw_o => dma_iface_fifo_c2b_usedw_int,
rd_req_i => dma_iface_fifo_c2b_rdreq_int,
rst_n_i => dma_iface_fifo_c2b_rst_n,
wr_clk_i => dma_clk_i,
rd_clk_i => clk_sys_i,
wr_data_i => dma_iface_fifo_c2b_in_int,
rd_data_o => dma_iface_fifo_c2b_out_int
);
-- extra code for reg/fifo/mem: FIFO B2C (Bus -> Core) synchronization
regs_o.fifo_b2c_data_o <= dma_iface_fifo_b2c_out_int(31 downto 0);
dma_iface_fifo_b2c_rst_n <= rst_n_i;
dma_iface_fifo_b2c_INST : wbgen2_fifo_async
generic map (
g_size => 256,
g_width => 32,
g_usedw_size => 8
)
port map (
rd_req_i => regs_i.fifo_b2c_rd_req_i,
rd_full_o => regs_o.fifo_b2c_rd_full_o,
rd_empty_o => regs_o.fifo_b2c_rd_empty_o,
rd_usedw_o => regs_o.fifo_b2c_rd_usedw_o,
wr_full_o => dma_iface_fifo_b2c_full_int,
wr_empty_o => dma_iface_fifo_b2c_empty_int,
wr_usedw_o => dma_iface_fifo_b2c_usedw_int,
wr_req_i => dma_iface_fifo_b2c_wrreq_int,
rst_n_i => dma_iface_fifo_b2c_rst_n,
rd_clk_i => data_clk_i,
wr_clk_i => clk_sys_i,
wr_data_i => dma_iface_fifo_b2c_in_int,
rd_data_o => dma_iface_fifo_b2c_out_int
);
-- extra code for reg/fifo/mem: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 0
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
dma_iface_fifo_c2b_rdreq_int_d0 <= '0';
elsif rising_edge(clk_sys_i) then
dma_iface_fifo_c2b_rdreq_int_d0 <= dma_iface_fifo_c2b_rdreq_int;
end if;
end process;
-- extra code for reg/fifo/mem: FIFO 'FIFO C2B (Core -> DMA) synchronization' data output register 1
-- extra code for reg/fifo/mem: FIFO 'FIFO B2C (Bus -> Core) synchronization' data input register 0
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/old/xdma_interface_wb.wb 0 → 100644
View file @ c9217ac1
-- Description of the wishbone interface for the wb_dma_interface core
peripheral {
name = "Wishbone DMA Streaming Interface";
description = "Simple Wishbone DMA interface for peripherals which want to stream data to a DMA";
-- Prefix for all generated ports
prefix = "dma_iface";
-- Name of the vhdl entity to be generated
hdl_entity = "wb_dma_interface_port";
mode = PIPELINED;
-- Control Register
reg {
name = "Control/Status register";
description = "A register defining the Control and Status of the core.";
prefix = "ctl";
field {
name = "Start Transaction";
description = "write 1: starts the DMA transaction.\
write 0: no effect";
prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "data_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DMA complete";
description = "read 1: the DMA has completed the transaction\
read 0: DMA transaction still in progress";
prefix = "done";
type = BIT;
clock = "dma_clk_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DMA overflow";
description = "read 1: the DMA overflow detected\
read 0: No overflow detected";
prefix = "ovf";
type = BIT;
clock = "dma_clk_i";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- Transaction Counter Register
reg {
name = "Transaction Counter";
description = "Register holding the word count to be transfered to DMA";
prefix = "tr_cntr";
field {
name = "Transactions Counter";
description = "Stores the words to be transfered to DMA";
--prefix = "";
type = SLV;
size = 32;
clock = "data_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Bus = Read, Core = Write (Core -> Bus)
fifo_reg {
size = 256;
direction = CORE_TO_BUS;
prefix = "fifo_c2b";
name = "FIFO C2B (Core -> DMA) synchronization";
description = "Data to to be written to DMA";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
clock = "dma_clk_i";
--mode = PIPELINED;
field {
name = "Output FIFO data value";
description = "Value of data word synchronized to the core clock";
prefix = "data";
type = SLV;
size = 32;
};
field {
name = "Transaction Last Data";
description = "0: Current entry is not the last transaction data\
1: Current entry is the last transaction data";
prefix = "last";
type = BIT;
};
};
-- Bus = Write, Core = Read (Bus -> Core)
fifo_reg {
size = 256;
direction = BUS_TO_CORE;
prefix = "fifo_b2c";
name = "FIFO B2C (Bus -> Core) synchronization";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
clock = "data_clk_i";
--mode = PIPELINED;
field {
name = "Input FIFO data value";
description = "Value of data word synchronized to the core clock";
prefix = "data";
type = SLV;
size = 32;
};
};
};
hdl/modules/custom_wishbone/wb_dma_interface_FIX/wb_dma_interface.old.vhd 0 → 100755
View file @ c9217ac1
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
use work.custom_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity wb_dma_interface is
generic(
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Clock Data Sink Input.
dma_clk_i : in std_logic;
-- Slave Data Sink port. To/From Data Sink Core
wb_sink_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_sink_cyc_i : in std_logic;
wb_sink_stb_i : in std_logic;
wb_sink_we_i : in std_logic;
wb_sink_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sink_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sink_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sink_ack_o : out std_logic;
wb_sink_stall_o : out std_logic;
-- Clock Data Source Input.
data_clk_i : in std_logic;
-- Slave Data Source port. To/From Data Source Core
wb_src_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_src_cyc_i : in std_logic;
wb_src_stb_i : in std_logic;
wb_src_we_i : in std_logic;
wb_src_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_src_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_src_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_src_ack_o : out std_logic;
wb_src_stall_o : out std_logic;
-- Slave Data Source port. To/From Data Source Core
wb_ctl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_ctl_cyc_i : in std_logic;
wb_ctl_stb_i : in std_logic;
wb_ctl_we_i : in std_logic;
wb_ctl_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ctl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ctl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ctl_ack_o : out std_logic;
wb_ctl_stall_o : out std_logic;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
--data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--data_valid_i : in std_logic;
--data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
--capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--dma_complete_o : out std_logic;
--dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end wb_dma_interface;
architecture rtl of wb_dma_interface is
--constant C_DATA_SIZE : natural := 32;
--constant C_OVF_COUNTER_SIZE : natural := 10;
-- FIFO signals index
--constant c_X_DATA : natural := 3;
--constant c_Y_DATA : natural := 2;
--constant c_Z_DATA : natural := 1;
--constant c_W_DATA : natural := 0;
-- Fifo Depth = 8K words * 32 bits/word
constant c_fifo_size : natural := 1024;
-- Register definition
constant c_FIFO_REG : std_logic_vector(2 downto 0) := "000";
------------------------------------------
-- Wishbone and Finite State Machine Signals
------------------------------------------
--type t_wishbone_state is (IDLE, CLASSIC, CABURST, EOBURST);
--signal wb_state : t_wishbone_state := IDLE;
signal cycle_progress : std_logic;
signal read_cycle_progress : std_logic;
signal write_cycle_progress : std_logic;
signal ack_int : std_logic;
signal stall_int : std_logic;
------------------------------------------
-- FIFO Signals
------------------------------------------
subtype fifo_data is std_logic_vector(c_wishbone_data_width downto 0);
--subtype fifo_count is std_logic_vector(12 downto 0);
subtype fifo_ctrl is std_logic;
--signal fifo_do_concat : std_logic_vector(C_NBITS_VALID_INPUT-1 downto 0);
signal data_i_d1 : std_logic_vector(c_wishbone_data_width-1 downto 0);
-- read data_i: 32-bit (each) output: read output data_i
signal fifo_do : fifo_data;
-- status: 1-bit (each) output: flags and other fifo status outputs
signal fifo_empty : fifo_ctrl;
signal fifo_full : fifo_ctrl;
-- read control signals: 1-bit (each) input: read clock, enable and reset input signals
signal fifo_rdclk : fifo_ctrl;
signal fifo_rden : fifo_ctrl;
signal fifo_rst_n : fifo_ctrl;
-- counter fifo signals
--signal fifo_rd_data_count : fifo_count;
--signal fifo_wr_data_count : fifo_count;
-- write control signals: 1-bit (each) input: write clock and enable input signals
signal fifo_wrclk : fifo_ctrl;
signal fifo_wren : fifo_ctrl;
-- write data_i: 32-bit (each) input: write input data_i
signal fifo_di : fifo_data;
signal last_data_reg : std_logic;
-- Overflow counter. One extra bit for easy overflow detection
signal s_fifo_ovf_c : std_logic_vector(g_ovf_counter_width downto 0);
signal s_fifo_ovf : std_logic;
------------------------------------------
-- Internal Control
------------------------------------------
signal capture_ctl_reg : std_logic_vector(c_wishbone_data_width-1 downto 0);
signal start_acq : std_logic;
signal start_acq_trig : std_logic;
------------------------------------------
-- Reset Synch
------------------------------------------
signal data_clk_rst_n : std_logic;
signal dma_clk_rst_n : std_logic;
------------------------------------------
-- DMA output signals
------------------------------------------
-- C_NBITS_DATA_INPUT+1 bits. C_NBITS_DATA_INPUT bits (LSBs) for data_i and 1 bit (MSB) for last data_i bit
signal dma_data_out0 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out0 : std_logic;
signal dma_data_out1 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out1 : std_logic;
signal dma_data_out2 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out2 : std_logic;
signal dma_data_out3 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out3 : std_logic;
signal dma_valid_s : std_logic;
signal dma_ready_s : std_logic;
signal dma_last_s : std_logic;
signal s_last_data : std_logic;
signal dma_valid_reg0 : std_logic;
-- Counter to coordinate the FIFO output - DMA input
signal output_counter_rd : std_logic_vector(1 downto 0);
signal pre_output_counter_wr : std_logic_vector(1 downto 0);
-- Internal signals
signal dma_complete_int : std_logic;
signal dma_last_int : std_logic;
signal dma_valid_int : std_logic;
signal dma_data_int : std_logic_vector(c_wishbone_data_width-1 downto 0);
-- Functions. Improve this function. Not generic.
function f_end_counter(counter : std_logic_vector(c_wishbone_data_width-1 downto 0))
return boolean is
begin
if counter(c_wishbone_data_width-1) = '1' and
unsigned(counter(c_wishbone_data_width-2 downto 0)) = 0 then
return true;
else
return false;
end if;
end f_end_counter;
begin
-- DMA signals glue
--dma_last_o <= s_dma_last_glue;
--dma_valid_o <= s_dma_valid_glue;
--dma_data_o <= s_dma_data_glue;
-- Debug data_i
--dma_debug_clk_o <= dma_clk_i;
--
--dma_debug_trigger_o(15 downto 6) <= (others => '0');
--dma_debug_trigger_o(5) <= fifo_full(C_W_DATA);
--dma_debug_trigger_o(4) <= start_acq_trig;
--dma_debug_trigger_o(3) <= capture_ctl_reg(21);
--dma_debug_trigger_o(2) <= dma_ready_i;
--dma_debug_trigger_o(1) <= s_dma_last_glue;
--dma_debug_trigger_o(0) <= s_dma_valid_glue;
--
--dma_debug_data_o(255 downto 120) <= (others => '0');
--dma_debug_data_o(119 downto 109) <= s_fifo_ovf_c(10 downto 0);
--dma_debug_data_o(108) <= s_dma_complete;
--dma_debug_data_o(107) <= start_acq_trig;
--dma_debug_data_o(106) <= fifo_full(C_W_DATA);
--dma_debug_data_o(105 downto 84) <= capture_ctl_reg;
--dma_debug_data_o(83 downto 52) <= s_dma_data_glue(31 downto 0);
--dma_debug_data_o(51 downto 36) <= fifo_do(C_W_DATA)(15 downto 0);-- FIXXXX
--dma_debug_data_o(35 downto 34) <= output_counter_rd;
--dma_debug_data_o(33 downto 32) <= pre_output_counter_wr;
--dma_debug_data_o(31 downto 19) <= fifo_wr_data_count(C_W_DATA);--(5 downto 0);
--dma_debug_data_o(18 downto 6) <= fifo_rd_data_count(C_W_DATA);--(5 downto 0);
--dma_debug_data_o(5) <= dma_ready_s;
--dma_debug_data_o(4) <= dma_valid_reg0;
--dma_debug_data_o(3) <= dma_valid_s;
--dma_debug_data_o(2) <= dma_ready_i;
--dma_debug_data_o(1) <= s_dma_last_glue;
--dma_debug_data_o(0) <= s_dma_valid_glue;
--------------------------------
-- Wishbone interface instantiation
--------------------------------
--wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
--wb_cyc_i : in std_logic;
--wb_stb_i : in std_logic;
--wb_we_i : in std_logic;
--wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--wb_cti_i : in std_logic_vector(2 downto 0);
--wb_bte_i : in std_logic_vector(1 downto 0);
wb_dat_o <= dma_data_int;
wb_ack_o <= ack_int;
wb_stall_o <= stall_int;
--FIXXX
-- Hard-wired slave pins
--slave_o.ACK <= slave_o_ACK;
--slave_o.ERR <= '0';
--slave_o.RTY <= '0';
--slave_o.STALL <= '0';
--slave_o.DAT <= slave_o_DAT;
-- Hard-wired master pins
--r_master_o.CYC <= r_master_o_CYC;
--w_master_o.CYC <= w_master_o_CYC;
--r_master_o.STB <= r_master_o_STB;
--w_master_o.STB <= w_master_o_STB;
--r_master_o.ADR <= read_issue_address;
--w_master_o.ADR <= write_issue_address;
--r_master_o.SEL <= (others => '1');
--w_master_o.SEL <= (others => '1');
--r_master_o.WE <= '0';
--w_master_o.WE <= '1';
--r_master_o.DAT <= (others => '0');
--w_master_o.DAT <= ring(index(write_issue_offset));
--------------------------------
-- Reset Logic
--------------------------------
-- FIFO reset cycle: RST must be held high for at least three RDCLK clock cycles,
-- and RDEN must be low for four clock cycles before RST becomes active high, and RDEN
-- remains low during this reset cycle.
-- Guarantees the synchronicity with the input clock on reset deassertion
cmp_reset_synch_dma : reset_synch
port map(
clk_i => dma_clk_i,
arst_n_i => arst_n_i,
rst_n_o => dma_clk_rst_n
);
cmp_reset_synch_data : reset_synch
port map(
clk_i => data_clk_i,
arst_n_i => arst_n_i,
rst_n_o => data_clk_rst_n
);
--------------------------------
-- Start Acquisition logic
--------------------------------
-- Simple trigger detector 0 -> 1 for start_acq.
-- Synchronize with bus clock data_clk_i might not be the same
p_start_acq_trig : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => data_clk_rst_n,
clk_i => data_clk_i,
data_i => start_acq,
synced_o => start_acq_trig,
npulse_o => open
);
-- MSB bit representing the start acquisition signal
start_acq <= capture_ctl_i(c_wishbone_data_width-1);
--------------------------------
-- Samples Counter Logic
--------------------------------
-- Hold counter for "capture_count" clock cycles
p_samples_counter : process (data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
capture_ctl_reg <= (others => '0');
elsif rising_edge(data_clk_i) then
-- start counting and stop only when we have input all data to fifos
if capture_ctl_reg(c_wishbone_data_width-1) = '1' and
data_valid_i = '1' and fifo_full = '0' then
capture_ctl_reg <= std_logic_vector(unsigned(capture_ctl_reg) - 1);
-- assign only when 0 -> 1 transition of MSB of start_acq. MSB of capture_ctl_reg
elsif start_acq_trig = '1' then
if data_valid_i = '1' then
-- MSB of capture_ctl_i might not be 1 by this time. Force to 1 then...
capture_ctl_reg <= '1' & std_logic_vector(unsigned(capture_ctl_i(c_wishbone_data_width-2 downto 0)) - 1);
else
-- Do not decrement now. wait until data_valid is set
capture_ctl_reg <= '1' & std_logic_vector(unsigned(capture_ctl_i(c_wishbone_data_width-2 downto 0)));
end if;
end if;
end if;
end process p_samples_counter;
--------------------------------
-- DMA Last Data Logic
--------------------------------
p_last_data_proc : process(data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
last_data_reg <= '0';
elsif rising_edge(data_clk_i) then
last_data_reg <= s_last_data;
end if;
end process p_last_data_proc;
-- bit c_wishbone_data_width-1 = 1 and bits c_wishbone_data_width-2 downto 0 = 0
s_last_data <= '1' when
f_end_counter(capture_ctl_reg(c_wishbone_data_width-1 downto 0)) and data_valid_i = '1' else '0';
--------------------------------
-- FIFO Write Enable Logic
--------------------------------
p_fifo_wr_en : process(data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
fifo_wren <= '0';
data_i_d1 <= (others => '0');
elsif rising_edge(data_clk_i) then
-- We only need to consider one as all FIFOs are synchronized with each other
if fifo_full = '0' then
-- input data to fifo only when data is valid
fifo_wren <= capture_ctl_reg(c_wishbone_data_width-1) and data_valid_i;
end if;
--Necessary in order to input data to FIFO correctly as fifo_wren is registered
data_i_d1 <= data_i;
end if;
end process p_fifo_wr_en;
p_gen_ack : process (dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
ack_int <= '0';
elsif rising_edge(dma_clk_i) then
if cycle_progress = '1' and wb_we_i = '0' and dma_valid_int = '1' then
ack_int <= '1';
else
ack_int <= '0';
end if;
end if;
end process;
p_gen_stall : process (dma_valid_s)
begin
stall_int <= dma_valid_s;
end process;
--------------------------------
-- DMA Output Logic
--------------------------------
cycle_progress <= wb_cyc_i and wb_stb_i; --and wb_we_i = '0';
read_cycle_progress <= cycle_progress and not wb_we_i;
write_cycle_progress <= cycle_progress and wb_we_i;
--dma_ready_s <= dma_ready_i or not s_dma_valid_glue;
dma_ready_s <= read_cycle_progress or not dma_valid_int;
-- fifo is not empty and dma is ready
--dma_valid_s <= '0' when fifo_empty = '1' else read_cycle_progress;
dma_valid_s <= not fifo_empty or read_cycle_progress;
-- We have a 2 output delay for FIFO. That being said, if we have a dma_ready_i signal it will take 2 dma clock cycles
-- in order to read the data_i from FIFO.
-- By this time, dma_ready_i might not be set and we have to wait for it. To solve this 2 delay read cycle
-- it is employed a small 4 position "buffer" to hold the values read from fifo but not yet passed to the DMA.
-- Note that dma_valid_reg0 is 1 clock cycle delayed in relation to dma_valid_s. That should give time to
-- FIFO output the data_i requested. Also not that that difference between pre_output_counter_wr and output_counter_rd
-- is at most (at any given point in time) not greater than 2. Thus, with a 2 bit counter, we will not have overflow
p_dma_pre_output : process(dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_data_out0 <= (others => '0');
dma_valid_out0 <= '0';
dma_data_out1 <= (others => '0');
dma_valid_out1 <= '0';
dma_data_out2 <= (others => '0');
dma_valid_out2 <= '0';
dma_data_out3 <= (others => '0');
dma_valid_out3 <= '0';
dma_valid_reg0 <= '0';
pre_output_counter_wr <= (others => '0');
-- fifo is not empty and dma is ready
elsif rising_edge(dma_clk_i) then
--if dma_valid_reg1 = '1' then -- fifo output should be valid by now as fifo_rden was enabled and it id not empty!
-- Store output from FIFO in the correct dma_data_outX if dma_valid_reg1 is valid.
-- On the next dma_valid_reg1 operation (next clock cycle if dma_valid_reg1 remains 1),
-- clear the past dma_data_outX if dma has read from it (read pointer is in the past write position).
if pre_output_counter_wr = "00" and dma_valid_reg0 = '1' then
-- Output only the last_data bit of fifo_do
dma_data_out0(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
-- Output the data from fifo itself
dma_data_out0(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out0 <= '1';
elsif output_counter_rd = "00" and dma_ready_s = '1' then
dma_data_out0 <= (others => '0');
dma_valid_out0 <= '0';
end if;
if pre_output_counter_wr = "01" and dma_valid_reg0 = '1' then
dma_data_out1(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out1(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out1 <= '1';
elsif output_counter_rd = "01" and dma_ready_s = '1' then
dma_data_out1 <= (others => '0');
dma_valid_out1 <= '0';
end if;
if pre_output_counter_wr = "10" and dma_valid_reg0 = '1' then
dma_data_out2(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out2(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out2 <= '1';
elsif output_counter_rd = "10" and dma_ready_s = '1' then
dma_data_out2 <= (others => '0');
dma_valid_out2 <= '0';
end if;
if pre_output_counter_wr = "11" and dma_valid_reg0 = '1' then
dma_data_out3(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out3(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out3 <= '1';
elsif output_counter_rd = "11" and dma_ready_s = '1' then
dma_data_out3 <= (others => '0');
dma_valid_out3 <= '0';
end if;
if dma_valid_reg0 = '1' then --dma_valid_reg0 = '1' then
pre_output_counter_wr <= std_logic_vector(unsigned(pre_output_counter_wr) + 1);
end if;
-- 2 clock cycle delay for read from fifo.
-- Nedded to break logic into one more FF as timing constraint wasn't met,
-- due to the use of dma_valid_s directly into fifo_rden.
-- This is not a problem since there is a 4 position "buffer" after this
-- to absorb dma_ready_i deassertion
dma_valid_reg0 <= dma_valid_s;
end if;
end process p_dma_pre_output;
-- Send to DMA the correct data_i from dma_data_out, based on the currently read pointer position
p_dma_output_proc : process(dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_data_int <= (others => '0');
dma_valid_int <= '0';
--dma_be_o <= (others => '0');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= '0';
output_counter_rd <= (others => '0');
elsif rising_edge(dma_clk_i) then
if dma_ready_s = '1' then
-- verify wr counter and output corresponding output
case output_counter_rd is
when "11" =>
dma_data_int <= dma_data_out3(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out3;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out3(c_wishbone_data_width) and dma_valid_out3;
when "10" =>
dma_data_int <= dma_data_out2(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out2;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out2(c_wishbone_data_width) and dma_valid_out2;
when "01" =>
dma_data_int <= dma_data_out1(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out1;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out1(c_wishbone_data_width) and dma_valid_out1;
--when "01" =>
when others =>
dma_data_int <= dma_data_out0(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out0;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out0(c_wishbone_data_width) and dma_valid_out0;
end case;
-- Only increment output_counter_rd if it is different from pre_output_counter_wr
-- to prevent overflow!
if output_counter_rd /= pre_output_counter_wr then
output_counter_rd <= std_logic_vector(unsigned(output_counter_rd) + 1);
end if;
end if;
end if;
end process p_dma_output_proc;
-- Simple backpressure scheme. Should be almost full for correct behavior.
-- fifo_full is already synchronized with fifo write_clock
data_ready_o <= not fifo_full;
--------------------------------
-- DMA complete status
--------------------------------
dma_last_s <= dma_valid_int and read_cycle_progress and dma_last_int;
p_dma_complete : process (dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_complete_int <= '0';
elsif rising_edge(dma_clk_i) then
if dma_last_s = '1' then
-- DMA could be held to 1 when completed, but it would be more difficult
-- to bring it back to 0, since the dma transfer is initiated in the data_clk_i domain
dma_complete_int <= not dma_complete_int;
end if;
end if;
end process p_dma_complete;
dma_complete_o <= dma_complete_int;
--------------------------------
-- DMA overflow (fifo full) status and counter
--------------------------------
-- Data is lost when this is asserted.
-- FIFO is full, there is data valid on input and we are in the middle of a dma transfer
s_fifo_ovf <= fifo_full and data_valid_i and
capture_ctl_reg(c_wishbone_data_width-1);
p_dma_overflow : process (data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
s_fifo_ovf_c <= (others => '0');
elsif rising_edge(data_clk_i) then
if start_acq_trig = '1' then
s_fifo_ovf_c <= (others => '0');
elsif s_fifo_ovf = '1' then
-- Even if the counter wrapps around, an overflow will still be detected!
s_fifo_ovf_c <= '1' & std_logic_vector(unsigned(s_fifo_ovf_c(g_ovf_counter_width-1 downto 0)) + 1);
end if;
end if;
end process p_dma_overflow;
dma_ovf_o <= s_fifo_ovf_c(g_ovf_counter_width);
--------------------------------
-- FIFO instantiation
--------------------------------
cmp_fifo : generic_async_fifo
generic map(
g_data_width => c_wishbone_data_width+1,
g_size => c_fifo_size,
-- Read-side flag selection
g_with_rd_empty => true, -- with empty flag
--g_with_rd_count => false, -- with words counter
--g_with_wr_empty => false,
g_with_wr_full => true
--g_with_wr_count => false,
--g_almost_empty_threshold => ?, -- threshold for almost empty flag
--g_almost_full_threshold => ? -- threshold for almost full flag
)
port map(
rst_n_i => fifo_rst_n,
-- write port
clk_wr_i => fifo_wrclk,
d_i => fifo_di,
we_i => fifo_wren,
wr_empty_o => open,
wr_full_o => fifo_full,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => open,
-- read port
clk_rd_i => fifo_rdclk,
q_o => fifo_do,
rd_i => fifo_rden,
rd_empty_o => fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open
);
fifo_rst_n <= arst_n_i;
fifo_rden <= dma_valid_s;
fifo_rdclk <= dma_clk_i;
-- Observe the FIFO reset cycle! dma_clk_buf is the clock for fifo_rd_en
fifo_wrclk <= data_clk_i;
-- -- c_wishbone_data_width + 1 bits.
-- -- It doesn't matter if the data_i is signed or unsigned since we do not care what the input data is.
-- -- The user has to treat this and extend the sign if necessary.
fifo_di <= last_data_reg & data_i_d1;
end rtl;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/wb_dma_interface.vhd 0 → 100755
View file @ c9217ac1
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.genram_pkg.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
use work.custom_common_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity wb_dma_interface is
port(
---------------------
-- Source Interface
---------------------
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
---------------------
-- Sink Interface
---------------------
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end wb_dma_interface;
architecture rtl of wb_dma_interface is
--constant C_DATA_SIZE : natural := 32;
--constant C_OVF_COUNTER_SIZE : natural := 10;
-- FIFO signals index
--constant c_X_DATA : natural := 3;
--constant c_Y_DATA : natural := 2;
--constant c_Z_DATA : natural := 1;
--constant c_W_DATA : natural := 0;
-- Fifo Depth = 8K words * 32 bits/word
constant c_fifo_size : natural := 1024;
-- Register definition
constant c_FIFO_REG : std_logic_vector(2 downto 0) := "000";
------------------------------------------
-- Wishbone and Finite State Machine Signals
------------------------------------------
--type t_wishbone_state is (IDLE, CLASSIC, CABURST, EOBURST);
--signal wb_state : t_wishbone_state := IDLE;
signal cycle_progress : std_logic;
signal read_cycle_progress : std_logic;
signal write_cycle_progress : std_logic;
signal ack_int : std_logic;
signal stall_int : std_logic;
------------------------------------------
-- FIFO Signals
------------------------------------------
subtype fifo_data is std_logic_vector(c_wishbone_data_width downto 0);
--subtype fifo_count is std_logic_vector(12 downto 0);
subtype fifo_ctrl is std_logic;
--signal fifo_do_concat : std_logic_vector(C_NBITS_VALID_INPUT-1 downto 0);
signal data_i_d1 : std_logic_vector(c_wishbone_data_width-1 downto 0);
-- read data_i: 32-bit (each) output: read output data_i
signal fifo_do : fifo_data;
-- status: 1-bit (each) output: flags and other fifo status outputs
signal fifo_empty : fifo_ctrl;
signal fifo_full : fifo_ctrl;
-- read control signals: 1-bit (each) input: read clock, enable and reset input signals
signal fifo_rdclk : fifo_ctrl;
signal fifo_rden : fifo_ctrl;
signal fifo_rst_n : fifo_ctrl;
-- counter fifo signals
--signal fifo_rd_data_count : fifo_count;
--signal fifo_wr_data_count : fifo_count;
-- write control signals: 1-bit (each) input: write clock and enable input signals
signal fifo_wrclk : fifo_ctrl;
signal fifo_wren : fifo_ctrl;
-- write data_i: 32-bit (each) input: write input data_i
signal fifo_di : fifo_data;
signal last_data_reg : std_logic;
-- Overflow counter. One extra bit for easy overflow detection
signal s_fifo_ovf_c : std_logic_vector(g_ovf_counter_width downto 0);
signal s_fifo_ovf : std_logic;
------------------------------------------
-- Internal Control
------------------------------------------
signal capture_ctl_reg : std_logic_vector(c_wishbone_data_width-1 downto 0);
signal start_acq : std_logic;
signal start_acq_trig : std_logic;
------------------------------------------
-- Reset Synch
------------------------------------------
signal data_clk_rst_n : std_logic;
signal dma_clk_rst_n : std_logic;
------------------------------------------
-- DMA output signals
------------------------------------------
-- C_NBITS_DATA_INPUT+1 bits. C_NBITS_DATA_INPUT bits (LSBs) for data_i and 1 bit (MSB) for last data_i bit
signal dma_data_out0 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out0 : std_logic;
signal dma_data_out1 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out1 : std_logic;
signal dma_data_out2 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out2 : std_logic;
signal dma_data_out3 : std_logic_vector(c_wishbone_data_width downto 0);
signal dma_valid_out3 : std_logic;
signal dma_valid_s : std_logic;
signal dma_ready_s : std_logic;
signal dma_last_s : std_logic;
signal s_last_data : std_logic;
signal dma_valid_reg0 : std_logic;
-- Counter to coordinate the FIFO output - DMA input
signal output_counter_rd : std_logic_vector(1 downto 0);
signal pre_output_counter_wr : std_logic_vector(1 downto 0);
-- Internal signals
signal dma_complete_int : std_logic;
signal dma_last_int : std_logic;
signal dma_valid_int : std_logic;
signal dma_data_int : std_logic_vector(c_wishbone_data_width-1 downto 0);
-- Functions. Improve this function. Not generic.
function f_end_counter(counter : std_logic_vector(c_wishbone_data_width-1 downto 0))
return boolean is
begin
if counter(c_wishbone_data_width-1) = '1' and
unsigned(counter(c_wishbone_data_width-2 downto 0)) = 0 then
return true;
else
return false;
end if;
end f_end_counter;
begin
-- DMA signals glue
--dma_last_o <= s_dma_last_glue;
--dma_valid_o <= s_dma_valid_glue;
--dma_data_o <= s_dma_data_glue;
-- Debug data_i
--dma_debug_clk_o <= dma_clk_i;
--
--dma_debug_trigger_o(15 downto 6) <= (others => '0');
--dma_debug_trigger_o(5) <= fifo_full(C_W_DATA);
--dma_debug_trigger_o(4) <= start_acq_trig;
--dma_debug_trigger_o(3) <= capture_ctl_reg(21);
--dma_debug_trigger_o(2) <= dma_ready_i;
--dma_debug_trigger_o(1) <= s_dma_last_glue;
--dma_debug_trigger_o(0) <= s_dma_valid_glue;
--
--dma_debug_data_o(255 downto 120) <= (others => '0');
--dma_debug_data_o(119 downto 109) <= s_fifo_ovf_c(10 downto 0);
--dma_debug_data_o(108) <= s_dma_complete;
--dma_debug_data_o(107) <= start_acq_trig;
--dma_debug_data_o(106) <= fifo_full(C_W_DATA);
--dma_debug_data_o(105 downto 84) <= capture_ctl_reg;
--dma_debug_data_o(83 downto 52) <= s_dma_data_glue(31 downto 0);
--dma_debug_data_o(51 downto 36) <= fifo_do(C_W_DATA)(15 downto 0);-- FIXXXX
--dma_debug_data_o(35 downto 34) <= output_counter_rd;
--dma_debug_data_o(33 downto 32) <= pre_output_counter_wr;
--dma_debug_data_o(31 downto 19) <= fifo_wr_data_count(C_W_DATA);--(5 downto 0);
--dma_debug_data_o(18 downto 6) <= fifo_rd_data_count(C_W_DATA);--(5 downto 0);
--dma_debug_data_o(5) <= dma_ready_s;
--dma_debug_data_o(4) <= dma_valid_reg0;
--dma_debug_data_o(3) <= dma_valid_s;
--dma_debug_data_o(2) <= dma_ready_i;
--dma_debug_data_o(1) <= s_dma_last_glue;
--dma_debug_data_o(0) <= s_dma_valid_glue;
--------------------------------
-- Wishbone interface instantiation
--------------------------------
--wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
--wb_cyc_i : in std_logic;
--wb_stb_i : in std_logic;
--wb_we_i : in std_logic;
--wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
--wb_cti_i : in std_logic_vector(2 downto 0);
--wb_bte_i : in std_logic_vector(1 downto 0);
wb_dat_o <= dma_data_int;
wb_ack_o <= ack_int;
wb_stall_o <= stall_int;
--FIXXX
-- Hard-wired slave pins
--slave_o.ACK <= slave_o_ACK;
--slave_o.ERR <= '0';
--slave_o.RTY <= '0';
--slave_o.STALL <= '0';
--slave_o.DAT <= slave_o_DAT;
-- Hard-wired master pins
--r_master_o.CYC <= r_master_o_CYC;
--w_master_o.CYC <= w_master_o_CYC;
--r_master_o.STB <= r_master_o_STB;
--w_master_o.STB <= w_master_o_STB;
--r_master_o.ADR <= read_issue_address;
--w_master_o.ADR <= write_issue_address;
--r_master_o.SEL <= (others => '1');
--w_master_o.SEL <= (others => '1');
--r_master_o.WE <= '0';
--w_master_o.WE <= '1';
--r_master_o.DAT <= (others => '0');
--w_master_o.DAT <= ring(index(write_issue_offset));
--------------------------------
-- Reset Logic
--------------------------------
-- FIFO reset cycle: RST must be held high for at least three RDCLK clock cycles,
-- and RDEN must be low for four clock cycles before RST becomes active high, and RDEN
-- remains low during this reset cycle.
-- Guarantees the synchronicity with the input clock on reset deassertion
cmp_reset_synch_dma : reset_synch
port map(
clk_i => dma_clk_i,
arst_n_i => arst_n_i,
rst_n_o => dma_clk_rst_n
);
cmp_reset_synch_data : reset_synch
port map(
clk_i => data_clk_i,
arst_n_i => arst_n_i,
rst_n_o => data_clk_rst_n
);
--------------------------------
-- Start Acquisition logic
--------------------------------
-- Simple trigger detector 0 -> 1 for start_acq.
-- Synchronize with bus clock data_clk_i might not be the same
p_start_acq_trig : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => data_clk_rst_n,
clk_i => data_clk_i,
data_i => start_acq,
synced_o => start_acq_trig,
npulse_o => open
);
-- MSB bit representing the start acquisition signal
start_acq <= capture_ctl_i(c_wishbone_data_width-1);
--------------------------------
-- Samples Counter Logic
--------------------------------
-- Hold counter for "capture_count" clock cycles
p_samples_counter : process (data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
capture_ctl_reg <= (others => '0');
elsif rising_edge(data_clk_i) then
-- start counting and stop only when we have input all data to fifos
if capture_ctl_reg(c_wishbone_data_width-1) = '1' and
data_valid_i = '1' and fifo_full = '0' then
capture_ctl_reg <= std_logic_vector(unsigned(capture_ctl_reg) - 1);
-- assign only when 0 -> 1 transition of MSB of start_acq. MSB of capture_ctl_reg
elsif start_acq_trig = '1' then
if data_valid_i = '1' then
-- MSB of capture_ctl_i might not be 1 by this time. Force to 1 then...
capture_ctl_reg <= '1' & std_logic_vector(unsigned(capture_ctl_i(c_wishbone_data_width-2 downto 0)) - 1);
else
-- Do not decrement now. wait until data_valid is set
capture_ctl_reg <= '1' & std_logic_vector(unsigned(capture_ctl_i(c_wishbone_data_width-2 downto 0)));
end if;
end if;
end if;
end process p_samples_counter;
--------------------------------
-- DMA Last Data Logic
--------------------------------
p_last_data_proc : process(data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
last_data_reg <= '0';
elsif rising_edge(data_clk_i) then
last_data_reg <= s_last_data;
end if;
end process p_last_data_proc;
-- bit c_wishbone_data_width-1 = 1 and bits c_wishbone_data_width-2 downto 0 = 0
s_last_data <= '1' when
f_end_counter(capture_ctl_reg(c_wishbone_data_width-1 downto 0)) and data_valid_i = '1' else '0';
--------------------------------
-- FIFO Write Enable Logic
--------------------------------
p_fifo_wr_en : process(data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
fifo_wren <= '0';
data_i_d1 <= (others => '0');
elsif rising_edge(data_clk_i) then
-- We only need to consider one as all FIFOs are synchronized with each other
if fifo_full = '0' then
-- input data to fifo only when data is valid
fifo_wren <= capture_ctl_reg(c_wishbone_data_width-1) and data_valid_i;
end if;
--Necessary in order to input data to FIFO correctly as fifo_wren is registered
data_i_d1 <= data_i;
end if;
end process p_fifo_wr_en;
p_gen_ack : process (dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
ack_int <= '0';
elsif rising_edge(dma_clk_i) then
if cycle_progress = '1' and wb_we_i = '0' and dma_valid_int = '1' then
ack_int <= '1';
else
ack_int <= '0';
end if;
end if;
end process;
p_gen_stall : process (dma_valid_s)
begin
stall_int <= dma_valid_s;
end process;
--------------------------------
-- DMA Output Logic
--------------------------------
cycle_progress <= wb_cyc_i and wb_stb_i; --and wb_we_i = '0';
read_cycle_progress <= cycle_progress and not wb_we_i;
write_cycle_progress <= cycle_progress and wb_we_i;
--dma_ready_s <= dma_ready_i or not s_dma_valid_glue;
dma_ready_s <= read_cycle_progress or not dma_valid_int;
-- fifo is not empty and dma is ready
--dma_valid_s <= '0' when fifo_empty = '1' else read_cycle_progress;
dma_valid_s <= not fifo_empty or read_cycle_progress;
-- We have a 2 output delay for FIFO. That being said, if we have a dma_ready_i signal it will take 2 dma clock cycles
-- in order to read the data_i from FIFO.
-- By this time, dma_ready_i might not be set and we have to wait for it. To solve this 2 delay read cycle
-- it is employed a small 4 position "buffer" to hold the values read from fifo but not yet passed to the DMA.
-- Note that dma_valid_reg0 is 1 clock cycle delayed in relation to dma_valid_s. That should give time to
-- FIFO output the data_i requested. Also not that that difference between pre_output_counter_wr and output_counter_rd
-- is at most (at any given point in time) not greater than 2. Thus, with a 2 bit counter, we will not have overflow
p_dma_pre_output : process(dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_data_out0 <= (others => '0');
dma_valid_out0 <= '0';
dma_data_out1 <= (others => '0');
dma_valid_out1 <= '0';
dma_data_out2 <= (others => '0');
dma_valid_out2 <= '0';
dma_data_out3 <= (others => '0');
dma_valid_out3 <= '0';
dma_valid_reg0 <= '0';
pre_output_counter_wr <= (others => '0');
-- fifo is not empty and dma is ready
elsif rising_edge(dma_clk_i) then
--if dma_valid_reg1 = '1' then -- fifo output should be valid by now as fifo_rden was enabled and it id not empty!
-- Store output from FIFO in the correct dma_data_outX if dma_valid_reg1 is valid.
-- On the next dma_valid_reg1 operation (next clock cycle if dma_valid_reg1 remains 1),
-- clear the past dma_data_outX if dma has read from it (read pointer is in the past write position).
if pre_output_counter_wr = "00" and dma_valid_reg0 = '1' then
-- Output only the last_data bit of fifo_do
dma_data_out0(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
-- Output the data from fifo itself
dma_data_out0(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out0 <= '1';
elsif output_counter_rd = "00" and dma_ready_s = '1' then
dma_data_out0 <= (others => '0');
dma_valid_out0 <= '0';
end if;
if pre_output_counter_wr = "01" and dma_valid_reg0 = '1' then
dma_data_out1(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out1(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out1 <= '1';
elsif output_counter_rd = "01" and dma_ready_s = '1' then
dma_data_out1 <= (others => '0');
dma_valid_out1 <= '0';
end if;
if pre_output_counter_wr = "10" and dma_valid_reg0 = '1' then
dma_data_out2(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out2(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out2 <= '1';
elsif output_counter_rd = "10" and dma_ready_s = '1' then
dma_data_out2 <= (others => '0');
dma_valid_out2 <= '0';
end if;
if pre_output_counter_wr = "11" and dma_valid_reg0 = '1' then
dma_data_out3(c_wishbone_data_width) <= fifo_do(c_wishbone_data_width);
dma_data_out3(c_wishbone_data_width-1 downto 0) <= fifo_do(c_wishbone_data_width-1 downto 0);
dma_valid_out3 <= '1';
elsif output_counter_rd = "11" and dma_ready_s = '1' then
dma_data_out3 <= (others => '0');
dma_valid_out3 <= '0';
end if;
if dma_valid_reg0 = '1' then --dma_valid_reg0 = '1' then
pre_output_counter_wr <= std_logic_vector(unsigned(pre_output_counter_wr) + 1);
end if;
-- 2 clock cycle delay for read from fifo.
-- Nedded to break logic into one more FF as timing constraint wasn't met,
-- due to the use of dma_valid_s directly into fifo_rden.
-- This is not a problem since there is a 4 position "buffer" after this
-- to absorb dma_ready_i deassertion
dma_valid_reg0 <= dma_valid_s;
end if;
end process p_dma_pre_output;
-- Send to DMA the correct data_i from dma_data_out, based on the currently read pointer position
p_dma_output_proc : process(dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_data_int <= (others => '0');
dma_valid_int <= '0';
--dma_be_o <= (others => '0');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= '0';
output_counter_rd <= (others => '0');
elsif rising_edge(dma_clk_i) then
if dma_ready_s = '1' then
-- verify wr counter and output corresponding output
case output_counter_rd is
when "11" =>
dma_data_int <= dma_data_out3(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out3;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out3(c_wishbone_data_width) and dma_valid_out3;
when "10" =>
dma_data_int <= dma_data_out2(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out2;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out2(c_wishbone_data_width) and dma_valid_out2;
when "01" =>
dma_data_int <= dma_data_out1(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out1;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out1(c_wishbone_data_width) and dma_valid_out1;
--when "01" =>
when others =>
dma_data_int <= dma_data_out0(c_wishbone_data_width-1 downto 0);
dma_valid_int <= dma_valid_out0;
--dma_be_o <= (others => '1');
-- The MSB is an indicator of the last data_i requested!
dma_last_int <= dma_data_out0(c_wishbone_data_width) and dma_valid_out0;
end case;
-- Only increment output_counter_rd if it is different from pre_output_counter_wr
-- to prevent overflow!
if output_counter_rd /= pre_output_counter_wr then
output_counter_rd <= std_logic_vector(unsigned(output_counter_rd) + 1);
end if;
end if;
end if;
end process p_dma_output_proc;
-- Simple backpressure scheme. Should be almost full for correct behavior.
-- fifo_full is already synchronized with fifo write_clock
data_ready_o <= not fifo_full;
--------------------------------
-- DMA complete status
--------------------------------
dma_last_s <= dma_valid_int and read_cycle_progress and dma_last_int;
p_dma_complete : process (dma_clk_i, dma_clk_rst_n)
begin
if dma_clk_rst_n = '0' then
dma_complete_int <= '0';
elsif rising_edge(dma_clk_i) then
if dma_last_s = '1' then
-- DMA could be held to 1 when completed, but it would be more difficult
-- to bring it back to 0, since the dma transfer is initiated in the data_clk_i domain
dma_complete_int <= not dma_complete_int;
end if;
end if;
end process p_dma_complete;
dma_complete_o <= dma_complete_int;
--------------------------------
-- DMA overflow (fifo full) status and counter
--------------------------------
-- Data is lost when this is asserted.
-- FIFO is full, there is data valid on input and we are in the middle of a dma transfer
s_fifo_ovf <= fifo_full and data_valid_i and
capture_ctl_reg(c_wishbone_data_width-1);
p_dma_overflow : process (data_clk_i, data_clk_rst_n)
begin
if data_clk_rst_n = '0' then
s_fifo_ovf_c <= (others => '0');
elsif rising_edge(data_clk_i) then
if start_acq_trig = '1' then
s_fifo_ovf_c <= (others => '0');
elsif s_fifo_ovf = '1' then
-- Even if the counter wrapps around, an overflow will still be detected!
s_fifo_ovf_c <= '1' & std_logic_vector(unsigned(s_fifo_ovf_c(g_ovf_counter_width-1 downto 0)) + 1);
end if;
end if;
end process p_dma_overflow;
dma_ovf_o <= s_fifo_ovf_c(g_ovf_counter_width);
--------------------------------
-- FIFO instantiation
--------------------------------
cmp_fifo : generic_async_fifo
generic map(
g_data_width => c_wishbone_data_width+1,
g_size => c_fifo_size,
-- Read-side flag selection
g_with_rd_empty => true, -- with empty flag
--g_with_rd_count => false, -- with words counter
--g_with_wr_empty => false,
g_with_wr_full => true
--g_with_wr_count => false,
--g_almost_empty_threshold => ?, -- threshold for almost empty flag
--g_almost_full_threshold => ? -- threshold for almost full flag
)
port map(
rst_n_i => fifo_rst_n,
-- write port
clk_wr_i => fifo_wrclk,
d_i => fifo_di,
we_i => fifo_wren,
wr_empty_o => open,
wr_full_o => fifo_full,
wr_almost_empty_o => open,
wr_almost_full_o => open,
wr_count_o => open,
-- read port
clk_rd_i => fifo_rdclk,
q_o => fifo_do,
rd_i => fifo_rden,
rd_empty_o => fifo_empty,
rd_full_o => open,
rd_almost_empty_o => open,
rd_almost_full_o => open,
rd_count_o => open
);
fifo_rst_n <= arst_n_i;
fifo_rden <= dma_valid_s;
fifo_rdclk <= dma_clk_i;
-- Observe the FIFO reset cycle! dma_clk_buf is the clock for fifo_rd_en
fifo_wrclk <= data_clk_i;
-- c_wishbone_data_width + 1 bits.
-- It doesn't matter if the data_i is signed or unsigned since we do not care what the input data is.
-- The user has to treat this and extend the sign if necessary.
fifo_di <= last_data_reg & data_i_d1;
end rtl;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/xdma_interface.wb 0 → 100644
View file @ c9217ac1
-- Description of the wishbone interface for the wb_dma_interface core
peripheral {
name = "Wishbone DMA Streaming Interface";
description = "Simple Wishbone DMA interface for peripherals which want to stream data to a DMA";
-- Prefix for all generated ports
prefix = "dma_iface";
-- Name of the vhdl entity to be generated
hdl_entity = "wb_dma_interface_port";
-- Control Register
reg {
name = "Control/Status register";
prefix = "ctl";
field {
name = "Start Transaction";
description = "write 1: starts the DMA transaction.\
write 0: no effect";
prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "data_clk_i";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DMA complete";
description = "read 1: the DMA has completed the transaction\
read 0: DMA transaction still in progress";
prefix = "done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DMA overflow";
description = "read 1: the DMA overflow detected\
read 0: No overflow detected";
prefix = "done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- Data Count Register
reg {
name = "Transaction Counter";
prefix = "tr_cntr";
field {
--name = "";
description = "Stores the the words to be transfered to DMA";
--prefix = "";
type = SLV;
size = 32;
clock = "data_clk_i";
access_bus = WRITE_ONLY;
access_dev = READ_ONLY;
};
};
-- Bus = Read, Core = Write (Core -> Bus)
fifo_reg {
size = 256;
direction = CORE_TO_BUS;
prefix = "fifo_out";
name = "FIFO DMA synchronization";
description = "Data to to be written to DMA";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
mode = PIPELINE;
field {
name = "Output FIFO data value";
description = "Value of data word synchronized to the core clock";
--prefix = "";
type = SLV;
size = 32;
clock = "dma_clk_i";
};
field {
name = "Transaction Last Data";
description = "0: Current entry is not the last transaction data\
1: Current entry is the last transaction data";
prefix = "last";
type = BIT;
clock = "dma_clk_i";
};
};
-- Bus = Write, Core = Read (Bus -> Core)
fifo_reg {
size = 256;
direction = BUS_TO_CORE;
prefix = "fifo_in";
name = "FIFO input synchronization";
flags_bus = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
flags_dev = {FIFO_FULL, FIFO_EMPTY, FIFO_COUNT};
mode = PIPELINE;
field {
name = "Input FIFO data value";
description = "Value of data word synchronized to the core clock";
--prefix = "";
type = SLV;
size = 32;
clock = "data_clk_i";
};
};
};
hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.old.vhd 0 → 100755
View file @ c9217ac1
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity xwb_dma_interface is
generic(
-- Three 32-bit data input. LSB bits are valid.
--C_NBITS_VALID_INPUT : natural := 128;
--C_NBITS_DATA_INPUT : natural := 128;
--C_OVF_COUNTER_SIZE : natural := 10
g_ovf_counter_width : natural := 10
);
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end xwb_dma_interface;
architecture rtl of xwb_dma_interface is
begin
cmp_wb_dma_interface : wb_dma_interface
port map(
-- Asynchronous Reset signal
arst_n_i => arst_n_i,
-- Write Domain Clock
dma_clk_i => dma_clk_i,
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i => dma_slave_i.sel,
wb_cyc_i => dma_slave_i.cyc,
wb_stb_i => dma_slave_i.stb,
wb_we_i => dma_slave_i.we,
wb_adr_i => dma_slave_i.adr,
wb_dat_i => dma_slave_i.dat,
--wb_cti_i => dma_dflow_slave_i.cti,
--wb_bte_i => dma_dflow_slave_i.bte,
wb_dat_o => dma_slave_o.dat,
wb_ack_o => dma_slave_o.ack,
wb_stall_o => dma_slave_o.stall,
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i => data_clk_i,
data_i => data_i,
data_valid_i => data_valid_i,
data_ready_o => data_ready_o,
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i => capture_ctl_i,
dma_complete_o => dma_complete_o,
dma_ovf_o => dma_ovf_o
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
dma_slave_o.rty <= '0';
dma_slave_o.err <= '0';
dma_slave_o.int <= '0';
end rtl;
hdl/modules/custom_wishbone/wb_dma_interface_FIX/xwb_dma_interface.vhd 0 → 100755
View file @ c9217ac1
------------------------------------------------------------------------------
-- dma_if.vhd - entity/architecture pair
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
entity xwb_dma_interface is
port(
-- Asynchronous Reset signal
arst_n_i : in std_logic;
-- Write Domain Clock
dma_clk_i : in std_logic;
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
dma_slave_i : in t_wishbone_slave_in;
dma_slave_o : out t_wishbone_slave_out;
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i : in std_logic;
data_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
data_valid_i : in std_logic;
data_ready_o : out std_logic;
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
dma_complete_o : out std_logic;
dma_ovf_o : out std_logic
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end xwb_dma_interface;
architecture rtl of xwb_dma_interface is
begin
cmp_wb_dma_interface : wb_dma_interface
port map(
-- Asynchronous Reset signal
arst_n_i => arst_n_i,
-- Write Domain Clock
dma_clk_i => dma_clk_i,
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
--dma_dflow_slave_i : in t_wishbone_dflow_slave_in;
--dma_dflow_slave_o : out t_wishbone_dflow_slave_out;
wb_sel_i => dma_slave_i.sel,
wb_cyc_i => dma_slave_i.cyc,
wb_stb_i => dma_slave_i.stb,
wb_we_i => dma_slave_i.we,
wb_adr_i => dma_slave_i.adr,
wb_dat_i => dma_slave_i.dat,
--wb_cti_i => dma_dflow_slave_i.cti,
--wb_bte_i => dma_dflow_slave_i.bte,
wb_dat_o => dma_slave_o.dat,
wb_ack_o => dma_slave_o.ack,
wb_stall_o => dma_slave_o.stall,
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i => data_clk_i,
data_i => data_i,
data_valid_i => data_valid_i,
data_ready_o => data_ready_o,
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i => capture_ctl_i,
dma_complete_o => dma_complete_o,
dma_ovf_o => dma_ovf_o
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
dma_slave_o.rty <= '0';
dma_slave_o.err <= '0';
dma_slave_o.int <= '0';
end rtl;
hdl/modules/custom_wishbone/wb_fmc150/Manifest.py 0 → 100644
View file @ c9217ac1
modules = { "local" : [
"adc",
"fmc150",
"netlist" ] };
files = ["wb_fmc150.vhd", "xwb_fmc150.vhd", "xfmc150_regs_pkg.vhd", "wb_fmc150_port.vhd",
"xwb_fmc150.vhd" ];
hdl/modules/custom_wishbone/wb_fmc150/adc/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["adc_channel_lvds_ddr.vhd", "adc_pkg.vhd", "strobe_lvds.vhd" ];
hdl/modules/custom_wishbone/wb_fmc150/adc/adc_channel_lvds_ddr.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity adc_channel_lvds_ddr is
generic
(
C_NBITS : natural := 16;
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_adc_i : in std_logic;
clk_ctrl_i : in std_logic;
adc_p_i : in std_logic_vector(C_NBITS/2 - 1 downto 0);
adc_n_i : in std_logic_vector(C_NBITS/2 - 1 downto 0);
adc_data_o : out std_logic_vector(C_NBITS - 1 downto 0);
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0)
);
end adc_channel_lvds_ddr;
architecture rtl of adc_channel_lvds_ddr is
signal s_adc_raw : std_logic_vector(C_NBITS/2 - 1 downto 0);
signal s_adc_ddr : std_logic_vector(C_NBITS/2 - 1 downto 0);
signal s_adc_ddr_dly : std_logic_vector(C_NBITS/2 - 1 downto 0);
begin
gen_adc_lvds_ddr : for i in 0 to (C_NBITS/2)-1 generate
-- Differential input buffer with termination (LVDS)
cmp_ibufds : ibufds
generic map
(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map
(
i => adc_p_i(i),
ib => adc_n_i(i),
o => s_adc_ddr(i)
);
-- Input delay
cmp_iodelay : iodelaye1
generic map
(
IDELAY_TYPE => "VAR_LOADABLE",
IDELAY_VALUE => C_DEFAULT_DELAY,
SIGNAL_PATTERN => "DATA",
DELAY_SRC => "I"
)
port map
(
idatain => s_adc_ddr(i),
dataout => s_adc_ddr_dly(i),
c => clk_ctrl_i,
ce => '0',
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
rst => ctrl_delay_update_i,
cntvaluein => ctrl_delay_value_i,
cntvalueout => open,
cinvctrl => '0',
t => '1'
);
-- DDR to SDR
cmp_iddr : iddr
generic map
(
DDR_CLK_EDGE => "SAME_EDGE_PIPELINED"
)
port map
(
q1 => adc_data_o(2*i),
q2 => adc_data_o(2*i+1),
c => clk_adc_i,
ce => '1',
d => s_adc_ddr_dly(i),
r => '0',
s => '0'
);
end generate;
end rtl;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/adc/adc_pkg.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
package adc_pkg is
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component strobe_lvds is
generic
(
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_ctrl_i : in std_logic;
strobe_p_i : in std_logic;
strobe_n_i : in std_logic;
strobe_o : out std_logic;
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0);
ctrl_delay_value_o : out std_logic_vector(4 downto 0)
);
end component;
component adc_channel_lvds_ddr is
generic
(
C_NBITS : natural := 16;
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_adc_i : in std_logic;
clk_ctrl_i : in std_logic;
adc_p_i : in std_logic_vector(C_NBITS/2 - 1 downto 0);
adc_n_i : in std_logic_vector(C_NBITS/2 - 1 downto 0);
adc_data_o : out std_logic_vector(C_NBITS - 1 downto 0);
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0)
);
end component;
end adc_pkg;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/adc/strobe_lvds.vhd 0 → 100755
View file @ c9217ac1
-----------------------------------------------------------------------------------
-- <description>
--
-- Author: Daniel Tavares (daniel.tavares@lnls.br)
-- Company: Brazilian Synchrotron Light Laboratory, Campinas, Brazil
-----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity strobe_lvds is
generic
(
C_DEFAULT_DELAY : natural := 0
);
port
(
clk_ctrl_i : in std_logic;
strobe_p_i : in std_logic;
strobe_n_i : in std_logic;
strobe_o : out std_logic;
ctrl_delay_update_i : in std_logic;
ctrl_delay_value_i : in std_logic_vector(4 downto 0);
ctrl_delay_value_o : out std_logic_vector(4 downto 0)
);
end strobe_lvds;
architecture rtl of strobe_lvds is
signal s_strobe_l : std_logic;
signal s_strobe_dly : std_logic;
begin
cmp_ibufgds : ibufds
generic map
(
IOSTANDARD => "LVDS_25",
DIFF_TERM => TRUE
)
port map
(
i => strobe_p_i,
ib => strobe_n_i,
o => s_strobe_l
);
cmp_iodelay : iodelaye1
generic map
(
IDELAY_TYPE => "VAR_LOADABLE",
IDELAY_VALUE => C_DEFAULT_DELAY,
SIGNAL_PATTERN => "CLOCK",
DELAY_SRC => "I"
)
port map
(
idatain => s_strobe_l,
dataout => s_strobe_dly,
c => clk_ctrl_i,
ce => '0',
inc => '0',
datain => '0',
odatain => '0',
clkin => '0',
rst => ctrl_delay_update_i,
cntvaluein => ctrl_delay_value_i,
cntvalueout => ctrl_delay_value_o,
cinvctrl => '0',
t => '1'
);
cmp_bufr : bufr
generic map
(
SIM_DEVICE => "VIRTEX6",
BUFR_DIVIDE => "BYPASS"
)
port map
(
clr => '1',
ce => '1',
i => s_strobe_dly,
o => strobe_o
);
end rtl;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/build_wb.sh 0 → 100755
View file @ c9217ac1
#!/bin/bash
wbgen2 -V wb_fmc150_port.vhd -H record -p xfmc150_regs_pkg.vhd -K ../../../sim/regs/xfmc150_regs_regs.vh -s struct -C xfmc150_regs_regs.h -D doc/xfmc150_regs_wb.html xfmc150.wb
hdl/modules/custom_wishbone/wb_fmc150/doc/xfmc150_regs_wb.html 0 → 100644
View file @ c9217ac1
<HTML>
<HEAD>
<TITLE>wb_fmc150_port</TITLE>
<STYLE TYPE="text/css" MEDIA="all">
<!--
BODY { background: white; color: black;
font-family: Arial,Helvetica; font-size:12; }
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h2 { font-family: Trebuchet MS,Arial,Helvetica; font-size:22; color:#404040; }
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</HEAD>
<BODY>
<h1 class="heading">wb_fmc150_port</h1>
<h3>FMC ADC/DAC interface registers</h3>
<p>FMC ADC/DAC interface</p>
<h3>Contents:</h3>
<span style="margin-left: 0px; ">1. <A href="#sect_1_0">Memory map summary</a></span><br/>
<span style="margin-left: 0px; ">2. <A href="#sect_2_0">HDL symbol</a></span><br/>
<span style="margin-left: 0px; ">3. <A href="#sect_3_0">Register description</a></span><br/>
<span style="margin-left: 20px; ">3.1. <A href="#sect_3_1">Input Flags for Pulsing Registers</a></span><br/>
<span style="margin-left: 20px; ">3.2. <A href="#sect_3_2">Input Flags for FMC150</a></span><br/>
<span style="margin-left: 20px; ">3.3. <A href="#sect_3_3">Address for Chips on FMC150</a></span><br/>
<span style="margin-left: 20px; ">3.4. <A href="#sect_3_4">Data In for Chips on FMC150</a></span><br/>
<span style="margin-left: 20px; ">3.5. <A href="#sect_3_5">Chipselect for Chips on FMC150</a></span><br/>
<span style="margin-left: 20px; ">3.6. <A href="#sect_3_6">ADC Delay</a></span><br/>
<span style="margin-left: 20px; ">3.7. <A href="#sect_3_7">Data Out From Chips on FMC150</a></span><br/>
<span style="margin-left: 20px; ">3.8. <A href="#sect_3_8">Flags out from Chips on FMC150</a></span><br/>
<h3><a name="sect_1_0">1. Memory map summary</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<th >
H/W Address
</th>
<th >
Type
</th>
<th >
Name
</th>
<th >
VHDL/Verilog prefix
</th>
<th >
C prefix
</th>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x0
</td>
<td >
REG
</td>
<td >
<A href="#FLGS_PULSE">Input Flags for Pulsing Registers</a>
</td>
<td class="td_code">
fmc150_flgs_pulse
</td>
<td class="td_code">
FLGS_PULSE
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x1
</td>
<td >
REG
</td>
<td >
<A href="#FLGS_IN">Input Flags for FMC150</a>
</td>
<td class="td_code">
fmc150_flgs_in
</td>
<td class="td_code">
FLGS_IN
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x2
</td>
<td >
REG
</td>
<td >
<A href="#ADDR">Address for Chips on FMC150</a>
</td>
<td class="td_code">
fmc150_addr
</td>
<td class="td_code">
ADDR
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x3
</td>
<td >
REG
</td>
<td >
<A href="#DATA_IN">Data In for Chips on FMC150</a>
</td>
<td class="td_code">
fmc150_data_in
</td>
<td class="td_code">
DATA_IN
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x4
</td>
<td >
REG
</td>
<td >
<A href="#CS">Chipselect for Chips on FMC150</a>
</td>
<td class="td_code">
fmc150_cs
</td>
<td class="td_code">
CS
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x5
</td>
<td >
REG
</td>
<td >
<A href="#ADC_DLY">ADC Delay</a>
</td>
<td class="td_code">
fmc150_adc_dly
</td>
<td class="td_code">
ADC_DLY
</td>
</tr>
<tr class="tr_odd">
<td class="td_code">
0x6
</td>
<td >
REG
</td>
<td >
<A href="#DATA_OUT">Data Out From Chips on FMC150</a>
</td>
<td class="td_code">
fmc150_data_out
</td>
<td class="td_code">
DATA_OUT
</td>
</tr>
<tr class="tr_even">
<td class="td_code">
0x7
</td>
<td >
REG
</td>
<td >
<A href="#FLGS_OUT">Flags out from Chips on FMC150</a>
</td>
<td class="td_code">
fmc150_flgs_out
</td>
<td class="td_code">
FLGS_OUT
</td>
</tr>
</table>
<h3><a name="sect_2_0">2. HDL symbol</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
rst_n_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Input Flags for Pulsing Registers:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
clk_sys_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_pulse_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_adr_i[2:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_dat_i[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Input Flags for FMC150:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&lArr;
</td>
<td class="td_pblock_left">
wb_dat_o[31:0]
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_in_spi_rw_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_cyc_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_in_ext_clk_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rArr;
</td>
<td class="td_pblock_left">
wb_sel_i[3:0]
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_stb_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Address for Chips on FMC150:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&rarr;
</td>
<td class="td_pblock_left">
wb_we_i
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_addr_o[15:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_ack_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Data In for Chips on FMC150:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_data_in_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Chipselect for Chips on FMC150:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_cs_cdce72010_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_cs_ads62p49_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_cs_dac3283_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_cs_amc7823_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>ADC Delay:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_adc_dly_str_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_adc_dly_cha_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_adc_dly_chb_o[4:0]
</td>
<td class="td_arrow_right">
&rArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Data Out From Chips on FMC150:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_data_out_i[31:0]
</td>
<td class="td_arrow_right">
&lArr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
<b>Flags out from Chips on FMC150:</b>
</td>
<td class="td_arrow_right">
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_spi_busy_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_pll_status_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_adc_clk_locked_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
</td>
<td class="td_pblock_left">
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc150_flgs_out_fmc_prst_i
</td>
<td class="td_arrow_right">
&larr;
</td>
</tr>
</table>
<h3><a name="sect_3_0">3. Register description</a></h3>
<a name="FLGS_PULSE"></a>
<h3><a name="sect_3_1">3.1. Input Flags for Pulsing Registers</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc150_flgs_pulse
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FLGS_PULSE
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x0
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FLGS_PULSE
</td>
</tr>
</table>
<ul>
<li><b>
FLGS_PULSE
</b>[<i>read/write</i>]: Update ADC delay
<br>write 1: pulse ADC delay register.<br> write 0: no effect
</ul>
<a name="FLGS_IN"></a>
<h3><a name="sect_3_2">3.2. Input Flags for FMC150</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc150_flgs_in
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x1
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FLGS_IN
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
EXT_CLK
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SPI_RW
</td>
</tr>
</table>
<ul>
<li><b>
SPI_RW
</b>[<i>read/write</i>]: SPI Read/Write flag
<br>write 1: write to SPI. <br> write 0: read from SPI
<li><b>
EXT_CLK
</b>[<i>read/write</i>]: External Clock for ADC
<br>write 1: external clock for ADC. <br> write 0: internal clock for ADC
</ul>
<a name="ADDR"></a>
<h3><a name="sect_3_3">3.3. Address for Chips on FMC150</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc150_addr
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x2
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ADDR
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x8
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ADDR[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
ADDR[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
ADDR
</b>[<i>read/write</i>]: SPI address
<br>Address of internal register
</ul>
<a name="DATA_IN"></a>
<h3><a name="sect_3_4">3.4. Data In for Chips on FMC150</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc150_data_in
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x3
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
DATA_IN
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0xc
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA_IN[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA_IN[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA_IN[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA_IN[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
DATA_IN
</b>[<i>read/write</i>]: Data In for FMC150
<br>Data to internal chip register
</ul>
<a name="CS"></a>
<h3><a name="sect_3_5">3.5. Chipselect for Chips on FMC150</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc150_cs
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x4
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
CS
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x10
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
AMC7823
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
DAC3283
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ADS62P49
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
CDCE72010
</td>
</tr>
</table>
<ul>
<li><b>
CDCE72010
</b>[<i>read/write</i>]: Chipselect for cdce72010
<br>write 1: select chip cdce72010 for operation.<br> write 0: no effect
<li><b>
ADS62P49
</b>[<i>read/write</i>]: Chipselect for ads62p49
<br>write 1: select chip ads62p49 for operation.<br> write 0: no effect
<li><b>
DAC3283
</b>[<i>read/write</i>]: Chipselect for dac3283
<br>write 1: select chip dac3283 for operation.<br> write 0: no effect
<li><b>
AMC7823
</b>[<i>read/write</i>]: Chipselect for amc7823
<br>write 1: select chip amc7823 for operation.<br> write 0: no effect
</ul>
<a name="ADC_DLY"></a>
<h3><a name="sect_3_6">3.6. ADC Delay</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc150_adc_dly
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x5
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
ADC_DLY
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x14
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
CHB[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
CHA[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=5 class="td_field">
STR[4:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
STR
</b>[<i>read/write</i>]: ADC Strobe delay
<br>write the strobe delay
<li><b>
CHA
</b>[<i>read/write</i>]: ADC Channel A delay
<br>write the channel A delay
<li><b>
CHB
</b>[<i>read/write</i>]: ADC Strobe delay
<br>write the channel B delay
</ul>
<a name="DATA_OUT"></a>
<h3><a name="sect_3_7">3.7. Data Out From Chips on FMC150</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc150_data_out
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x6
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
DATA_OUT
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x18
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA_OUT[31:24]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA_OUT[23:16]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA_OUT[15:8]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DATA_OUT[7:0]
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
<td >
</td>
</tr>
</table>
<ul>
<li><b>
DATA_OUT
</b>[<i>read-only</i>]: Data out from FMC150
<br>Data from internal chip register
</ul>
<a name="FLGS_OUT"></a>
<h3><a name="sect_3_8">3.8. Flags out from Chips on FMC150</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td >
<b>HW prefix: </b>
</td>
<td class="td_code">
fmc150_flgs_out
</td>
</tr>
<tr>
<td >
<b>HW address: </b>
</td>
<td class="td_code">
0x7
</td>
</tr>
<tr>
<td >
<b>C prefix: </b>
</td>
<td class="td_code">
FLGS_OUT
</td>
</tr>
<tr>
<td >
<b>C offset: </b>
</td>
<td class="td_code">
0x1c
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
31
</td>
<td class="td_bit">
30
</td>
<td class="td_bit">
29
</td>
<td class="td_bit">
28
</td>
<td class="td_bit">
27
</td>
<td class="td_bit">
26
</td>
<td class="td_bit">
25
</td>
<td class="td_bit">
24
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
23
</td>
<td class="td_bit">
22
</td>
<td class="td_bit">
21
</td>
<td class="td_bit">
20
</td>
<td class="td_bit">
19
</td>
<td class="td_bit">
18
</td>
<td class="td_bit">
17
</td>
<td class="td_bit">
16
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
15
</td>
<td class="td_bit">
14
</td>
<td class="td_bit">
13
</td>
<td class="td_bit">
12
</td>
<td class="td_bit">
11
</td>
<td class="td_bit">
10
</td>
<td class="td_bit">
9
</td>
<td class="td_bit">
8
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
</tr>
</table>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
<td class="td_bit">
7
</td>
<td class="td_bit">
6
</td>
<td class="td_bit">
5
</td>
<td class="td_bit">
4
</td>
<td class="td_bit">
3
</td>
<td class="td_bit">
2
</td>
<td class="td_bit">
1
</td>
<td class="td_bit">
0
</td>
</tr>
<tr>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td class="td_unused">
-
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
FMC_PRST
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
ADC_CLK_LOCKED
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
PLL_STATUS
</td>
<td style="border: solid 1px black;" colspan=1 class="td_field">
SPI_BUSY
</td>
</tr>
</table>
<ul>
<li><b>
SPI_BUSY
</b>[<i>read-only</i>]: SPI Busy
<br>read 1: spi busy.<br> read 0: spi idle
<li><b>
PLL_STATUS
</b>[<i>read-only</i>]: CDCE72010 PLL Status
<br>read 1: PLL locked.<br> read 0: PLL not locked
<li><b>
ADC_CLK_LOCKED
</b>[<i>read-only</i>]: FPGA ADC clock locked
<br>read 1: FPGA ADC PLL locked.<br> read 0: FPGA ADC PLL not locked
<li><b>
FMC_PRST
</b>[<i>read-only</i>]: FMC present
<br>read 1: FMC present.<br> read 0: FMC not present
</ul>
</BODY>
</HTML>
hdl/modules/custom_wishbone/wb_fmc150/fmc150/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["ads62p49_ctrl.vhd", "amc7823_ctrl.vhd", "cdce72010_ctrl.vhd", "dac3283_ctrl.vhd",
"fmc150_adc_if.vhd", "fmc150_dac_if.vhd", "fmc150_pkg.vhd", "fmc150_spi_ctrl.vhd",
"fmc150_stellar_cmd.vhd", "fmc150_testbench.vhd", "pulse2pulse.vhd"];
hdl/modules/custom_wishbone/wb_fmc150/fmc150/ads62p49_ctrl.vhd 0 → 100755
View file @ c9217ac1
-------------------------------------------------------------------------------------
-- FILE NAME : ads62p49_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - ads62p49_ctrl
-- architecture - ads62p49_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the ADS62P49 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity ads62p49_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
adc_reset : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end ads62p49_ctrl;
architecture ads62p49_ctrl_syn of ads62p49_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component ads62p49_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(4 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000077";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0000076";
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"0000076";
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal reset : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(7 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(15 downto 0);
signal init_address : std_logic_vector(4 downto 0);
signal init_data : std_logic_vector(15 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the rising edge of SCLK.
-- therefore we make sure the external clock is slightly
-- after the internal clock.
serial_clk <= clk_div(clk_div'length-1);
sclk_ext <= serial_clk;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
reset <= '1';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
reset <= out_reg(1);
else
reset <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 27) & '0' & busy & '0' & reset & init_done_prev;
-- read from serial if when address is within device range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(7 downto 0);
data_reg <= out_reg(7 downto 0);
-- Read instruction, only when address is within device range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(7 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= init_data;
-- Stop when update instruction is reveived (= last instruction)
if (init_data(15 downto 8) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length - 2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
ads62p49_init_mem_inst : ads62p49_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
adc_reset <= reset;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end ads62p49_ctrl_syn;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/amc7823_ctrl.vhd 0 → 100755
View file @ c9217ac1
-------------------------------------------------------------------------------------
-- FILE NAME : amc7823_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - amc7823_ctrl
-- architecture - amc7823_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the AMC7823 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity amc7823_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end amc7823_ctrl;
architecture amc7823_ctrl_syn of amc7823_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component amc7823_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(4 downto 0);
douta : out std_logic_vector(31 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector(27 downto 0) := x"0000320";
constant ADDR_MAX_WR : std_logic_vector(27 downto 0) := x"0000115"; --page 1 (0x40), reg 0x15
constant ADDR_MAX_RD : std_logic_vector(27 downto 0) := x"000011E"; --page 1 (0x40), reg 0x1E
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal mon_reset : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal page_reg : std_logic_vector(1 downto 0);
signal inst_reg : std_logic_vector(4 downto 0);
signal data_reg : std_logic_vector(15 downto 0);
signal sh_counter : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(31 downto 0);
signal init_address : std_logic_vector(4 downto 0);
signal init_data : std_logic_vector(31 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(15 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the falling edge of SCLK.
-- therefore we make sure the external clock is slightly
-- before the internal clock.
sclk_ext <= clk_div(clk_div'length-1);
serial_clk <= sclk_ext;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the DAC state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
mon_reset <= '1';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
page_reg <= (others=> '0');
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
mon_reset <= out_reg(1);
else
mon_reset <= '0';
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 28) & busy & not mon_n_int & mon_reset & init_done_prev;
-- read from serial if when address is within DAC range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 16) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within DAC range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
page_reg <= out_reg_addr(9 downto 8);
inst_reg <= out_reg_addr(4 downto 0);
data_reg <= out_reg(15 downto 0);
-- Read instruction, only when address is within DAC range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
page_reg <= in_reg_addr(9 downto 8);
inst_reg <= in_reg_addr(4 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- DAC serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus one data byte;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus one data byte;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- DAC instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
--rw + X,PG + X,StartADR + X,EndADR+ data
shift_reg <= '0' & init_data(26 downto 24) & init_data(21 downto 16) & init_data(21 downto 16) & init_data(15 downto 0);
-- Stop when update instruction is reveived (= last instruction)
if (init_data(31 downto 16) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
-- Always access one register per cycle
shift_reg <= inst_rw & '0' & page_reg & '0' & inst_reg & '0' & inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length - 2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from DAC
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(15 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
amc7823_init_mem_inst : amc7823_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on falling edge SCLK
-- therefore pass the signal to the process that captures on the rising edge of serial clock.
----------------------------------------------------------------------------------------------------
--process (serial_clk)
--begin
-- if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
-- end if;
--end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
mon_n_reset <= not mon_reset;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end amc7823_ctrl_syn;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/cdce72010_ctrl.vhd 0 → 100755
View file @ c9217ac1
-------------------------------------------------------------------------------------
-- FILE NAME : cdce72010_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - cdce72010_ctrl
-- architecture - cdce72010_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the CDCE72010 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity cdce72010_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
external_clock : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end cdce72010_ctrl;
architecture cdce72010_ctrl_syn of cdce72010_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component cdce72010_init_mem_int is
port (
clka : in std_logic;
addra : in std_logic_vector(3 downto 0);
douta : out std_logic_vector(31 downto 0)
);
end component;
component cdce72010_init_mem_ext is
port (
clka : in std_logic;
addra : in std_logic_vector(3 downto 0);
douta : out std_logic_vector(31 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector := x"0000010";
constant ADDR_MAX_WR : std_logic_vector := x"000000C";
constant ADDR_MAX_RD : std_logic_vector := x"000000C";
type sh_states is (idle, reg_write, start_reg_read, reg_read, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal cdce_reset : std_logic;
signal cdce_pd : std_logic;
signal ref_dis : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(3 downto 0);
signal data_reg : std_logic_vector(27 downto 0);
signal sh_counter : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(31 downto 0);
signal init_address : std_logic_vector(3 downto 0);
signal init_data_int : std_logic_vector(31 downto 0);
signal init_data_ext : std_logic_vector(31 downto 0);
signal init_data : std_logic_vector(31 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(27 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the rising edge of SCLK.
-- therefore we make sure the external clock is slightly
-- after the internal clock.
sclk_ext <= clk_div(clk_div'length-1);
serial_clk <= sclk_ext;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the DAC state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
cdce_reset <= '0';
cdce_pd <= '0';
ref_dis <= '0';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
--Write
if (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
cdce_reset <= out_reg(1);
cdce_pd <= out_reg(2);
ref_dis <= out_reg(3);
else
cdce_reset <= '0';
cdce_pd <= cdce_pd;
ref_dis <= ref_dis;
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 26) & busy & pll_status & ref_dis & cdce_pd & cdce_reset & init_done_prev;
-- Read from serial if when address is within chip range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= data_read & in_reg_addr(3 downto 0);
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within chip range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(3 downto 0);
data_reg <= out_reg(31 downto 4);
-- Read instruction, only when address is within chip range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= "1110";
data_reg <= conv_std_logic_vector(0, 24) & in_reg_addr(3 downto 0);
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- DAC serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length - 1;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= reg_write;
else
shifting <= '0';
ncs_int <= '1';
end if;
when reg_write =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length - 1;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= start_reg_read;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when start_reg_read =>
sh_counter <= shift_reg'length - 1;
shifting <= '1';
ncs_int <= '0';
sh_state <= reg_read;
when reg_read =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length - 1;
shifting <= '0';
ncs_int <= '1';
sh_state <= data_valid;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- DAC instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= init_data;
-- Stop when update instruction is reveived (= last instruction)
if (init_data(3 downto 0) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= data_reg & inst_reg;
elsif (shifting = '1') then
shift_reg <= sdi & shift_reg(shift_reg'length - 1 downto 1);
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from DAC
if (sh_state = data_valid) then
read_byte_val <= '1';
data_read <= shift_reg(31 downto 4);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory for internal clock source
----------------------------------------------------------------------------------------------------
cdce72010_init_mem_int_inst : cdce72010_init_mem_int
port map (
clka => serial_clk,
addra => init_address,
douta => init_data_int
);
----------------------------------------------------------------------------------------------------
-- Initialization memory for external clock source
----------------------------------------------------------------------------------------------------
cdce72010_init_mem_ext_inst : cdce72010_init_mem_ext
port map (
clka => serial_clk,
addra => init_address,
douta => init_data_ext
);
----------------------------------------------------------------------------------------------------
-- Select between internal clock or external clock initialisation
----------------------------------------------------------------------------------------------------
init_data <= init_data_ext when external_clock = '1' else init_data_int;
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = reg_read) else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = reg_read) else shift_reg(0);
cdce_n_reset <= not cdce_reset;
cdce_n_pd <= not cdce_pd;
ref_en <= not ref_dis;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end cdce72010_ctrl_syn;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/dac3283_ctrl.vhd 0 → 100755
View file @ c9217ac1
-------------------------------------------------------------------------------------
-- FILE NAME : dac3283_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - dac3283_ctrl
-- architecture - dac3283_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers in the DAC3283 from FPGA ROM
-- through SPI communication bus.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_unsigned.all;
entity dac3283_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end dac3283_ctrl;
architecture dac3283_ctrl_syn of dac3283_ctrl is
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
component dac3283_init_mem is
port (
clka : in std_logic;
addra : in std_logic_vector(4 downto 0);
douta : out std_logic_vector(15 downto 0)
);
end component;
constant ADDR_GLOBAL : std_logic_vector := x"0000020";
constant ADDR_MAX_WR : std_logic_vector := x"000001F";
constant ADDR_MAX_RD : std_logic_vector := x"000001F";
type sh_states is (idle, instruct, data_io, data_valid);
signal sh_state : sh_states;
signal serial_clk : std_logic;
signal sclk_ext : std_logic;
signal out_reg_val : std_logic;
signal out_reg_addr : std_logic_vector(27 downto 0);
signal out_reg : std_logic_vector(31 downto 0);
signal in_reg_req : std_logic;
signal in_reg_addr : std_logic_vector(27 downto 0);
signal in_reg_val : std_logic;
signal in_reg : std_logic_vector(31 downto 0);
signal done_sclk : std_logic;
signal init_done_sclk : std_logic;
signal init_done_tmp : std_logic;
signal init_done_prev : std_logic;
signal init : std_logic;
signal init_tmp : std_logic;
signal init_reg : std_logic;
signal inst_val : std_logic;
signal inst_reg_val : std_logic;
signal inst_rw : std_logic;
signal inst_reg : std_logic_vector(4 downto 0);
signal data_reg : std_logic_vector(7 downto 0);
signal sh_counter : integer;
signal shifting : std_logic;
signal read_n_write : std_logic;
signal ncs_int : std_logic;
signal busy : std_logic;
signal sdi : std_logic;
signal shift_reg : std_logic_vector(15 downto 0);
signal init_address : std_logic_vector(4 downto 0);
signal init_data : std_logic_vector(15 downto 0);
signal read_byte_val : std_logic;
signal data_read_val : std_logic;
signal data_read : std_logic_vector(7 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Generate serial clock (max 20MHz)
----------------------------------------------------------------------------------------------------
process (clk)
-- Divide by 2^4 = 16, CLKmax = 16 x 20MHz = 320MHz
variable clk_div : std_logic_vector(3 downto 0) := (others => '0');
begin
if (rising_edge(clk)) then
clk_div := clk_div + '1';
-- The slave samples the data on the rising edge of SCLK.
-- therefore we make sure the external clock is slightly
-- after the internal clock.
sclk_ext <= clk_div(clk_div'length-1);
serial_clk <= sclk_ext;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Stellar Command Interface
----------------------------------------------------------------------------------------------------
fmc150_stellar_cmd_inst : fmc150_stellar_cmd
generic map
(
START_ADDR => START_ADDR,
STOP_ADDR => STOP_ADDR
)
port map
(
reset => rst,
clk_cmd => clk_cmd,
in_cmd_val => in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => out_cmd_val,
out_cmd => out_cmd,
clk_reg => clk,
out_reg_val => out_reg_val,
out_reg_addr => out_reg_addr,
out_reg => out_reg,
in_reg_req => in_reg_req,
in_reg_addr => in_reg_addr,
in_reg_val => in_reg_val,
in_reg => in_reg,
mbx_in_val => '0',
mbx_in_reg => (others => '0')
);
----------------------------------------------------------------------------------------------------
-- Shoot commands to the state machine
----------------------------------------------------------------------------------------------------
process (rst, clk)
begin
if (rst = '1') then
init_done <= '0';
init_done_tmp <= '0';
init_done_prev <= '0';
init <= '0';
in_reg_val <= '0';
in_reg <= (others => '0');
inst_val <= '0';
inst_rw <= '0';
inst_reg <= (others=> '0');
data_reg <= (others=> '0');
elsif (rising_edge(clk)) then
init_done <= init_done_sclk;
init_done_tmp <= done_sclk;
init_done_prev <= init_done_tmp;
-- Release the init flag on rising edge init done
if (init_done_tmp = '1' and init_done_prev = '0') then
init <= '0';
-- Enable the init flag when enable flag is high, but done flag is low
elsif (init_ena = '1' and init_done_tmp = '0') then
init <= '1';
-- There is one additional status and control register available
elsif (out_reg_val = '1' and out_reg_addr = ADDR_GLOBAL) then
init <= out_reg(0);
end if;
-- There is one additional status and control register available
if (in_reg_req = '1' and in_reg_addr = ADDR_GLOBAL) then
in_reg_val <= '1';
in_reg <= conv_std_logic_vector(0, 27) & '0' & busy & '0' & '0' & init_done_prev;
-- read from serial if when address is within device range
elsif (in_reg_addr <= ADDR_MAX_RD) then
in_reg_val <= data_read_val;
in_reg <= conv_std_logic_vector(0, 24) & data_read;
else
in_reg_val <= '0';
in_reg <= in_reg;
end if;
-- Write instruction, only when address is within device range
if (out_reg_val = '1' and out_reg_addr <= ADDR_MAX_WR) then
inst_val <= '1';
inst_rw <= '0'; -- write
inst_reg <= out_reg_addr(4 downto 0);
data_reg <= out_reg(7 downto 0);
-- Read instruction, only when address is within device range
elsif (in_reg_req = '1' and in_reg_addr <= ADDR_MAX_RD) then
inst_val <= '1';
inst_rw <= '1'; -- read
inst_reg <= in_reg_addr(4 downto 0);
data_reg <= data_reg;
-- No instruction
else
inst_val <= '0';
inst_rw <= inst_rw;
inst_reg <= inst_reg;
data_reg <= data_reg;
end if;
end if;
end process;
-- Intruction pulse
pulse2pulse_inst0 : pulse2pulse
port map
(
rst => rst,
in_clk => clk,
out_clk => serial_clk,
pulsein => inst_val,
pulseout => inst_reg_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Serial interface state-machine
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
init_tmp <= '0';
init_reg <= '0';
sh_state <= idle;
sh_counter <= 0;
shifting <= '0';
read_n_write <= '0';
ncs_int <= '1';
elsif (rising_edge(serial_clk)) then
-- Double synchonise flag from other clock domain
init_tmp <= init;
init_reg <= init_tmp;
-- Main state machine
case sh_state is
when idle =>
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus data bytes;
-- Accept every instruction
if (inst_reg_val = '1' or init_reg = '1') then
shifting <= '1';
read_n_write <= inst_rw and not init_reg; -- force write during init
ncs_int <= '0';
sh_state <= instruct;
else
shifting <= '0';
ncs_int <= '1';
end if;
when instruct =>
if (sh_counter = 0) then
sh_counter <= data_reg'length-1;
sh_state <= data_io;
else
sh_counter <= sh_counter - 1;
end if;
when data_io =>
if (sh_counter = 0) then
sh_counter <= shift_reg'length-data_reg'length-1; --total length minus one data byte;
shifting <= '0';
ncs_int <= '1';
if (read_n_write = '1') then
sh_state <= data_valid;
else
sh_state <= idle;
end if;
else
sh_counter <= sh_counter - 1;
end if;
when data_valid =>
sh_state <= idle;
when others =>
sh_state <= idle;
end case;
end if;
end process;
busy <= '0' when (sh_state = idle and init_reg = '0') else '1';
----------------------------------------------------------------------------------------------------
-- Instruction & data shift register
----------------------------------------------------------------------------------------------------
process (rst, serial_clk)
begin
if (rst = '1') then
shift_reg <= (others => '0');
init_address <= (others => '0');
done_sclk <= '0';
init_done_sclk <= '0';
read_byte_val <= '0';
data_read <= (others => '0');
elsif (rising_edge(serial_clk)) then
if (init_reg = '1' and shifting = '0') then
shift_reg <= '0' & "00" & init_data(12 downto 0);
-- Stop when update instruction is reveived (= last instruction)
if (init_data(12 downto 8) = ADDR_MAX_WR) then
init_address <= (others => '0');
done_sclk <= '1';
else
init_address <= init_address + 1;
done_sclk <= '0';
end if;
elsif (inst_reg_val = '1' and init_reg = '0') then
shift_reg <= inst_rw & "00" & inst_reg & data_reg;
elsif (shifting = '1') then
shift_reg <= shift_reg(shift_reg'length - 2 downto 0) & sdi;
end if;
if (done_sclk = '0') then
init_done_sclk <= '0';
elsif (sh_state = idle) then
init_done_sclk <= '1';
end if;
-- Data read from device
if (sh_state = data_valid) then
read_byte_val <= '1';
--data_read <= shift_reg(8 downto 1); -- at this stage already one bit has shifted in too much
data_read <= shift_reg(7 downto 0);
else
read_byte_val <= '0';
data_read <= data_read;
end if;
end if;
end process;
-- Transfer data valid pulse to other clock domain
pulse2pulse_inst1 : pulse2pulse
port map
(
rst => rst,
in_clk => serial_clk,
out_clk => clk,
pulsein => read_byte_val,
pulseout => data_read_val,
inbusy => open
);
----------------------------------------------------------------------------------------------------
-- Initialization memory
----------------------------------------------------------------------------------------------------
dac3283_init_mem_inst : dac3283_init_mem
port map (
clka => serial_clk,
addra => init_address,
douta => init_data
);
----------------------------------------------------------------------------------------------------
-- Capture data in on rising edge SCLK
-- therefore freeze the signal on the falling edge of serial clock.
----------------------------------------------------------------------------------------------------
process (serial_clk)
begin
if (falling_edge(serial_clk)) then
sdi <= spi_sdi;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Connect entity
----------------------------------------------------------------------------------------------------
in_cmd_busy <= busy; -- serial interface busy
spi_n_oe <= '1' when (sh_state = data_io and read_n_write = '1') else ncs_int;
spi_n_cs <= ncs_int;
spi_sclk <= not sclk_ext when ncs_int = '0' else '0';
spi_sdo <= 'Z' when (sh_state = data_io and read_n_write = '1') else shift_reg(shift_reg'length - 1);
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end dac3283_ctrl_syn;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_adc_if.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.adc_pkg.all;
entity fmc150_adc_if is
port
(
clk_200MHz_i : in std_logic;
clk_100MHz_i : in std_logic;
rst_i : in std_logic;
cha_p_i : in std_logic_vector(6 downto 0);
cha_n_i : in std_logic_vector(6 downto 0);
chb_p_i : in std_logic_vector(6 downto 0);
chb_n_i : in std_logic_vector(6 downto 0);
str_p_i : in std_logic;
str_n_i : in std_logic;
cha_data_o : out std_logic_vector(13 downto 0);
chb_data_o : out std_logic_vector(13 downto 0);
clk_adc_i : in std_logic;
str_o : out std_logic;
delay_update_i : in std_logic;
str_cntvalue_i : in std_logic_vector(4 downto 0);
cha_cntvalue_i : in std_logic_vector(4 downto 0);
chb_cntvalue_i : in std_logic_vector(4 downto 0);
str_cntvalue_o : out std_logic_vector(4 downto 0)
);
end fmc150_adc_if;
architecture rtl of fmc150_adc_if is
--------------------------------------------------------------------
-- Signal declaration
--------------------------------------------------------------------
-- ADC data strobe
signal s_adc_str_dly : std_logic;
signal s_adc_str : std_logic;
-- ADC data streams on Single Data Rate (SDR)
signal s_adc_cha_sdr : std_logic_vector(13 downto 0);
signal s_adc_chb_sdr : std_logic_vector(13 downto 0);
begin
-- ADC data strobe (channel A and B) with adjustable delay
cmp_adc_str: strobe_lvds
port map
(
clk_ctrl_i => clk_100MHz_i,
strobe_p_i => str_p_i,
strobe_n_i => str_n_i,
strobe_o => s_adc_str_dly,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => str_cntvalue_i,
ctrl_delay_value_o => str_cntvalue_o
);
-- s_adc_str_dly is a regional clock driven by BUFR.
-- Must go through a BUFG before other components (BPM DDC)
-- ADC strobe must be routed on a global net
--cmp_adc_str_bufg: bufg
--port map
--(
-- i => s_adc_str_dly,
-- o => s_adc_str
--);
--str_o <= s_adc_str;
str_o <= s_adc_str_dly;
-- ADC channel A with adjustable delay
cmp_adc_cha: adc_channel_lvds_ddr
generic map
(
C_NBITS => 14,
C_DEFAULT_DELAY => 15
)
port map
(
clk_adc_i => s_adc_str_dly,--clk_adc_i,
clk_ctrl_i => clk_100MHz_i,
adc_p_i => cha_p_i,
adc_n_i => cha_n_i,
adc_data_o => cha_data_o,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => cha_cntvalue_i
);
-- ADC channel B with adjustable delay
cmp_adc_chb: adc_channel_lvds_ddr
generic map
(
C_NBITS => 14,
C_DEFAULT_DELAY => 15
)
port map
(
clk_adc_i => s_adc_str_dly,--clk_adc_i,
clk_ctrl_i => clk_100MHz_i,
adc_p_i => chb_p_i,
adc_n_i => chb_n_i,
adc_data_o => chb_data_o,
ctrl_delay_update_i => delay_update_i,
ctrl_delay_value_i => chb_cntvalue_i
);
end rtl;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_dac_if.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity fmc150_dac_if is
port
(
rst_i : in std_logic;
clk_dac_i : in std_logic;
clk_dac_2x_i : in std_logic;
dac_din_c_i : in std_logic_vector(15 downto 0);
dac_din_d_i : in std_logic_vector(15 downto 0);
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic
);
end fmc150_dac_if;
architecture rtl of fmc150_dac_if is
signal frame : std_logic;
signal io_rst : std_logic;
signal dac_dclk_prebuf : std_logic;
signal dac_data_prebuf : std_logic_vector(7 downto 0);
signal dac_frame_prebuf : std_logic;
begin
---------------------------------------------------------------------------------------------------
-- Reset sequence
----------------------------------------------------------------------------------------------------
process (rst_i, clk_dac_i)
variable cnt : integer range 0 to 1023 := 0;
begin
if (rst_i = '0') then
cnt := 0;
io_rst <= '0';
frame <= '0';
txenable_o <= '0';
elsif (rising_edge(clk_dac_i)) then
if (cnt < 1023) then
cnt := cnt + 1;
else
cnt := cnt;
end if;
-- The OSERDES blocks are synchronously reset for one clock cycle...
if (cnt = 255) then
io_rst <= '1';
else
io_rst <= '0';
end if;
-- Then a frame pulse is transmitted to the DAC...
if (cnt = 511) then
frame <= '1';
else
frame <= '0';
end if;
-- Finally the TX enable for the DAC can be pulled high.
if (cnt = 1023) then
txenable_o <= '1';
end if;
end if;
end process;
-- Output SERDES and LVDS buffer for DAC clock
oserdes_clock : oserdes
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
INIT_OQ => '0',
INIT_TQ => '0',
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 1
)
port map (
oq => dac_dclk_prebuf,
shiftout1 => open,
shiftout2 => open,
tq => open,
clk => clk_dac_2x_i,
clkdiv => clk_dac_i,
d1 => '1',
d2 => '0',
d3 => '1',
d4 => '0',
d5 => '0',
d6 => '0',
oce => '1',
rev => '0',
shiftin1 => '0',
shiftin2 => '0',
sr => io_rst,
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0'
);
-- Output buffer
obufds_clock : obufds_lvdsext_25
port map (
i => dac_dclk_prebuf,
o => dac_dclk_p_o,
ob => dac_dclk_n_o
);
-- Output serdes and LVDS buffers for DAC data
dac_data: for i in 0 to 7 generate
oserdes_data : oserdes
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
INIT_OQ => '0',
INIT_TQ => '0',
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 1
)
port map (
oq => dac_data_prebuf(i),
shiftout1 => open,
shiftout2 => open,
tq => open,
clk => clk_dac_2x_i,
clkdiv => clk_dac_i,
d1 => dac_din_c_i(i + 8),
d2 => dac_din_c_i(i),
d3 => dac_din_d_i(i + 8),
d4 => dac_din_d_i(i),
d5 => '0',
d6 => '0',
oce => '1',
rev => '0',
shiftin1 => '0',
shiftin2 => '0',
sr => io_rst,
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0'
);
--output buffers
obufds_data : obufds_lvdsext_25
port map (
i => dac_data_prebuf(i),
o => dac_data_p_o(i),
ob => dac_data_n_o(i)
);
end generate;
-- Output serdes and LVDS buffer for DAC frame
oserdes_frame : oserdes
generic map (
DATA_RATE_OQ => "DDR",
DATA_RATE_TQ => "DDR",
DATA_WIDTH => 4,
INIT_OQ => '0',
INIT_TQ => '0',
SERDES_MODE => "MASTER",
SRVAL_OQ => '0',
SRVAL_TQ => '0',
TRISTATE_WIDTH => 1
)
port map (
oq => dac_frame_prebuf,
shiftout1 => open,
shiftout2 => open,
tq => open,
clk => clk_dac_2x_i,
clkdiv => clk_dac_i,
d1 => frame,
d2 => frame,
d3 => frame,
d4 => frame,
d5 => '0',
d6 => '0',
oce => '1',
rev => '0',
shiftin1 => '0',
shiftin2 => '0',
sr => io_rst,
t1 => '0',
t2 => '0',
t3 => '0',
t4 => '0',
tce => '0'
);
--output buffer
obufds_frame : obufds_lvdsext_25
port map (
i => dac_frame_prebuf,
o => dac_frame_p_o,
ob => dac_frame_n_o
);
end rtl;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_pkg.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
package fmc150_pkg is
--------------------------------------------------------------------
-- Type definition
--------------------------------------------------------------------
type cntvalueout_array is array(13 downto 0) of std_logic_vector(4 downto 0);
type t_fmc150_ctrl_in is record
-- Common for ADS62P49, CDCE72010, AMC7823
rdwr : std_logic;
addr : std_logic_vector(15 downto 0);
data : std_logic_vector(31 downto 0);
-- ADS62P49
adc_sdo : std_logic;
ads62p49_valid : std_logic;
-- CDCE72010
cdce_sdo : std_logic;
cdce_pll_status : std_logic;
cdce_external_clock : std_logic;
cdce72010_valid : std_logic;
-- DAC3283
dac_sdo : std_logic;
dac3283_valid : std_logic;
-- AMC7823
mon_sdo : std_logic;
mon_n_int : std_logic;
amc7823_valid : std_logic;
end record t_fmc150_ctrl_in;
type t_fmc150_ctrl_out is record
-- Common for ADS62P49, CDCE72010, AMC7823
data : std_logic_vector(31 downto 0);
busy : std_logic;
-- ADS62P49
adc_en_n : std_logic;
rst_adc : std_logic;
-- CDCE72010
cdce_en_n : std_logic;
rst_cdce_n : std_logic;
cdce_n_pd : std_logic;
cdce_ref_en : std_logic;
-- DAC3283
dac_en_n : std_logic;
-- AMC7823
mon_en_n : std_logic;
rst_mon_n : std_logic;
end record t_fmc150_ctrl_out;
--------------------------------------------------------------------
-- Components
--------------------------------------------------------------------
component sin_cos
port
(
clk: in std_logic;
cosine: out std_logic_vector(15 downto 0);
sine: out std_logic_vector(15 downto 0);
phase_out: out std_logic_vector(15 downto 0)
);
end component;
component fmc150_adc_if is
port
(
clk_200MHz_i : in std_logic;
clk_100MHz_i : in std_logic;
rst_i : in std_logic;
cha_p_i : in std_logic_vector(6 downto 0);
cha_n_i : in std_logic_vector(6 downto 0);
chb_p_i : in std_logic_vector(6 downto 0);
chb_n_i : in std_logic_vector(6 downto 0);
clk_adc_i : in std_logic;
str_p_i : in std_logic;
str_n_i : in std_logic;
str_o : out std_logic;
cha_data_o : out std_logic_vector(13 downto 0);
chb_data_o : out std_logic_vector(13 downto 0);
delay_update_i : in std_logic;
str_cntvalue_i : in std_logic_vector(4 downto 0);
cha_cntvalue_i : in std_logic_vector(4 downto 0);
chb_cntvalue_i : in std_logic_vector(4 downto 0);
str_cntvalue_o : out std_logic_vector(4 downto 0)
);
end component fmc150_adc_if;
component fmc150_dac_if is
port
(
clk_dac_i : in std_logic;
clk_dac_2x_i : in std_logic;
rst_i : in std_logic;
dac_din_c_i : in std_logic_vector(15 downto 0);
dac_din_d_i : in std_logic_vector(15 downto 0);
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic
);
end component fmc150_dac_if;
component fmc150_testbench is
port (
rst : in std_logic;
clk_100Mhz : in std_logic;
clk_200Mhz : in std_logic;
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p : in std_logic;
adc_clk_ab_n : in std_logic;
adc_cha_p : in std_logic_vector(6 downto 0);
adc_cha_n : in std_logic_vector(6 downto 0);
adc_chb_p : in std_logic_vector(6 downto 0);
adc_chb_n : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p : out std_logic;
dac_dclk_n : out std_logic;
dac_data_p : out std_logic_vector(7 downto 0);
dac_data_n : out std_logic_vector(7 downto 0);
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
--Serial Peripheral Interface (SPI)
spi_sclk : out std_logic; -- Shared SPI clock line
spi_sdata : out std_logic; -- Shared SPI data line
--Clock/Trigger connection to FMC150
clk_to_fpga_p : in std_logic;
clk_to_fpga_n : in std_logic;
ext_trigger_p : in std_logic;
ext_trigger_n : in std_logic;
-- Control signals from/to FMC150
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
external_clock : in std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
--FMC Present status
prsnt_m2c_l : in std_logic;
adc_delay_update_i : in std_logic;
adc_str_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_cha_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_chb_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_str_cntvalueout_o : out std_logic_vector(4 downto 0);
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
mmcm_adc_locked_o : out std_logic
);
end component;
--------------------
-- THIRD-PARTY CODE
--------------------
component fmc150_spi_ctrl is
port
(
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
external_clock : in std_logic;
rst : in std_logic;
clk : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic
);
end component fmc150_spi_ctrl;
component cdce72010_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
external_clock : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component ads62p49_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
adc_reset : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component dac3283_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component amc7823_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component fmc150_stellar_cmd is
generic
(
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port
(
reset : in std_logic;
-- Command Interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0); --caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0); --out register address
in_reg : in std_logic_vector(31 downto 0); --requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0); --requested address
--mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0); --value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end component fmc150_stellar_cmd;
component pulse2pulse
port (
rst : in std_logic;
in_clk : in std_logic;
out_clk : in std_logic;
pulsein : in std_logic;
pulseout : out std_logic;
inbusy : out std_logic
);
end component;
end fmc150_pkg;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_spi_ctrl.vhd 0 → 100755
View file @ c9217ac1
-------------------------------------------------------------------------------------
-- FILE NAME : fmc150_spi_ctrl.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc150_spi_ctrl
-- architecture - fmc150_spi_ctrl_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file initialises the internal registers of devices on the FMC150 from
-- FPGA ROM through SPI communication busses.
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
library work;
entity fmc150_spi_ctrl is
port (
-- VIO command interface
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
rst : in std_logic;
clk : in std_logic;
external_clock : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic
);
end fmc150_spi_ctrl;
architecture fmc150_spi_ctrl_syn of fmc150_spi_ctrl is
----------------------------------------------------------------------------------------------------
-- Constant declaration
----------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------------------------------
--Component declaration
----------------------------------------------------------------------------------------------------
component cdce72010_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
external_clock : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component ads62p49_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
adc_reset : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component dac3283_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
component amc7823_ctrl is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"00000FF"
);
port (
rst : in std_logic;
clk : in std_logic;
-- Sequence interface
init_ena : in std_logic;
init_done : out std_logic;
-- Command Interface
clk_cmd : in std_logic;
in_cmd_val : in std_logic;
in_cmd : in std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
out_cmd : out std_logic_vector(63 downto 0);
in_cmd_busy : out std_logic;
-- Direct control
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
-- SPI control
spi_n_oe : out std_logic;
spi_n_cs : out std_logic;
spi_sclk : out std_logic;
spi_sdo : out std_logic;
spi_sdi : in std_logic
);
end component;
----------------------------------------------------------------------------------------------------
--Signal declaration
----------------------------------------------------------------------------------------------------
signal in_cmd : std_logic_vector(63 downto 0);
signal cdce72010_valid_prev : std_logic;
signal cdce72010_in_cmd_val : std_logic;
signal cdce72010_out_cmd_val : std_logic;
signal cdce72010_out_cmd : std_logic_vector(63 downto 0);
signal cdce72010_in_cmd_busy : std_logic;
signal ads62p49_valid_prev : std_logic;
signal ads62p49_in_cmd_val : std_logic;
signal ads62p49_out_cmd_val : std_logic;
signal ads62p49_out_cmd : std_logic_vector(63 downto 0);
signal ads62p49_in_cmd_busy : std_logic;
signal dac3283_valid_prev : std_logic;
signal dac3283_in_cmd_val : std_logic;
signal dac3283_out_cmd_val : std_logic;
signal dac3283_out_cmd : std_logic_vector(63 downto 0);
signal dac3283_in_cmd_busy : std_logic;
signal amc7823_valid_prev : std_logic;
signal amc7823_in_cmd_val : std_logic;
signal amc7823_out_cmd_val : std_logic;
signal amc7823_out_cmd : std_logic_vector(63 downto 0);
signal amc7823_in_cmd_busy : std_logic;
signal init_ena_cdce72010 : std_logic;
signal init_done_cdce72010 : std_logic;
signal init_ena_ads62p49 : std_logic;
signal init_done_ads62p49 : std_logic;
signal init_ena_dac3283 : std_logic;
signal init_done_dac3283 : std_logic;
signal init_ena_amc7823 : std_logic;
signal init_done_amc7823 : std_logic;
signal spi_n_oe0 : std_logic_vector(3 downto 0);
signal spi_n_cs0 : std_logic_vector(3 downto 0);
signal spi_sclk0 : std_logic_vector(3 downto 0);
signal spi_sdo0 : std_logic_vector(3 downto 0);
signal spi_sdi0 : std_logic_vector(3 downto 0);
begin
----------------------------------------------------------------------------------------------------
-- Input control
----------------------------------------------------------------------------------------------------
process(clk)
begin
if (rising_edge(clk)) then
cdce72010_valid_prev <= cdce72010_valid;
ads62p49_valid_prev <= ads62p49_valid;
dac3283_valid_prev <= dac3283_valid;
amc7823_valid_prev <= amc7823_valid;
cdce72010_in_cmd_val <= cdce72010_valid xor cdce72010_valid_prev;
ads62p49_in_cmd_val <= ads62p49_valid xor ads62p49_valid_prev;
dac3283_in_cmd_val <= dac3283_valid xor dac3283_valid_prev;
amc7823_in_cmd_val <= amc7823_valid xor amc7823_valid_prev;
if (rd_n_wr = '0') then
in_cmd(63 downto 60) <= x"1"; -- write command
else
in_cmd(63 downto 60) <= x"2"; -- read command
end if;
in_cmd(59 downto 32) <= x"000" & addr; -- address
in_cmd(31 downto 00) <= idata; -- data
end if;
end process;
----------------------------------------------------------------------------------------------------
-- Output control
----------------------------------------------------------------------------------------------------
process(clk)
begin
if (rising_edge(clk)) then
busy <= cdce72010_in_cmd_busy or
ads62p49_in_cmd_busy or
dac3283_in_cmd_busy or
amc7823_in_cmd_busy;
if (cdce72010_out_cmd_val = '1') then
odata <= cdce72010_out_cmd(31 downto 0);
elsif (ads62p49_out_cmd_val = '1') then
odata <= ads62p49_out_cmd(31 downto 0);
elsif (dac3283_out_cmd_val = '1') then
odata <= dac3283_out_cmd(31 downto 0);
elsif (amc7823_out_cmd_val = '1') then
odata <= amc7823_out_cmd(31 downto 0);
end if;
end if;
end process;
----------------------------------------------------------------------------------------------------
-- SPI Interface controlling the clock IC
----------------------------------------------------------------------------------------------------
cdce72010_ctrl_inst : cdce72010_ctrl
generic map (
START_ADDR => x"0000000",
STOP_ADDR => x"FFFFFFF"
)
port map (
rst => rst,
clk => clk,
init_ena => init_ena_cdce72010,
init_done => init_done_cdce72010,
clk_cmd => clk,
in_cmd_val => cdce72010_in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => cdce72010_out_cmd_val,
out_cmd => cdce72010_out_cmd,
in_cmd_busy => cdce72010_in_cmd_busy,
external_clock => external_clock,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => ref_en,
pll_status => pll_status,
spi_n_oe => spi_n_oe0(0),
spi_n_cs => spi_n_cs0(0),
spi_sclk => spi_sclk0(0),
spi_sdo => spi_sdo0(0),
spi_sdi => spi_sdi0(0)
);
----------------------------------------------------------------------------------------------------
-- SPI interface controlling ADC chip
----------------------------------------------------------------------------------------------------
ads62p49_ctrl_inst : ads62p49_ctrl
generic map (
START_ADDR => x"0000000",
STOP_ADDR => x"FFFFFFF"
)
port map (
rst => rst,
clk => clk,
init_ena => init_ena_ads62p49,
init_done => init_done_ads62p49,
clk_cmd => clk,
in_cmd_val => ads62p49_in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => ads62p49_out_cmd_val,
out_cmd => ads62p49_out_cmd,
in_cmd_busy => ads62p49_in_cmd_busy,
adc_reset => adc_reset,
spi_n_oe => spi_n_oe0(1),
spi_n_cs => spi_n_cs0(1),
spi_sclk => spi_sclk0(1),
spi_sdo => spi_sdo0(1),
spi_sdi => spi_sdi0(1)
);
----------------------------------------------------------------------------------------------------
-- SPI interface controlling DAC chip
----------------------------------------------------------------------------------------------------
dac3283_ctrl_inst : dac3283_ctrl
generic map (
START_ADDR => x"0000000",
STOP_ADDR => x"FFFFFFF"
)
port map (
rst => rst,
clk => clk,
init_ena => init_ena_dac3283,
init_done => init_done_dac3283,
clk_cmd => clk,
in_cmd_val => dac3283_in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => dac3283_out_cmd_val,
out_cmd => dac3283_out_cmd,
in_cmd_busy => dac3283_in_cmd_busy,
spi_n_oe => spi_n_oe0(2),
spi_n_cs => spi_n_cs0(2),
spi_sclk => spi_sclk0(2),
spi_sdo => spi_sdo0(2),
spi_sdi => spi_sdi0(2)
);
----------------------------------------------------------------------------------------------------
-- SPI interface controlling Monitoring chip
----------------------------------------------------------------------------------------------------
amc7823_ctrl_inst : amc7823_ctrl
generic map (
START_ADDR => x"0000000",
STOP_ADDR => x"FFFFFFF"
)
port map (
rst => rst,
clk => clk,
init_ena => init_ena_amc7823,
init_done => init_done_amc7823,
clk_cmd => clk,
in_cmd_val => amc7823_in_cmd_val,
in_cmd => in_cmd,
out_cmd_val => amc7823_out_cmd_val,
out_cmd => amc7823_out_cmd,
in_cmd_busy => amc7823_in_cmd_busy,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
spi_n_oe => spi_n_oe0(3),
spi_n_cs => spi_n_cs0(3),
spi_sclk => spi_sclk0(3),
spi_sdo => spi_sdo0(3),
spi_sdi => spi_sdi0(3)
);
----------------------------------------------------------------------------------------------------
-- SPI PHY, shared SPI bus
----------------------------------------------------------------------------------------------------
spi_sclk <= spi_sclk0(0) when spi_n_cs0(0) = '0' else
spi_sclk0(1) when spi_n_cs0(1) = '0' else
spi_sclk0(2) when spi_n_cs0(2) = '0' else
spi_sclk0(3) when spi_n_cs0(3) = '0' else '0';
spi_sdata <= spi_sdo0(0) when spi_n_oe0(0) = '0' else
spi_sdo0(1) when spi_n_oe0(1) = '0' else
spi_sdo0(2) when spi_n_oe0(2) = '0' else
spi_sdo0(3) when spi_n_oe0(3) = '0' else '0';
cdce_n_en <= spi_n_cs0(0);
adc_n_en <= spi_n_cs0(1);
dac_n_en <= spi_n_cs0(2);
mon_n_en <= spi_n_cs0(3);
spi_sdi0(0) <= cdce_sdo;
spi_sdi0(1) <= adc_sdo;
spi_sdi0(2) <= dac_sdo;
spi_sdi0(3) <= mon_sdo;
----------------------------------------------------------------------------------------------------
-- Sequence SPI initialization
----------------------------------------------------------------------------------------------------
init_ena_cdce72010 <= '1';
init_ena_ads62p49 <= init_done_cdce72010;
init_ena_dac3283 <= init_done_ads62p49;
init_ena_amc7823 <= init_done_dac3283;
----------------------------------------------------------------------------------------------------
-- End
----------------------------------------------------------------------------------------------------
end fmc150_spi_ctrl_syn;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_stellar_cmd.vhd 0 → 100755
View file @ c9217ac1
-------------------------------------------------------------------------------------
-- FILE NAME : fmc150_stellar_cmd.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - fmc150_stellar_cmd
-- architecture - fmc150_stellar_cmd_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
--
--
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
-- Entity declaration
--------------------------------------------------------------------------------
entity fmc150_stellar_cmd is
generic (
START_ADDR : std_logic_vector(27 downto 0) := x"0000000";
STOP_ADDR : std_logic_vector(27 downto 0) := x"0000010"
);
port (
reset : in std_logic;
-- Command interface
clk_cmd : in std_logic; --cmd_in and cmd_out are synchronous to this clock;
out_cmd : out std_logic_vector(63 downto 0);
out_cmd_val : out std_logic;
in_cmd : in std_logic_vector(63 downto 0);
in_cmd_val : in std_logic;
-- Register interface
clk_reg : in std_logic; --register interface is synchronous to this clock
out_reg : out std_logic_vector(31 downto 0);--caries the out register data
out_reg_val : out std_logic; --the out_reg has valid data (pulse)
out_reg_addr : out std_logic_vector(27 downto 0);--out register address
in_reg : in std_logic_vector(31 downto 0);--requested register data is placed on this bus
in_reg_val : in std_logic; --pulse to indicate requested register is valid
in_reg_req : out std_logic; --pulse to request data
in_reg_addr : out std_logic_vector(27 downto 0);--requested address
-- Mailbox interface
mbx_in_reg : in std_logic_vector(31 downto 0);--value of the mailbox to send
mbx_in_val : in std_logic --pulse to indicate mailbox is valid
);
end entity fmc150_stellar_cmd;
--------------------------------------------------------------------------------
-- Architecture declaration
--------------------------------------------------------------------------------
architecture arch_fmc150_stellar_cmd of fmc150_stellar_cmd is
-----------------------------------------------------------------------------------
-- Constant declarations
-----------------------------------------------------------------------------------
constant CMD_WR : std_logic_vector(3 downto 0) := x"1";
constant CMD_RD : std_logic_vector(3 downto 0) := x"2";
constant CMD_RD_ACK : std_logic_vector(3 downto 0) := x"4";
-----------------------------------------------------------------------------------
-- Dignal declarations
-----------------------------------------------------------------------------------
signal register_wr : std_logic;
signal register_rd : std_logic;
signal out_cmd_val_sig : std_logic;
signal in_reg_addr_sig : std_logic_vector(27 downto 0);
signal mbx_in_val_sig : std_logic;
signal mbx_received : std_logic;
-----------------------------------------------------------------------------------
-- Component declarations
-----------------------------------------------------------------------------------
component pulse2pulse
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end component;
-----------------------------------------------------------------------------------
-- Begin
-----------------------------------------------------------------------------------
begin
-----------------------------------------------------------------------------------
-- Component instantiations
-----------------------------------------------------------------------------------
p2p0: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_wr,
inbusy => open,
pulseout => out_reg_val
);
p2p1: pulse2pulse
port map (
in_clk => clk_cmd,
out_clk => clk_reg,
rst => reset,
pulsein => register_rd,
inbusy => open,
pulseout => in_reg_req
);
p2p2: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd,
rst => reset,
pulsein => in_reg_val,
inbusy => open,
pulseout => out_cmd_val_sig
);
p2p3: pulse2pulse
port map (
in_clk => clk_reg,
out_clk => clk_cmd ,
rst => reset,
pulsein => mbx_in_val,
inbusy => open,
pulseout => mbx_in_val_sig
);
-----------------------------------------------------------------------------------
-- Synchronous processes
-----------------------------------------------------------------------------------
in_reg_proc: process (reset, clk_cmd)
begin
if (reset = '1') then
in_reg_addr_sig <= (others => '0');
register_rd <= '0';
mbx_received <= '0';
out_cmd <= (others => '0');
out_cmd_val <= '0';
elsif (clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr;
end if;
--generate the read req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_RD and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_rd <= '1';
else
register_rd <= '0';
end if;
--mailbox has less priority then command acknowledge
--create the output packet
if (out_cmd_val_sig = '1' and mbx_in_val_sig = '1') then
mbx_received <= '1';
elsif( mbx_received = '1' and out_cmd_val_sig = '0') then
mbx_received <= '0';
end if;
if (out_cmd_val_sig = '1') then
out_cmd(31 downto 0) <= in_reg;
out_cmd(59 downto 32) <= in_reg_addr_sig+start_addr;
out_cmd(63 downto 60) <= CMD_RD_ACK;
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd(31 downto 0) <= mbx_in_reg;
out_cmd(59 downto 32) <= start_addr;
out_cmd(63 downto 60) <= (others=>'0');
else
out_cmd(63 downto 0) <= (others=>'0');
end if;
if (out_cmd_val_sig = '1') then
out_cmd_val <= '1';
elsif (mbx_in_val_sig = '1' or mbx_received = '1') then
out_cmd_val <= '1';
else
out_cmd_val <= '0';
end if;
end if;
end process;
out_reg_proc: process(reset, clk_cmd)
begin
if (reset = '1') then
out_reg_addr <= (others => '0');
out_reg <= (others => '0');
register_wr <= '0';
elsif(clk_cmd'event and clk_cmd = '1') then
--register the requested address when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
out_reg_addr <= in_cmd(59 downto 32) - start_addr;
out_reg <= in_cmd(31 downto 0);
end if;
--generate the write req pulse when the address is in the modules range
if (in_cmd_val = '1' and in_cmd(63 downto 60) = CMD_WR and in_cmd(59 downto 32) >= start_addr and in_cmd(59 downto 32) <= stop_addr) then
register_wr <= '1';
else
register_wr <= '0';
end if;
end if;
end process;
-----------------------------------------------------------------------------------
-- Asynchronous mapping
-----------------------------------------------------------------------------------
in_reg_addr <= in_reg_addr_sig;
-----------------------------------------------------------------------------------
-- End
-----------------------------------------------------------------------------------
end architecture arch_fmc150_stellar_cmd;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/fmc150_testbench.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library work;
use work.fmc150_pkg.all;
entity fmc150_testbench is
port
(
rst : in std_logic;
clk_100Mhz : in std_logic;
clk_200Mhz : in std_logic;
adc_clk_ab_p : in std_logic;
adc_clk_ab_n : in std_logic;
adc_cha_p : in std_logic_vector(6 downto 0);
adc_cha_n : in std_logic_vector(6 downto 0);
adc_chb_p : in std_logic_vector(6 downto 0);
adc_chb_n : in std_logic_vector(6 downto 0);
dac_dclk_p : out std_logic;
dac_dclk_n : out std_logic;
dac_data_p : out std_logic_vector(7 downto 0);
dac_data_n : out std_logic_vector(7 downto 0);
dac_frame_p : out std_logic;
dac_frame_n : out std_logic;
txenable : out std_logic;
clk_to_fpga_p : in std_logic;
clk_to_fpga_n : in std_logic;
ext_trigger_p : in std_logic;
ext_trigger_n : in std_logic;
spi_sclk : out std_logic;
spi_sdata : out std_logic;
rd_n_wr : in std_logic;
addr : in std_logic_vector(15 downto 0);
idata : in std_logic_vector(31 downto 0);
odata : out std_logic_vector(31 downto 0);
busy : out std_logic;
cdce72010_valid : in std_logic;
ads62p49_valid : in std_logic;
dac3283_valid : in std_logic;
amc7823_valid : in std_logic;
external_clock : in std_logic;
adc_n_en : out std_logic;
adc_sdo : in std_logic;
adc_reset : out std_logic;
cdce_n_en : out std_logic;
cdce_sdo : in std_logic;
cdce_n_reset : out std_logic;
cdce_n_pd : out std_logic;
ref_en : out std_logic;
pll_status : in std_logic;
dac_n_en : out std_logic;
dac_sdo : in std_logic;
mon_n_en : out std_logic;
mon_sdo : in std_logic;
mon_n_reset : out std_logic;
mon_n_int : in std_logic;
prsnt_m2c_l : in std_logic;
adc_delay_update_i : in std_logic;
adc_str_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_cha_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_chb_cntvaluein_i : in std_logic_vector(4 downto 0);
adc_str_cntvalueout_o : out std_logic_vector(4 downto 0);
adc_dout_o : out std_logic_vector(31 downto 0);
clk_adc_o : out std_logic;
mmcm_adc_locked_o : out std_logic
);
end fmc150_testbench;
architecture rtl of fmc150_testbench is
----------------------------------------------------------------------------------------------------
-- Constant declaration
----------------------------------------------------------------------------------------------------
constant ADC_STR_IDELAY : integer := 0; -- Initial number of delay taps on ADC clock input
constant ADC_CHA_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port A
constant ADC_CHB_IDELAY : integer := 0; -- Initial number of delay taps on ADC data port B
----------------------------------------------------------------------------------------------------
-- Signal declaration
----------------------------------------------------------------------------------------------------
signal clk_ab_l : std_logic;
signal clk_ab_dly : std_logic;
signal adc_cha_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal adc_cha_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal adc_cha_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal adc_chb_ddr : std_logic_vector(6 downto 0); -- Double Data Rate
signal adc_chb_ddr_dly : std_logic_vector(6 downto 0); -- Double Data Rate, Delayed
signal adc_chb_sdr : std_logic_vector(13 downto 0); -- Single Data Rate
signal adc_dout_a : std_logic_vector(15 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_dout_b : std_logic_vector(15 downto 0); -- Single Data Rate, Extended to 16-bit
signal adc_str : std_logic;
signal clk_adc : std_logic;
signal mmcm_adc_locked : std_logic;
signal fmc150_ctrl_in : t_fmc150_ctrl_in;
signal fmc150_ctrl_out : t_fmc150_ctrl_out;
signal clk_to_fpga : std_logic;
signal clk_adc_2x : std_logic;
signal dac_din_c : std_logic_vector(15 downto 0);
signal dac_din_d : std_logic_vector(15 downto 0);
signal adc_str_fbin, adc_str_out, adc_str_2x_out, adc_str_fbout : std_logic;
begin
-- I/O delay control
cmp_idelayctrl : idelayctrl
port map
(
rst => rst,
refclk => clk_200MHz,
rdy => open
);
-- ADC Clock PLL
cmp_mmcm_adc : MMCM_ADV
generic map
(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
--CLKFBOUT_MULT_F => 16.000,
CLKFBOUT_MULT_F => 8.000,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
--CLKOUT0_DIVIDE_F => 16.000,
CLKOUT0_DIVIDE_F => 8.000,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
--CLKOUT1_DIVIDE => 8,
CLKOUT1_DIVIDE => 4,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
-- 61.44 MHZ input clock
--CLKIN1_PERIOD => 16.276,
-- 122.88 MHZ input clock
CLKIN1_PERIOD => 8.138,
REF_JITTER1 => 0.010
)
port map
(
-- Output clocks
CLKFBOUT => adc_str_fbout,
CLKFBOUTB => open,
CLKOUT0 => adc_str_out,
CLKOUT0B => open,
CLKOUT1 => adc_str_2x_out,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => adc_str_fbin,
CLKIN1 => adc_str,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => mmcm_adc_locked,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst
);
-- Global clock buffers for "cmp_mmcm_adc" instance
cmp_clkf_bufg : BUFG
port map
(
O => adc_str_fbin,
I => adc_str_fbout
);
cmp_adc_str_out_bufg : BUFG
port map
(
O => clk_adc,
I => adc_str_out
);
cmp_adc_str_2x_out_bufg : BUFG
port map
(
O => clk_adc_2x,
I => adc_str_2x_out
);
clk_adc_o <= clk_adc;--adc_str;
-- ADC Interface
cmp_adc_if : fmc150_adc_if
port map
(
clk_200MHz_i => clk_200MHz,
clk_100MHz_i => clk_100MHz,
rst_i => mmcm_adc_locked,
str_p_i => adc_clk_ab_p,
str_n_i => adc_clk_ab_n,
cha_p_i => adc_cha_p,
cha_n_i => adc_cha_n,
chb_p_i => adc_chb_p,
chb_n_i => adc_chb_n,
cha_data_o => adc_cha_sdr,
chb_data_o => adc_chb_sdr,
str_o => adc_str,
-- Not used for now. Should it be removed?
clk_adc_i => adc_str,--clk_adc,
delay_update_i => adc_delay_update_i,
str_cntvalue_i => adc_str_cntvaluein_i,
cha_cntvalue_i => adc_cha_cntvaluein_i,
chb_cntvalue_i => adc_chb_cntvaluein_i,
str_cntvalue_o => adc_str_cntvalueout_o
);
-- Extend to 16-bit and register ADC data output
-- p_extend_adc_output : process (clk_adc)
-- begin
-- if (rising_edge(clk_adc)) then
p_extend_adc_output : process (adc_str)
begin
if (rising_edge(adc_str)) then
-- Left justify the data of both channels on 16-bits
adc_dout_a <= adc_cha_sdr(13) & adc_cha_sdr(13) & adc_cha_sdr;
adc_dout_b <= adc_chb_sdr(13) & adc_chb_sdr(13) & adc_chb_sdr;
-- adc_dout_a <= std_logic_vector(unsigned(adc_dout_a)+1);
-- adc_dout_b <= std_logic_vector(unsigned(adc_dout_b)-1);
end if;
end process;
adc_dout_o <= adc_dout_a & adc_dout_b;
--adc_dout_o <= dac_din_c & dac_din_d;
-- DAC Interface
cmp_dac_if : fmc150_dac_if
port map
(
rst_i => mmcm_adc_locked,
clk_dac_i => clk_adc,
clk_dac_2x_i => clk_adc_2x,
dac_din_c_i => dac_din_c,
dac_din_d_i => dac_din_d,
dac_data_p_o => dac_data_p,
dac_data_n_o => dac_data_n,
dac_dclk_p_o => dac_dclk_p,
dac_dclk_n_o => dac_dclk_n,
dac_frame_p_o => dac_frame_p,
dac_frame_n_o => dac_frame_n,
txenable_o => txenable
);
mmcm_adc_locked_o <= mmcm_adc_locked;
-- Reference signal generation (need external netlist file)
-- cmp_sin_cos : sin_cos
-- port map
-- (
-- clk => clk_adc,
-- cosine => dac_din_c,
-- sine => dac_din_d,
-- phase_out => open
-- );
-- FMC150 control (SPI and direct signals)
cmp_fmc150_ctrl : fmc150_spi_ctrl
port map
(
rst => rst,
clk => clk_100MHz,
rd_n_wr => rd_n_wr,
addr => addr,
idata => idata,
odata => odata,
busy => busy,
cdce72010_valid => cdce72010_valid,
ads62p49_valid => ads62p49_valid,
dac3283_valid => dac3283_valid,
amc7823_valid => amc7823_valid,
external_clock => external_clock,
adc_n_en => adc_n_en,
adc_sdo => adc_sdo,
adc_reset => adc_reset,
cdce_n_en => cdce_n_en,
cdce_sdo => cdce_sdo,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => ref_en,
pll_status => pll_status,
dac_n_en => dac_n_en,
dac_sdo => dac_sdo,
mon_n_en => mon_n_en,
mon_sdo => mon_sdo,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
spi_sclk => spi_sclk,
spi_sdata => spi_sdata,
prsnt_m2c_l => prsnt_m2c_l
);
end rtl;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/fmc150/pulse2pulse.vhd 0 → 100755
View file @ c9217ac1
-------------------------------------------------------------------------------------
-- FILE NAME : pulse2pulse.vhd
--
-- AUTHOR : Peter Kortekaas
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - pulse2pulse
-- architecture - pulse2pulse_syn
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- This file transfers a pulse from one clock domain (in_clk) to another (out_clk).
--
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
entity pulse2pulse is
port (
in_clk : in std_logic;
out_clk : in std_logic;
rst : in std_logic;
pulsein : in std_logic;
inbusy : out std_logic;
pulseout : out std_logic
);
end pulse2pulse;
architecture syn of pulse2pulse is
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--constant declarations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--signal declarations
-----------------------------------------------------------------------------------
signal out_set :std_logic;
signal out_set_prev :std_logic;
signal out_set_prev2 :std_logic;
signal in_set :std_logic;
signal outreset :std_logic;
signal in_reset :std_logic;
signal in_reset_prev :std_logic;
signal in_reset_prev2:std_logic;
-----------------------------------------------------------------------------------
--component declarations
-----------------------------------------------------------------------------------
--*********************************************************************************
begin
--*********************************************************************************
-----------------------------------------------------------------------------------
--component instantiations
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--synchronous processes
-----------------------------------------------------------------------------------
in_proc:process(in_clk,rst)
begin
if(rst = '1') then
in_reset <= '0';
in_reset_prev <= '0';
in_reset_prev2<= '0';
in_set <= '0';
elsif(in_clk'event and in_clk = '1') then
--regitser a pulse on the pulse in port
--reset the signal when the ouput has registerred the pulse
if (in_reset_prev = '1' and in_reset_prev2 = '1') then
in_set <= '0';
elsif (pulsein = '1') then
in_set <= '1';
end if;
--register the reset signal from the other clock domain
--three times. double stage synchronising circuit
--reduces the MTB
in_reset <= outreset;
in_reset_prev <= in_reset;
in_reset_prev2 <= in_reset_prev;
end if;
end process in_proc;
out_proc:process(out_clk,rst)
begin
if(rst = '1') then
out_set <= '0';
out_set_prev <= '0';
out_set_prev2 <= '0';
outreset <= '0';
pulseout <= '0';
elsif(out_clk'event and out_clk = '1') then
--generate a pulse on the outpput when the
--set signal has travelled through the synchronising fip flops
if (out_set_prev = '1' and out_set_prev2 = '0') then
pulseout <= '1';
else
pulseout <= '0';
end if;
--feedback the corret reception of the set signal to reset the set pulse
if (out_set_prev = '1' and out_set_prev2 = '1') then
outreset <= '1';
elsif (out_set_prev = '0' and out_set_prev2 = '0') then
outreset <= '0';
end if;
--register the reset signal from the other clock domain
--three times. double stage synchronising circuit
--reduces the MTB
out_set <= in_set;
out_set_prev <= out_set;
out_set_prev2 <= out_set_prev;
end if;
end process out_proc;
-----------------------------------------------------------------------------------
--asynchronous processes
-----------------------------------------------------------------------------------
-----------------------------------------------------------------------------------
--asynchronous mapping
-----------------------------------------------------------------------------------
inbusy <= in_set or in_reset_prev;
-------------------
-------------------
end syn;
\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/netlist/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["ads62p49_init_mem.ngc", "amc7823_init_mem.ngc", "cdce72010_init_mem_ext.ngc",
"cdce72010_init_mem_int.ngc", "dac3283_init_mem.ngc"];
hdl/modules/custom_wishbone/wb_fmc150/netlist/ads62p49_init_mem.ngc 0 → 100755
View file @ c9217ac1
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/netlist/amc7823_init_mem.ngc 0 → 100755
View file @ c9217ac1
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_ext.ngc 0 → 100755
View file @ c9217ac1
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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hdl/modules/custom_wishbone/wb_fmc150/netlist/cdce72010_init_mem_int.ngc 0 → 100755
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hdl/modules/custom_wishbone/wb_fmc150/netlist/dac3283_init_mem.ngc 0 → 100755
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XILINX-XDM V1.6e
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44b28<=7)?;c;357>o6=?0;6)?>3;36f>h69;0;76g>5483>!76;3;>n6`>1382?>o6==0;6)?>3;36f>h69;0976g>5283>!76;3;>n6`>1380?>o6=;0;6)?>3;36f>h69;0?76a>9583>!76;3;j?6`>1383?>i61:0;6)?>3;3b7>h69;0:76a>9383>!76;3;j?6`>1381?>i6180;6)?>3;3b7>h69;0876a>9183>!76;3;j?6`>1387?>i60o0;6)?>3;3b7>h69;0>76a>9b83>!76;3;j?6`>1385?>i61k0;6)?>3;3b7>h69;0<76a>9`83>!76;3;j?6`>138;?>i6100;6)?>3;3b7>h69;0276a>9983>!76;3;j?6`>138b?>i61>0;6)?>3;3b7>h69;0i76a>9783>!76;3;j?6`>138`?>i61<0;6)?>3;3b7>h69;0o76a>8d83>!76;3;j?6`>138f?>i60m0;6)?>3;3b7>h69;0m76g>6583>>d6;;0;6<4?:1yK567<,88n6<==;n324?6=3thj97>51;294~N6;81/=?k5a49le1<722wi8;4?:4f97?7?sA;8=6T;7;314c=9:0:87?l:0f954<6:3n1i7?<:0a9`?7328n1i7?>:0095`<z,88n6<86;%6;>4003->h6<87;%312?7<,88>6<;>;%33g?77n2c:o>4?::m2g<<72-;:?7?lb:l257<732e:o54?:%327?7dj2d:=?4>;:m2g2<72-;:?7?lb:l257<532e:o;4?:%327?7dj2d:=?4<;:m2g0<72-;:?7?lb:l257<332c:o=4?::k2g4<722c:on4?::k2ga<722c:h?4?:%327?7c;2d:=?4?;:k2`1<72-;:?7?k5:l257<732c:9;4?:%327?72j2d:=?4?;:k210<72-;:?7?:b:l257<632c:994?:%327?72j2d:=?4=;:k216<72-;:?7?:b:l257<432c:9?4?:%327?72j2d:=?4;;:k224<72-;:?7?92:l257<732c::=4?:%327?71:2d:=?4>;:k21c<72-;:?7?92:l257<532c:9h4?:%327?71:2d:=?4<;:k21a<72-;:?7?92:l257<332c:oh4?::k2gc<722e:h=4?::m2=1<72-;:?7?n3:l257<732e:5>4?:%327?7f;2d:=?4>;:m2=7<72-;:?7?n3:l257<532e:5<4?:%327?7f;2d:=?4<;:m2=5<72-;:?7?n3:l257<332e:4k4?:%327?7f;2d:=?4:;:m2=f<72-;:?7?n3:l257<132e:5o4?:%327?7f;2d:=?48;:m2=d<72-;:?7?n3:l257<?32e:544?:%327?7f;2d:=?46;:m2==<72-;:?7?n3:l257<f32e:5:4?:%327?7f;2d:=?4m;:m2=3<72-;:?7?n3:l257<d32e:584?:%327?7f;2d:=?4k;:m2<`<72-;:?7?n3:l257<b32e:4i4?:%327?7f;2d:=?4i;:m2f0<72-;:?7?me:l257<732e:n94?:%327?7em2d:=?4>;:m2f6<72-;:?7?me:l257<532e:n?4?:%327?7em2d:=?4<;:m2f4<72-;:?7?me:l257<332e:n=4?:%327?7em2d:=?4:;:m2fa<72-;:?7?me:l257<132e:nn4?:%327?7em2d:=?48;:m2fg<72-;:?7?me:l257<?32e:nl4?:%327?7em2d:=?46;:m2f<<72-;:?7?me:l257<f32e:n54?:%327?7em2d:=?4m;:m2f2<72-;:?7?me:l257<d32e:n;4?:%327?7em2d:=?4k;:m2ec<72-;:?7?me:l257<b32e:mh4?:%327?7em2d:=?4i;:k221<722c::84?::k237<72-;:?7?8b:l257<732c:;<4?:%327?70j2d:=?4>;:k235<72-;:?7?8b:l257<532c::k4?:%327?70j2d:=?4<;:k22`<72-;:?7?8b:l257<332c::i4?:%327?70j2d:=?4:;:k23d<72-;:?7?8b:l257<132c:;44?:%327?70j2d:=?48;:k23=<72-;:?7?8b:l257<?32c:;:4?:%327?70j2d:=?46;:k233<72-;:?7?8b:l257<f32c:;84?:%327?70j2d:=?4m;:k231<72-;:?7?8b:l257<d32c:;>4?:%327?70j2d:=?4k;:k22f<72-;:?7?8b:l257<b32c::o4?:%327?70j2d:=?4i;:k2<6<72-;:?7?7c:l257<732c:4?4?:%327?7?k2d:=?4>;:k2<4<72-;:?7?7c:l257<532c:4=4?:%327?7?k2d:=?4<;:k23c<72-;:?7?7c:l257<332c:;h4?:%327?7?k2d:=?4:;:k2<g<72-;:?7?7c:l257<132c:4l4?:%327?7?k2d:=?48;:k2<<<72-;:?7?7c:l257<?32c:454?:%327?7?k2d:=?46;:k2<2<72-;:?7?7c:l257<f32c:4;4?:%327?7?k2d:=?4m;:k2<0<72-;:?7?7c:l257<d32c:494?:%327?7?k2d:=?4k;:k23a<72-;:?7?7c:l257<b32c:;n4?:%327?7?k2d:=?4i;:k2g7<722e::l4?::`20d<7280;6=u+13g9e0=O9=30D<=>;nc7>5<<uk;?n7>51;294~"6:l0:??5G15;8L4563f;:<7>5;|`26c<721:1<7>t$00f>4733A;?56F>309Y02<bs8?1=;46:`823?7?2831=l4m:b8e>46=:90:n7sa8983?k?f291/m;4<;%c4>6=#i1087)o6:29'ed<43-ki6>5+ab80?!gc2:1/mh4;;%ce>0=#j90=7)l>:69'f7<43-h86>5+b580?!d22:1/n;4<;%`4>6=#j1087)l6:29'fd<43-hi6>5+bb80?!dc2:1/nh4<;%`e>6=#k9087)m>:29'g7<43-i86>5+c580?!e22:1/o;4<;%a4>6=#k1087)m6:29'gd<43-ii6>5+cb80?!ec2:1/oh4<;%ae>6=#l9087)j>:29'`7<43-n86>5+d580?!b22:1/h;4<;%f4>6=#l1087)j6:29'`d<43-ni6>5+db80?!bc2:1/hh4<;%fe>6=#m9087)k>:29'a7<43-o86>5+e580?!c22:1/i;4<;%g4>6=#m1087)k6:29'ad<43-oi6>5+eb80?!cc2:1/ih4=;%ge>7=#n90:<h5+107957b<,8;=69k4n034>44<f8;36<<4$001>47>3-;9?7?>9:&262<3=2.:>54>359'57d=:2.:>n4=;%370?73;2.:884>429m510=9;1e=995139'572=i:1b844?::k7e?6=3`k:6=44i`094?=n98k1<75f10`94?=n98i1<7F>2898m47c290C=?74;h32a?6=3`;:j7>5;h314?6=3`;9=7>5;h05>5<#9891>85a10094>=n:=0;6)?>3;06?k76:3;07d<<:18'545=:<1e=<<52:9j67<72-;:?7<:;o326?5<3`8m6=4+101960=i9881865f2d83>!76;38>7c?>2;78?l4c290/=<=5249m544=>21b>n4?:%327?423g;:>794;h0a>5<#9891>85a1009<>=n:h0;6)?>3;06?k76:3307d<6:18'545=:<1e=<<5a:9j6=<72-;:?7<:;o326?d<3`8<6=4+101960=i9881o65f2083>!76;38>7c?>2;f8?l55290/=<=5309m544=82B:>454i2294?"69:08=6`>1382?M75121b?84?:%327?533g;:>7>4H00:?>o4;3:1(<?<:268j475281C=?74;h1a>5<#9891?l5a10094>=n;00;6)?>3;1b?k76:3;07d=7:18'545=;h1e=<<52:9j72<72-;:?7=n;o326?5<3`>?6=4+10197d=i9881865f4283>!76;39j7c?>2;78?l25290/=<=53`9m544=>21b8<4?:%327?5f3g;:>794;h63>5<#9891?l5a1009<>=n;o0;6)?>3;1b?k76:3307d=j:18'545=;h1e=<<5a:9j7a<72-;:?7=n;o326?d<3`9h6=4+10197d=i9881o65f3783>!76;39j7c?>2;f8?l31290/=<=5549m544=821b994?:%327?323g;:>7?4;h70>5<#9891985a10096>=n=;0;6)?>3;76?k76:3907d;>:18'545==<1e=<<54:9j15<72-;:?7;:;o326?3<3`?m6=4+101910=i9881:65f5d83>!76;3?>7c?>2;58?l3c290/=<=5549m544=021b9n4?:%327?323g;:>774;h7a>5<#9891985a1009e>=n=h0;6)?>3;76?k76:3h07d;6:18'545==<1e=<<5c:9j1=<72-;:?7;:;o326?b<3`?<6=4+101910=i9881i65f4g83>!76;3?>7c?>2;d8?l00290/=<=5679m544=821b:84?:%327?013g;:>7?4;h47>5<#9891:;5a10096>=n>:0;6)?>3;45?k76:3907d8=:18'545=>?1e=<<54:9j24<72-;:?789;o326?3<3`=;6=4+101923=i9881:65f6g83>!76;3<=7c?>2;58?l0b290/=<=5679m544=021b:i4?:%327?013g;:>774;h4`>5<#9891:;5a1009e>=n>k0;6)?>3;45?k76:3h07d8n:18'545=>?1e=<<5c:9j2<<72-;:?789;o326?b<3`<36=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\ No newline at end of file
hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wb_fmc150_pkg.all;
use work.wb_stream_pkg.all;
entity wb_fmc150 is
generic
(
g_packet_size : natural := 32
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- Wishbone Streaming Interface Source
wbs_adr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
wbs_cyc_o : out std_logic;
wbs_stb_o : out std_logic;
wbs_we_o : out std_logic;
wbs_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
wbs_ack_i : in std_logic;
wbs_stall_i : in std_logic;
wbs_err_i : in std_logic;
wbs_rty_i : in std_logic
);
end wb_fmc150;
architecture rtl of wb_fmc150 is
-----------------------------------------------------------------------------------------------
-- IP / user logic interface signals
-----------------------------------------------------------------------------------------------
--signal s_adc_dout : std_logic_vector(31 downto 0);
--signal s_clk_adc : std_logic;
signal regs_in : t_fmc150_out_registers;
signal regs_out : t_fmc150_in_registers;
signal wbs_stream_out : t_wbs_source_out;
signal wbs_stream_in : t_wbs_source_in;
-- FMC 150 testbench
signal cdce_pll_status : std_logic;
signal s_mmcm_adc_locked : std_logic;
signal s_adc_dout : std_logic;
signal s_clk_adc : std_logic;
-- Streaming control signals
signal s_wbs_packet_counter : unsigned;
signal s_addr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal s_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal s_dvalid : std_logic;
signal s_sof : std_logic;
signal s_eof : std_logic;
signal s_error : std_logic;
signal s_bytesel : std_logic_vector((c_wbs_data_width/8)-1 downto 0);
signal s_dreq : std_logic;
begin
-- Glue logic
--adc_dout_o <= s_adc_dout;
--clk_adc_o <= s_clk_adc;
-----------------------------------------------------------------------------------------------
-- BUS / IP interface
-----------------------------------------------------------------------------------------------
--s_clk_out_pulse_sync(0) <= clk_100Mhz;
--gen_pulse_register_sync : for i in 0 to (C_SLV_DWIDTH/2)-1 generate
--
-- cmp_adc_delay_update : pulse2pulse
-- port map
-- (
-- in_clk => Bus2IP_Clk,
-- out_clk => s_clk_out_pulse_sync(i),
-- rst => not Bus2IP_Resetn,
-- pulsein => s_registers(FLAGS_PULSE_0)(i),
-- inbusy => open,
-- pulseout => s_pulse_register_sync(i)
-- );
--
--end generate;
--
--s_adc_delay_update <= s_pulse_register_sync(0);
cmp_fmc150_testbench: fmc150_testbench
port map
(
rst => rst,
clk_100Mhz => clk_100Mhz,
clk_200Mhz => clk_200Mhz,
adc_clk_ab_p => adc_clk_ab_p,
adc_clk_ab_n => adc_clk_ab_n,
adc_cha_p => adc_cha_p,
adc_cha_n => adc_cha_n,
adc_chb_p => adc_chb_p,
adc_chb_n => adc_chb_n,
dac_dclk_p => dac_dclk_p,
dac_dclk_n => dac_dclk_n,
dac_data_p => dac_data_p,
dac_data_n => dac_data_n,
dac_frame_p => dac_frame_p,
dac_frame_n => dac_frame_n,
txenable => txenable,
clk_to_fpga_p => clk_to_fpga_p,
clk_to_fpga_n => clk_to_fpga_n,
ext_trigger_p => ext_trigger_p,
ext_trigger_n => ext_trigger_n,
spi_sclk => spi_sclk,
spi_sdata => spi_sdata,
adc_n_en => adc_n_en,
adc_sdo => adc_sdo,
adc_reset => adc_reset,
cdce_n_en => cdce_n_en,
cdce_sdo => cdce_sdo,
cdce_n_reset => cdce_n_reset,
cdce_n_pd => cdce_n_pd,
ref_en => cdce_ref_en,
dac_n_en => dac_n_en,
dac_sdo => dac_sdo,
mon_n_en => mon_n_en,
mon_sdo => mon_sdo,
mon_n_reset => mon_n_reset,
mon_n_int => mon_n_int,
pll_status => cdce_pll_status,--regs_out.flgs_out_pll_status_i,
mmcm_adc_locked_o => s_mmcm_adc_locked,--regs_out.flgs_out_adc_clk_locked_i,
odata => regs_out.data_out_i,--s_odata,
busy => regs_out.flgs_out_spi_busy_i,--s_busy,
prsnt_m2c_l => regs_out.flgs_out_fmc_prst_i,--prsnt_m2c_l,
rd_n_wr => regs_in.flgs_in_spi_rw_o, --s_registers(FLAGS_IN_0)(FLAGS_IN_0_SPI_RW),
addr => regs_in.addr_o, --s_registers(ADDR)(15 downto 0),
idata => regs_in.data_in_o, --s_registers(DATAIN),
cdce72010_valid => regs_in.cs_cdce72010_o,--s_registers(CHIPSELECT)(CHIPSELECT_CDCE72010),
ads62p49_valid => regs_in.cs_ads62p49_o, --s_registers(CHIPSELECT)(CHIPSELECT_ADS62P49),
dac3283_valid => regs_in.cs_dac3283_o, --s_registers(CHIPSELECT)(CHIPSELECT_DAC3283),
amc7823_valid => regs_in.cs_amc7823_o, --s_registers(CHIPSELECT)(CHIPSELECT_AMC7823),
external_clock => regs_in.flgs_in_ext_clk_o, --s_registers(FLAGS_IN_0)(FLAGS_IN_0_EXTERNAL_CLOCK),
adc_delay_update_i => regs_in.flgs_pulse_o,--s_adc_delay_update,
adc_str_cntvaluein_i => regs_in.adc_dly_str_o,--s_registers(ADC_DELAY)(4 downto 0),
adc_cha_cntvaluein_i => regs_in.adc_dly_cha_o,--s_registers(ADC_DELAY)(12 downto 8),
adc_chb_cntvaluein_i => regs_in.adc_dly_chb_o,--s_registers(ADC_DELAY)(20 downto 16),
adc_str_cntvalueout_o => open,
adc_dout_o => s_adc_dout,
clk_adc_o => s_clk_adc
);
regs_out.flgs_out_pll_status_i <= cdce_pll_status;
regs_out.flgs_out_adc_clk_locked_i <= s_mmcm_adc_locked;
cmp_wb_fmc150_port : wb_fmc150_port
port map (
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
wb_stall_o => wb_stall_o,
clk_100Mhz => clk_100_i,
regs_i => regs_out,
regs_o => regs_in
);
cmp_wb_source_if : xwb_stream_source
port map(
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
-- Wishbone Fabric Interface I/O
src_i => wbs_stream_in,
src_o => wbs_stream_out,
-- Decoded & buffered logic
addr_i => s_addr,
data_i => s_data,
dvalid_i => s_dvalid,
sof_i => s_sof,
eof_i => s_eof,
error_i => s_error,
bytesel_i => s_bytesel,
dreq_o => s_dreq
);
s_addr <= (others => '0');
s_data <= s_adc_dout;
s_dvalid <= cdce_pll_status and s_mmcm_adc_locked;
p_gen_sof_eof : process(s_clk_adc, rst_n_i)
begin
if rst_n_i = '0' then
s_sof <= '0';
s_eof <= '0';
s_wbs_packet_counter <= 0;
elsif rising_edge(s_clk_adc) then
-- Defaults assignments
s_sof <= '0';
s_eof <= '0';
-- Finish current transaction
if(s_wbs_packet_counter = g_packet_size) then
s_eof <= '1';
s_wbs_packet_counter <= 0;
elsif (s_wbs_packet_counter = 0) then
s_sof <= '1';
end if;
-- Increment counter if data is valid
if s_dvalid then
s_wbs_packet_counter <= s_wbs_packet_counter + 1;
end if;
end if;
end process;
s_error <= '0';
bytesel_i <= (others => '1');
wbs_adr_o <= wbs_stream_out.adr;
wbs_dat_o <= wbs_stream_out.dat;
wbs_cyc_o <= wbs_stream_out.cyc;
wbs_stb_o <= wbs_stream_out.cyc;
wbs_we_o <= wbs_stream_out.we;
wbs_sel_o <= wbs_stream_out.sel;
wbs_stream_in.ack <= wbs_ack_i;
wbs_stream_in.stall <= wbs_stall_i;
wbs_stream_in.err <= wbs_err_i;
wbs_stream_in.rty <= wbs_rty_i;
end rtl;
hdl/modules/custom_wishbone/wb_fmc150/wb_fmc150_port.vhd 0 → 100644
View file @ c9217ac1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC/DAC interface registers
---------------------------------------------------------------------------------------
-- File : wb_fmc150_port.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Mon Oct 1 15:20:18 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.fmc150_wbgen2_pkg.all;
entity wb_fmc150_port is
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
clk_100Mhz : in std_logic;
regs_i : in t_fmc150_in_registers;
regs_o : out t_fmc150_out_registers
);
end wb_fmc150_port;
architecture syn of wb_fmc150_port is
signal fmc150_flgs_pulse_int : std_logic ;
signal fmc150_flgs_pulse_int_delay : std_logic ;
signal fmc150_flgs_pulse_sync0 : std_logic ;
signal fmc150_flgs_pulse_sync1 : std_logic ;
signal fmc150_flgs_pulse_sync2 : std_logic ;
signal fmc150_flgs_in_spi_rw_int : std_logic ;
signal fmc150_flgs_in_ext_clk_int : std_logic ;
signal fmc150_addr_int : std_logic_vector(15 downto 0);
signal fmc150_data_in_int : std_logic_vector(31 downto 0);
signal fmc150_cs_cdce72010_int : std_logic ;
signal fmc150_cs_ads62p49_int : std_logic ;
signal fmc150_cs_dac3283_int : std_logic ;
signal fmc150_cs_amc7823_int : std_logic ;
signal fmc150_adc_dly_str_int : std_logic_vector(4 downto 0);
signal fmc150_adc_dly_cha_int : std_logic_vector(4 downto 0);
signal fmc150_adc_dly_chb_int : std_logic_vector(4 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(2 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
fmc150_flgs_pulse_int <= '0';
fmc150_flgs_pulse_int_delay <= '0';
fmc150_flgs_in_spi_rw_int <= '0';
fmc150_flgs_in_ext_clk_int <= '0';
fmc150_addr_int <= "0000000000000000";
fmc150_data_in_int <= "00000000000000000000000000000000";
fmc150_cs_cdce72010_int <= '0';
fmc150_cs_ads62p49_int <= '0';
fmc150_cs_dac3283_int <= '0';
fmc150_cs_amc7823_int <= '0';
fmc150_adc_dly_str_int <= "00000";
fmc150_adc_dly_cha_int <= "00000";
fmc150_adc_dly_chb_int <= "00000";
elsif rising_edge(clk_sys_i) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
ack_in_progress <= '0';
else
fmc150_flgs_pulse_int <= fmc150_flgs_pulse_int_delay;
fmc150_flgs_pulse_int_delay <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(2 downto 0) is
when "000" =>
if (wb_we_i = '1') then
fmc150_flgs_pulse_int <= wrdata_reg(0);
fmc150_flgs_pulse_int_delay <= wrdata_reg(0);
end if;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(4) <= '1';
ack_in_progress <= '1';
when "001" =>
if (wb_we_i = '1') then
fmc150_flgs_in_spi_rw_int <= wrdata_reg(0);
fmc150_flgs_in_ext_clk_int <= wrdata_reg(1);
end if;
rddata_reg(0) <= fmc150_flgs_in_spi_rw_int;
rddata_reg(1) <= fmc150_flgs_in_ext_clk_int;
rddata_reg(2) <= 'X';
rddata_reg(3) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "010" =>
if (wb_we_i = '1') then
fmc150_addr_int <= wrdata_reg(15 downto 0);
end if;
rddata_reg(15 downto 0) <= fmc150_addr_int;
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "011" =>
if (wb_we_i = '1') then
fmc150_data_in_int <= wrdata_reg(31 downto 0);
end if;
rddata_reg(31 downto 0) <= fmc150_data_in_int;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "100" =>
if (wb_we_i = '1') then
fmc150_cs_cdce72010_int <= wrdata_reg(0);
fmc150_cs_ads62p49_int <= wrdata_reg(1);
fmc150_cs_dac3283_int <= wrdata_reg(2);
fmc150_cs_amc7823_int <= wrdata_reg(3);
end if;
rddata_reg(0) <= fmc150_cs_cdce72010_int;
rddata_reg(1) <= fmc150_cs_ads62p49_int;
rddata_reg(2) <= fmc150_cs_dac3283_int;
rddata_reg(3) <= fmc150_cs_amc7823_int;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "101" =>
if (wb_we_i = '1') then
fmc150_adc_dly_str_int <= wrdata_reg(4 downto 0);
fmc150_adc_dly_cha_int <= wrdata_reg(12 downto 8);
fmc150_adc_dly_chb_int <= wrdata_reg(20 downto 16);
end if;
rddata_reg(4 downto 0) <= fmc150_adc_dly_str_int;
rddata_reg(12 downto 8) <= fmc150_adc_dly_cha_int;
rddata_reg(20 downto 16) <= fmc150_adc_dly_chb_int;
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "110" =>
if (wb_we_i = '1') then
end if;
rddata_reg(31 downto 0) <= regs_i.data_out_i;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "111" =>
if (wb_we_i = '1') then
end if;
rddata_reg(0) <= regs_i.flgs_out_spi_busy_i;
rddata_reg(1) <= regs_i.flgs_out_pll_status_i;
rddata_reg(2) <= regs_i.flgs_out_adc_clk_locked_i;
rddata_reg(3) <= regs_i.flgs_out_fmc_prst_i;
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
rddata_reg(12) <= 'X';
rddata_reg(13) <= 'X';
rddata_reg(14) <= 'X';
rddata_reg(15) <= 'X';
rddata_reg(16) <= 'X';
rddata_reg(17) <= 'X';
rddata_reg(18) <= 'X';
rddata_reg(19) <= 'X';
rddata_reg(20) <= 'X';
rddata_reg(21) <= 'X';
rddata_reg(22) <= 'X';
rddata_reg(23) <= 'X';
rddata_reg(24) <= 'X';
rddata_reg(25) <= 'X';
rddata_reg(26) <= 'X';
rddata_reg(27) <= 'X';
rddata_reg(28) <= 'X';
rddata_reg(29) <= 'X';
rddata_reg(30) <= 'X';
rddata_reg(31) <= 'X';
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_dat_o <= rddata_reg;
-- Update ADC delay
process (clk_100Mhz, rst_n_i)
begin
if (rst_n_i = '0') then
regs_o.flgs_pulse_o <= '0';
fmc150_flgs_pulse_sync0 <= '0';
fmc150_flgs_pulse_sync1 <= '0';
fmc150_flgs_pulse_sync2 <= '0';
elsif rising_edge(clk_100Mhz) then
fmc150_flgs_pulse_sync0 <= fmc150_flgs_pulse_int;
fmc150_flgs_pulse_sync1 <= fmc150_flgs_pulse_sync0;
fmc150_flgs_pulse_sync2 <= fmc150_flgs_pulse_sync1;
regs_o.flgs_pulse_o <= fmc150_flgs_pulse_sync2 and (not fmc150_flgs_pulse_sync1);
end if;
end process;
-- SPI Read/Write flag
regs_o.flgs_in_spi_rw_o <= fmc150_flgs_in_spi_rw_int;
-- External Clock for ADC
regs_o.flgs_in_ext_clk_o <= fmc150_flgs_in_ext_clk_int;
-- SPI address
regs_o.addr_o <= fmc150_addr_int;
-- Data In for FMC150
regs_o.data_in_o <= fmc150_data_in_int;
-- Chipselect for cdce72010
regs_o.cs_cdce72010_o <= fmc150_cs_cdce72010_int;
-- Chipselect for ads62p49
regs_o.cs_ads62p49_o <= fmc150_cs_ads62p49_int;
-- Chipselect for dac3283
regs_o.cs_dac3283_o <= fmc150_cs_dac3283_int;
-- Chipselect for amc7823
regs_o.cs_amc7823_o <= fmc150_cs_amc7823_int;
-- ADC Strobe delay
regs_o.adc_dly_str_o <= fmc150_adc_dly_str_int;
-- ADC Channel A delay
regs_o.adc_dly_cha_o <= fmc150_adc_dly_cha_int;
-- ADC Strobe delay
regs_o.adc_dly_chb_o <= fmc150_adc_dly_chb_int;
-- Data out from FMC150
-- SPI Busy
-- CDCE72010 PLL Status
-- FPGA ADC clock locked
-- FMC present
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
hdl/modules/custom_wishbone/wb_fmc150/xfmc150.wb 0 → 100644
View file @ c9217ac1
-- Description of the wishbone interface for the wb_dma_interface core
peripheral {
name = "FMC ADC/DAC interface registers";
description = "FMC ADC/DAC interface";
-- Prefix for all generated ports
prefix = "fmc150";
-- Name of the vhdl entity to be generated
hdl_entity = "wb_fmc150_port";
-- Flags Pulse
reg {
name = "Input Flags for Pulsing Registers";
prefix = "flgs_pulse";
field {
name = "Update ADC delay";
description = "write 1: pulse ADC delay register.\
write 0: no effect";
--prefix = "start";
-- Pulse to start
type = MONOSTABLE;
clock = "clk_100Mhz";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Input Flags
reg {
name = "Input Flags for FMC150";
prefix = "flgs_in";
field {
name = "SPI Read/Write flag";
description = "write 1: write to SPI. \
write 0: read from SPI";
prefix = "spi_rw";
type = BIT;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "External Clock for ADC";
description = "write 1: external clock for ADC. \
write 0: internal clock for ADC";
prefix = "ext_clk";
type = BIT;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Address
reg {
name = "Address for Chips on FMC150";
prefix = "addr";
field {
name = "SPI address";
description = "Address of internal register";
--prefix = "addr";
type = SLV;
size = 16;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Data In
reg {
name = "Data In for Chips on FMC150";
prefix = "data_in";
field {
name = "Data In for FMC150";
description = "Data to internal chip register";
--prefix = "data";
type = SLV;
size = 32;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Chipselect
reg {
name = "Chipselect for Chips on FMC150";
prefix = "cs";
field {
name = "Chipselect for cdce72010";
description = "write 1: select chip cdce72010 for operation.\
write 0: no effect";
prefix = "cdce72010";
type = BIT;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Chipselect for ads62p49";
description = "write 1: select chip ads62p49 for operation.\
write 0: no effect";
prefix = "ads62p49";
type = BIT;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Chipselect for dac3283";
description = "write 1: select chip dac3283 for operation.\
write 0: no effect";
prefix = "dac3283";
type = BIT;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Chipselect for amc7823";
description = "write 1: select chip amc7823 for operation.\
write 0: no effect";
prefix = "amc7823";
type = BIT;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- ADC delay
reg {
name = "ADC Delay";
prefix = "adc_dly";
field {
name = "ADC Strobe delay";
description = "write the strobe delay";
prefix = "str";
type = SLV;
size = 5;
align = 8;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADC Channel A delay";
description = "write the channel A delay";
prefix = "cha";
type = SLV;
size = 5;
align = 8;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "ADC Strobe delay";
description = "write the channel B delay";
prefix = "chb";
type = SLV;
size = 5;
align = 8;
--clock = "";
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- Data Out
reg {
name = "Data Out From Chips on FMC150";
prefix = "data_out";
field {
name = "Data out from FMC150";
description = "Data from internal chip register";
--prefix = "data";
type = SLV;
size = 32;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
-- Flags out
reg {
name = "Flags out from Chips on FMC150";
prefix = "flgs_out";
field {
name = "SPI Busy";
description = "read 1: spi busy.\
read 0: spi idle";
prefix = "spi_busy";
type = BIT;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "CDCE72010 PLL Status";
description = "read 1: PLL locked.\
read 0: PLL not locked";
prefix = "pll_status";
type = BIT;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FPGA ADC clock locked";
description = "read 1: FPGA ADC PLL locked.\
read 0: FPGA ADC PLL not locked";
prefix = "adc_clk_locked";
type = BIT;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "FMC present";
description = "read 1: FMC present.\
read 0: FMC not present";
prefix = "fmc_prst";
type = BIT;
--clock = "";
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
};
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_pkg.vhd 0 → 100644
View file @ c9217ac1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for FMC ADC/DAC interface registers
---------------------------------------------------------------------------------------
-- File : xfmc150_regs_pkg.vhd
-- Author : auto-generated by wbgen2 from xfmc150.wb
-- Created : Mon Oct 1 15:20:18 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package fmc150_wbgen2_pkg is
-- Input registers (user design -> WB slave)
type t_fmc150_in_registers is record
data_out_i : std_logic_vector(31 downto 0);
flgs_out_spi_busy_i : std_logic;
flgs_out_pll_status_i : std_logic;
flgs_out_adc_clk_locked_i : std_logic;
flgs_out_fmc_prst_i : std_logic;
end record;
constant c_fmc150_in_registers_init_value: t_fmc150_in_registers := (
data_out_i => (others => '0'),
flgs_out_spi_busy_i => '0',
flgs_out_pll_status_i => '0',
flgs_out_adc_clk_locked_i => '0',
flgs_out_fmc_prst_i => '0'
);
-- Output registers (WB slave -> user design)
type t_fmc150_out_registers is record
flgs_pulse_o : std_logic;
flgs_in_spi_rw_o : std_logic;
flgs_in_ext_clk_o : std_logic;
addr_o : std_logic_vector(15 downto 0);
data_in_o : std_logic_vector(31 downto 0);
cs_cdce72010_o : std_logic;
cs_ads62p49_o : std_logic;
cs_dac3283_o : std_logic;
cs_amc7823_o : std_logic;
adc_dly_str_o : std_logic_vector(4 downto 0);
adc_dly_cha_o : std_logic_vector(4 downto 0);
adc_dly_chb_o : std_logic_vector(4 downto 0);
end record;
constant c_fmc150_out_registers_init_value: t_fmc150_out_registers := (
flgs_pulse_o => '0',
flgs_in_spi_rw_o => '0',
flgs_in_ext_clk_o => '0',
addr_o => (others => '0'),
data_in_o => (others => '0'),
cs_cdce72010_o => '0',
cs_ads62p49_o => '0',
cs_dac3283_o => '0',
cs_amc7823_o => '0',
adc_dly_str_o => (others => '0'),
adc_dly_cha_o => (others => '0'),
adc_dly_chb_o => (others => '0')
);
function "or" (left, right: t_fmc150_in_registers) return t_fmc150_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
end package;
package body fmc150_wbgen2_pkg is
function f_x_to_zero (x:std_logic) return std_logic is
begin
if(x = 'X' or x = 'U') then
return '0';
else
return x;
end if;
end function;
function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
variable tmp: std_logic_vector(x'length-1 downto 0);
begin
for i in 0 to x'length-1 loop
if(x(i) = 'X' or x(i) = 'U') then
tmp(i):= '0';
else
tmp(i):=x(i);
end if;
end loop;
return tmp;
end function;
function "or" (left, right: t_fmc150_in_registers) return t_fmc150_in_registers is
variable tmp: t_fmc150_in_registers;
begin
tmp.data_out_i := f_x_to_zero(left.data_out_i) or f_x_to_zero(right.data_out_i);
tmp.flgs_out_spi_busy_i := f_x_to_zero(left.flgs_out_spi_busy_i) or f_x_to_zero(right.flgs_out_spi_busy_i);
tmp.flgs_out_pll_status_i := f_x_to_zero(left.flgs_out_pll_status_i) or f_x_to_zero(right.flgs_out_pll_status_i);
tmp.flgs_out_adc_clk_locked_i := f_x_to_zero(left.flgs_out_adc_clk_locked_i) or f_x_to_zero(right.flgs_out_adc_clk_locked_i);
tmp.flgs_out_fmc_prst_i := f_x_to_zero(left.flgs_out_fmc_prst_i) or f_x_to_zero(right.flgs_out_fmc_prst_i);
return tmp;
end function;
end package body;
hdl/modules/custom_wishbone/wb_fmc150/xfmc150_regs_regs.h 0 → 100644
View file @ c9217ac1
/*
Register definitions for slave core: FMC ADC/DAC interface registers
* File : xfmc150_regs_regs.h
* Author : auto-generated by wbgen2 from xfmc150.wb
* Created : Mon Oct 1 15:20:18 2012
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE xfmc150.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_XFMC150_WB
#define __WBGEN2_REGDEFS_XFMC150_WB
#include <inttypes.h>
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Input Flags for Pulsing Registers */
/* definitions for register: Input Flags for FMC150 */
/* definitions for field: SPI Read/Write flag in reg: Input Flags for FMC150 */
#define FMC150_FLGS_IN_SPI_RW WBGEN2_GEN_MASK(0, 1)
/* definitions for field: External Clock for ADC in reg: Input Flags for FMC150 */
#define FMC150_FLGS_IN_EXT_CLK WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Address for Chips on FMC150 */
/* definitions for register: Data In for Chips on FMC150 */
/* definitions for register: Chipselect for Chips on FMC150 */
/* definitions for field: Chipselect for cdce72010 in reg: Chipselect for Chips on FMC150 */
#define FMC150_CS_CDCE72010 WBGEN2_GEN_MASK(0, 1)
/* definitions for field: Chipselect for ads62p49 in reg: Chipselect for Chips on FMC150 */
#define FMC150_CS_ADS62P49 WBGEN2_GEN_MASK(1, 1)
/* definitions for field: Chipselect for dac3283 in reg: Chipselect for Chips on FMC150 */
#define FMC150_CS_DAC3283 WBGEN2_GEN_MASK(2, 1)
/* definitions for field: Chipselect for amc7823 in reg: Chipselect for Chips on FMC150 */
#define FMC150_CS_AMC7823 WBGEN2_GEN_MASK(3, 1)
/* definitions for register: ADC Delay */
/* definitions for field: ADC Strobe delay in reg: ADC Delay */
#define FMC150_ADC_DLY_STR_MASK WBGEN2_GEN_MASK(0, 5)
#define FMC150_ADC_DLY_STR_SHIFT 0
#define FMC150_ADC_DLY_STR_W(value) WBGEN2_GEN_WRITE(value, 0, 5)
#define FMC150_ADC_DLY_STR_R(reg) WBGEN2_GEN_READ(reg, 0, 5)
/* definitions for field: ADC Channel A delay in reg: ADC Delay */
#define FMC150_ADC_DLY_CHA_MASK WBGEN2_GEN_MASK(8, 5)
#define FMC150_ADC_DLY_CHA_SHIFT 8
#define FMC150_ADC_DLY_CHA_W(value) WBGEN2_GEN_WRITE(value, 8, 5)
#define FMC150_ADC_DLY_CHA_R(reg) WBGEN2_GEN_READ(reg, 8, 5)
/* definitions for field: ADC Strobe delay in reg: ADC Delay */
#define FMC150_ADC_DLY_CHB_MASK WBGEN2_GEN_MASK(16, 5)
#define FMC150_ADC_DLY_CHB_SHIFT 16
#define FMC150_ADC_DLY_CHB_W(value) WBGEN2_GEN_WRITE(value, 16, 5)
#define FMC150_ADC_DLY_CHB_R(reg) WBGEN2_GEN_READ(reg, 16, 5)
/* definitions for register: Data Out From Chips on FMC150 */
/* definitions for register: Flags out from Chips on FMC150 */
/* definitions for field: SPI Busy in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_SPI_BUSY WBGEN2_GEN_MASK(0, 1)
/* definitions for field: CDCE72010 PLL Status in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_PLL_STATUS WBGEN2_GEN_MASK(1, 1)
/* definitions for field: FPGA ADC clock locked in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_ADC_CLK_LOCKED WBGEN2_GEN_MASK(2, 1)
/* definitions for field: FMC present in reg: Flags out from Chips on FMC150 */
#define FMC150_FLGS_OUT_FMC_PRST WBGEN2_GEN_MASK(3, 1)
PACKED struct FMC150_WB {
/* [0x0]: REG Input Flags for Pulsing Registers */
uint32_t FLGS_PULSE;
/* [0x4]: REG Input Flags for FMC150 */
uint32_t FLGS_IN;
/* [0x8]: REG Address for Chips on FMC150 */
uint32_t ADDR;
/* [0xc]: REG Data In for Chips on FMC150 */
uint32_t DATA_IN;
/* [0x10]: REG Chipselect for Chips on FMC150 */
uint32_t CS;
/* [0x14]: REG ADC Delay */
uint32_t ADC_DLY;
/* [0x18]: REG Data Out From Chips on FMC150 */
uint32_t DATA_OUT;
/* [0x1c]: REG Flags out from Chips on FMC150 */
uint32_t FLGS_OUT;
};
#endif
hdl/modules/custom_wishbone/wb_fmc150/xwb_fmc150.vhd 0 → 100755
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wb_fmc150_pkg.all;
use work.wb_stream_pkg.all;
entity wb_fmc150 is
generic
(
g_packet_size : natural := 32
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_slv_i : t_wishbone_slave_in;
wb_slv_o : t_wishbone_slave_out;
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- Wishbone Streaming Interface Source
wbs_source_i : t_wbs_source_in;
wbs_source_o : t_wbs_source_out;
);
end wb_fmc150;
architecture rtl of wb_fmc150 is
component wb_fmc150
generic
(
g_packet_size : natural := 32
);
port
(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
clk_100Mhz_i : in std_logic;
clk_200Mhz_i : in std_logic;
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := (others => '0');
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := (others => '0');
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := (others => '0');
wb_we_i : in std_logic := '0';
wb_cyc_i : in std_logic := '0';
wb_stb_i : in std_logic := '0';
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_rty_o : out std_logic;
wb_stall_o : out std_logic;
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i : in std_logic;
adc_clk_ab_n_i : in std_logic;
adc_cha_p_i : in std_logic_vector(6 downto 0);
adc_cha_n_i : in std_logic_vector(6 downto 0);
adc_chb_p_i : in std_logic_vector(6 downto 0);
adc_chb_n_i : in std_logic_vector(6 downto 0);
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o : out std_logic;
dac_dclk_n_o : out std_logic;
dac_data_p_o : out std_logic_vector(7 downto 0);
dac_data_n_o : out std_logic_vector(7 downto 0);
dac_frame_p_o : out std_logic;
dac_frame_n_o : out std_logic;
txenable_o : out std_logic;
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i : in std_logic;
clk_to_fpga_n_i : in std_logic;
ext_trigger_p_i : in std_logic;
ext_trigger_n_i : in std_logic;
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o : out std_logic; -- Shared SPI clock line
spi_sdata_o : out std_logic; -- Shared SPI data line
-- ADC specific signals
adc_n_en_o : out std_logic; -- SPI chip select
adc_sdo_i : in std_logic; -- SPI data out
adc_reset_o : out std_logic; -- SPI reset
-- CDCE specific signals
cdce_n_en_o : out std_logic; -- SPI chip select
cdce_sdo_i : in std_logic; -- SPI data out
cdce_n_reset_o : out std_logic;
cdce_n_pd_o : out std_logic;
cdce_ref_en_o : out std_logic;
cdce_pll_status_i : in std_logic;
-- DAC specific signals
dac_n_en_o : out std_logic; -- SPI chip select
dac_sdo_i : in std_logic; -- SPI data out
-- Monitoring specific signals
mon_n_en_o : out std_logic; -- SPI chip select
mon_sdo_i : in std_logic; -- SPI data out
mon_n_reset_o : out std_logic;
mon_n_int_i : in std_logic;
--FMC Present status
prsnt_m2c_l_i : in std_logic;
-- Wishbone Streaming Interface Source
wbs_adr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
wbs_dat_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
wbs_cyc_o : out std_logic;
wbs_stb_o : out std_logic;
wbs_we_o : out std_logic;
wbs_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
wbs_ack_i : in std_logic;
wbs_stall_i : in std_logic;
wbs_err_i : in std_logic;
wbs_rty_i : in std_logic
);
end component;
begin
cmp_wb_fmc150 : wb_fmc150
generic map
(
g_packet_size => g_packet_size
);
port
(
rst_n_i => rst_n_i,
clk_sys_i => clk_sys_i,
clk_100Mhz_i => clk_100Mhz_i,
clk_200Mhz_i => clk_200Mhz_i,
-----------------------------
-- Wishbone signals
-----------------------------
wb_adr_i => wb_adr_i,
wb_dat_i => wb_dat_i,
wb_dat_o => wb_dat_o,
wb_sel_i => wb_sel_i,
wb_we_i => wb_we_i,
wb_cyc_i => wb_cyc_i,
wb_stb_i => wb_stb_i,
wb_ack_o => wb_ack_o,
wb_err_o => wb_err_o,
wb_rty_o => wb_rty_o,
wb_stall_o => wb_stall_o,
-----------------------------
-- External ports
-----------------------------
--Clock/Data connection to ADC on FMC150 (ADS62P49)
adc_clk_ab_p_i => adc_clk_ab_p_i,
adc_clk_ab_n_i => adc_clk_ab_n_i,
adc_cha_p_i => adc_cha_p_i,
adc_cha_n_i => adc_cha_n_i,
adc_chb_p_i => adc_chb_p_i,
adc_chb_n_i => adc_chb_n_i,
--Clock/Data connection to DAC on FMC150 (DAC3283)
dac_dclk_p_o => dac_dclk_p_o,
dac_dclk_n_o => dac_dclk_n_o,
dac_data_p_o => dac_data_p_o,
dac_data_n_o => dac_data_n_o,
dac_frame_p_o => dac_frame_p_o,
dac_frame_n_o => dac_frame_n_o,
txenable_o => txenable_o,
--Clock/Trigger connection to FMC150
clk_to_fpga_p_i => clk_to_fpga_p_i,
clk_to_fpga_n_i => clk_to_fpga_n_i,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
-- Control signals from/to FMC150
--Serial Peripheral Interface (SPI)
spi_sclk_o => spi_sclk_o, -- Shared SPI clock line
spi_sdata_o => spi_sdata_o, -- Shared SPI data line
-- ADC specific signals
adc_n_en_o => adc_n_en_o -- SPI chip select
adc_sdo_i => adc_sdo_i -- SPI data out
adc_reset_o => adc_reset_o -- SPI reset
-- CDCE specific signals
cdce_n_en_o => cdce_n_en_o -- SPI chip select
cdce_sdo_i => cdce_sdo_i -- SPI data out
cdce_n_reset_o => cdce_n_reset_o
cdce_n_pd_o => cdce_n_pd_o
cdce_ref_en_o => cdce_ref_en_o
cdce_pll_status_i => cdce_pll_status_i
-- DAC specific signals
dac_n_en_o => dac_n_en_o,-- SPI chip select
dac_sdo_i => dac_sdo_i, -- SPI data out
-- Monitoring specific signals
mon_n_en_o => mon_n_en_o, -- SPI chip select
mon_sdo_i => mon_sdo_i, -- SPI data out
mon_n_reset_o => mon_n_reset_o,
mon_n_int_i => mon_n_int_i,
--FMC Present status
prsnt_m2c_l_i => prsnt_m2c_l_i,
-- Wishbone Streaming Interface Source
wbs_adr_o => wbs_adr_o,
wbs_dat_o => wbs_dat_o,
wbs_cyc_o => wbs_cyc_o,
wbs_stb_o => wbs_stb_o,
wbs_we_o => wbs_we_o,
wbs_sel_o => wbs_sel_o,
wbs_ack_i => wbs_ack_i,
wbs_stall_i => wbs_stall_i,
wbs_err_i => wbs_err_i,
wbs_rty_i => wbs_rty_i
);
end component;
wbs_source_i.ack <= wbs_ack_i;
wbs_source_i.stall <= wbs_stall_i;
wbs_source_i.err <= wbs_err_i;
wbs_source_i.rty <= wbs_rty_i;
wbs_source_o.adr <= wbs_adr_o;
wbs_source_o.dat <= wbs_dat_o;
wbs_source_o.cyc <= wbs_cyc_o;
wbs_source_o.stb <= wbs_stb_o;
wbs_source_o.we <= wbs_we_o;
wbs_source_o.sel <= wbs_sel_o;
wb_slave_i.cyc <= wb_cyc_i;
wb_slave_i.stb <= wb_stb_i;
wb_slave_i.adr <= wb_adr_i;
wb_slave_i.sel <= wb_sel_i;
wb_slave_i.we <= wb_we_i;
wb_slave_i.dat <= wb_dat_i;
wb_slave_o.ack <= wb_ack_o;
wb_slave_o.err <= wb_err_o;
wb_slave_o.rty <= wb_rty_o;
wb_slave_o.stall <= wb_stall_o;
wb_slave_o.int <= '0';
wb_slave_o.dat <= wb_dat_o;
end rtl;
hdl/modules/custom_wishbone/wb_irq_mngr/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["xwb_irq_mngr.vhd", "wb_irq_mngr.vhd"]
hdl/modules/custom_wishbone/wb_irq_mngr/wb_irq_mngr.vhd 0 → 100755
View file @ c9217ac1
-- Simple IRQ Manager
-- Based on the original design by:
--
-- Fabrice Mousset (fabrice.mousset@laposte.net)
-- Project : Wishbone Interruption Manager (ARMadeus wishbone example)
-- See: http://www.armadeus.com/wiki/index.php?title=A_simple_design_with_Wishbone_bus
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
entity wb_irq_mngr is
generic(
g_irq_count : integer := 16;
g_irq_level : std_logic := '1';
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- Global Signals
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone interface signals
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
--slave_i : in t_wishbone_slave_in;
--slave_o : out t_wishbone_slave_out;
-- irq from other IP
irq_req_i : in std_logic_vector(g_irq_count-1 downto 0);
-- Component external signals
irq_req_o : out std_logic
);
end wb_irq_mngr;
architecture rtl of wb_irq_mngr is
-- Read/Write regs
constant c_IRQ_REG_MASK : std_logic_vector(2 downto 0) := "000"; -- *reg* IRQ mask
constant c_IRQ_REG_ACK : std_logic_vector(2 downto 0) := "001"; -- *reg* IRQ acknowledge from master
-- Read regs
constant c_IRQ_REG_PEND : std_logic_vector(2 downto 0) := "010"; -- *reg* IRQ pending
-- Slave Wishbone structs
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
-- IRQ signals
signal irq_r : std_logic_vector(g_irq_count-1 downto 0);
signal irq_old : std_logic_vector(g_irq_count-1 downto 0);
signal irq_pend : std_logic_vector(g_irq_count-1 downto 0);
signal irq_ack : std_logic_vector(g_irq_count-1 downto 0);
signal irq_mask : std_logic_vector(g_irq_count-1 downto 0);
signal readdata : std_logic_vector(c_wishbone_data_width-1 downto 0);
signal rd_ack : std_logic;
signal wr_ack : std_logic;
signal sel : std_logic;
begin
-- External signals synchronization process
gen_sync_ff : for i in 0 to g_irq_count-1 generate
cmp_input_sync : gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
rst_n_i => rst_n_i,
clk_i => clk_sys_i,
data_i => irq_req_i(i),
synced_o => irq_old(i),
ppulse_o => irq_r(i));
end generate gen_sync_ff;
-- Simple sel bus aggregate
sel <= '1' when (unsigned(not wb_in.sel) = 0) else '0';
-- Slave adapter for granularity (byte, word) and interface mode (classic, pipelined)
cmp_slv_adapter : wb_slave_adapter
generic map (
g_master_use_struct => true,
g_master_mode => CLASSIC,
g_master_granularity => WORD,
g_slave_use_struct => false,
g_slave_mode => g_interface_mode,
g_slave_granularity => g_address_granularity)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
master_i => wb_out,
master_o => wb_in,
sl_adr_i => wb_adr_i,
sl_dat_i => wb_dat_i,
sl_sel_i => wb_sel_i,
sl_cyc_i => wb_cyc_i,
sl_stb_i => wb_stb_i,
sl_we_i => wb_we_i,
sl_dat_o => wb_dat_o,
sl_ack_o => wb_ack_o,
sl_stall_o => wb_stall_o
);
----------------------------------------------------------------------------
-- Interruption requests latching process on rising edge
----------------------------------------------------------------------------
p_int_req : process(clk_sys_i, rst_n_i)
begin
if(rst_n_i = '0') then
irq_pend <= (others => '0');
elsif rising_edge(clk_sys_i) then
irq_pend <= (irq_pend or (irq_r and irq_mask)) and (not irq_ack);
end if;
end process p_int_req;
----------------------------------------------------------------------------
-- Register reading process
----------------------------------------------------------------------------
p_read_reg : process(clk_sys_i, rst_n_i)
begin
if(rst_n_i = '0') then
rd_ack <= '0';
readdata <= (others => '0');
elsif rising_edge(clk_sys_i) then
rd_ack <= '0';
-- WB READ classic cycle
if(wb_in.stb = '1' and wb_in.we = '0' and wb_in.cyc = '1') then
rd_ack <= '1';
-- Decode address (partial decoding only). Word granularity.
if(wb_in.adr(4 downto 2) = c_IRQ_REG_MASK) then
readdata(g_irq_count-1 downto 0) <= irq_mask;
elsif(wb_in.adr(4 downto 2) = c_IRQ_REG_PEND) then
readdata(g_irq_count-1 downto 0) <= irq_pend;
--elsif(wbs_s1_address="10") then
--readdata <= std_logic_vector(to_unsigned(id,16));
else
readdata <= (others => '0');
end if;
end if;
end if;
end process p_read_reg;
----------------------------------------------------------------------------
-- Register update process
----------------------------------------------------------------------------
p_update_reg : process(clk_sys_i, rst_n_i)
begin
if(rst_n_i = '0') then
irq_ack <= (others => '0');
wr_ack <= '0';
irq_mask <= (others => '0');
elsif rising_edge(clk_sys_i) then
irq_ack <= (others => '0');
wr_ack <= '0';
-- WB WRITE classic cycle. Word granularity
if(wb_in.stb = '1' and wb_in.we = '0' and wb_in.cyc = '1' and sel = '1') then
wr_ack <= '1';
if(wb_in.adr(4 downto 2) = c_IRQ_REG_MASK) then
irq_mask <= wb_in.dat(g_irq_count-1 downto 0);
elsif(wb_in.adr(4 downto 2) = c_IRQ_REG_ACK) then
irq_ack <= wb_in.dat(g_irq_count-1 downto 0);
end if;
end if;
end if;
end process;
irq_req_o <= g_irq_level when(unsigned(irq_pend) /= 0 and rst_n_i = '1') else
not g_irq_level;
wb_out.ack <= rd_ack or wr_ack;
wb_out.dat <= readdata when (wb_in.stb = '1' and wb_in.we = '0' and wb_in.cyc = '1') else (others => '0');
wb_out.err <= '0';
wb_out.int <= '0';
wb_out.rty <= '0';
wb_out.stall <= '0';
end rtl;
hdl/modules/custom_wishbone/wb_irq_mngr/xwb_irq_mngr.vhd 0 → 100755
View file @ c9217ac1
-- Simple IRQ Manager
-- Based on the original design by:
--
-- Fabrice Mousset (fabrice.mousset@laposte.net)
-- Project : Wishbone Interruption Manager (ARMadeus wishbone example)
-- See: http://www.armadeus.com/wiki/index.php?title=A_simple_design_with_Wishbone_bus
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
entity xwb_irq_mngr is
generic(
g_irq_count : integer := 16;
g_irq_level : std_logic := '1';
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- Global Signals
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone interface signals
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
-- irq from other IP
irq_req_i : in std_logic_vector(g_irq_count-1 downto 0);
-- Component external signals
irq_req_o : out std_logic
);
end entity;
architecture rtl of xwb_irq_mngr is
component wb_irq_mngr
generic(
g_irq_count : integer := 16;
g_irq_level : std_logic := '1';
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := BYTE
);
port(
-- Global Signals
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone interface signals
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
--slave_i : in t_wishbone_slave_in;
--slave_o : out t_wishbone_slave_out;
-- irq from other IP
irq_req_i : in std_logic_vector(g_irq_count-1 downto 0);
-- Component external signals
irq_req_o : out std_logic
);
end component;
begin
cmp_wrapped_irq_mngr : wb_irq_mngr
generic map (
g_irq_count => g_irq_count,
g_irq_level => g_irq_level,
g_interface_mode => g_interface_mode,
g_address_granularity => g_address_granularity
)
port map (
clk_sys_i => clk_sys_i,
rst_n_i => rst_n_i,
wb_sel_i => slave_i.sel,
wb_cyc_i => slave_i.cyc,
wb_stb_i => slave_i.stb,
wb_we_i => slave_i.we,
wb_adr_i => slave_i.adr,
wb_dat_i => slave_i.dat,
wb_dat_o => slave_o.dat,
wb_ack_o => slave_o.ack,
wb_stall_o => slave_o.stall,
irq_req_i => irq_req_i,
irq_req_o => irq_req_o
);
slave_o.err <= '0';
slave_o.int <= '0';
slave_o.rty <= '0';
end rtl;
hdl/modules/custom_wishbone/wb_stream/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["wb_stream_pkg.vhd", "xwb_stream_sink.vhd", "xwb_stream_source.vhd"]
hdl/modules/custom_wishbone/wb_stream/wb_stream_pkg.vhd 0 → 100644
View file @ c9217ac1
-- Based on wb_fabric_pkg.vhd from Tomasz Wlostowski
-- Modified by Lucas Russo <lucas.russo@lnls.br>
library ieee;
use ieee.std_logic_1164.all;
package wb_stream_pkg is
-- Must be at least 2 bits wide
constant c_wbs_address_width : integer := 4;
-- Must be at least 16 bits wide
constant c_wbs_data_width : integer := 32;
subtype t_wbs_address is
std_logic_vector(c_wbs_address_width-1 downto 0);
subtype t_wbs_data is
std_logic_vector(c_wbs_data_width-1 downto 0);
subtype t_wbs_byte_select is
std_logic_vector((c_wbs_data_width/8)-1 downto 0);
constant c_WRF_DATA : unsigned(c_wbs_address_width-1 downto 0) := 0;
constant c_WRF_OOB : unsigned(c_wbs_address_width-1 downto 0) := 1;
constant c_WRF_STATUS : unsigned(c_wbs_address_width-1 downto 0) := 2;
constant c_WRF_USER : unsigned(c_wbs_address_width-1 downto 0) := 3;
--constant c_WRF_OOB_TYPE_RX : std_logic_vector(3 downto 0) := "0000";
--constant c_WRF_OOB_TYPE_TX : std_logic_vector(3 downto 0) := "0001";
type t_wb_stream_status_reg is record
is_hp : std_logic;
has_smac : std_logic;
has_crc : std_logic;
error : std_logic;
tag_me : std_logic;
match_class : std_logic_vector(7 downto 0);
end record;
type t_wbs_source_out is record
adr : t_wbs_address;
dat : c_wbs_data_width;
cyc : std_logic;
stb : std_logic;
we : std_logic;
sel : t_wbs_byte_select;
end record;
type t_wbs_source_in is record
ack : std_logic;
stall : std_logic;
err : std_logic;
rty : std_logic;
end record;
--type t_wrf_oob is record
-- valid: std_logic;
-- oob_type : std_logic_vector(3 downto 0);
-- ts_r : std_logic_vector(27 downto 0);
-- ts_f : std_logic_vector(3 downto 0);
-- frame_id : std_logic_vector(15 downto 0);
-- port_id : std_logic_vector(5 downto 0);
--end record;
subtype t_wbs_sink_in is t_wbs_source_out;
subtype t_wbs_sink_out is t_wbs_source_in;
type t_wbs_source_in_array is array (natural range <>) of t_wbs_source_in;
type t_wbs_source_out_array is array (natural range <>) of t_wbs_source_out;
subtype t_wbs_sink_in_array is t_wbs_source_out_array;
subtype t_wbs_sink_out_array is t_wbs_source_in_array;
function f_marshall_wbs_status (stat : t_wrf_status_reg) return std_logic_vector;
function f_unmarshall_wbs_status(stat : std_logic_vector) return t_wbs_status_reg;
constant cc_dummy_wbs_addr : std_logic_vector(c_wbs_address_width-1 downto 0):=
(others => 'X');
constant cc_dummy_wbs_dat : std_logic_vector(c_wbs_data_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_wbs_sel : std_logic_vector(c_wbs_data_width/8-1 downto 0) :=
(others => 'X');
constant c_dummy_src_in : t_wbs_source_in :=
('0', '0', '0', '0');
constant c_dummy_snk_in : t_wbs_sink_in :=
(cc_dummy_wbs_addr, cc_dummy_wbs_dat, '0', '0', '0', cc_dummy_wbs_sel);
end wb_stream_pkg;
package body wb_stream_pkg is
function f_marshall_wbs_status(stat : t_wbs_status_reg)
return std_logic_vector is
-- Wishbone bus data_width is at least 16 bits
variable tmp : std_logic_vector(c_wbs_data_width-1 downto 0);
begin
tmp(0) := stat.is_hp;
tmp(1) := stat.error;
tmp(2) := stat.has_smac;
tmp(3) := stat.has_crc;
tmp(15 downto 8) := stat.match_class;
return tmp;
end function;
function f_unmarshall_wbs_status(stat : std_logic_vector) return t_wbs_status_reg is
variable tmp : t_wbs_status_reg;
begin
tmp.is_hp := stat(0);
tmp.error := stat(1);
tmp.has_smac := stat(2);
tmp.has_crc := stat(3);
tmp.match_class := stat(15 downto 8);
return tmp;
end function;
end wb_stream_pkg;
hdl/modules/custom_wishbone/wb_stream/xwb_stream_sink.vhd 0 → 100644
View file @ c9217ac1
-------------------------------------------------------------------------------
-- Title : Wishbone Packet Fabric buffered packet sink
-- Project : WR Cores Collection
-------------------------------------------------------------------------------
-- File : xwb_fabric_sink.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-01-16
-- Last update: 2012-01-22
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: A simple WB packet streaming sink with builtin FIFO buffer.
-- Outputs a trivial interface (start-of-packet, end-of-packet, data-valid)
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-16 1.0 twlostow Created
-------------------------------------------------------------------------------
-- Modified by Lucas Russo <lucas.russo@lnls.br>
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
entity xwb_stream_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end xwb_fabric_sink;
architecture rtl of xwb_fabric_sink is
constant c_logic_width : integer := 4;
constant c_fifo_width : integer := c_wbs_data_width + c_wbs_address_width + 4;
constant c_fifo_depth : integer := 32;
constant c_logic_start : integer := c_wbs_data_width + c_wbs_address_width;
subtype c_logic_range is natural range c_wbs_address_width+c_wbs_data_width+c_logic_width-1 downto
c_wbs_address_width+c_wbs_data_width;
subtype c_data_range is natural range c_wbs_data_width-1 downto 0;
subtype c_addr_range is natural range c_wbs_address_width-1+c_wbs_data_width downto c_wbs_data_width;
signal q_valid, full, we, rd : std_logic;
signal fin, fout, fout_reg : std_logic_vector(c_fifo_width-1 downto 0);
signal cyc_d0, rd_d0 : std_logic;
signal pre_sof, pre_eof, pre_bytesel, pre_dvalid : std_logic;
signal post_sof, post_dvalid : std_logic;
signal post_addr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal post_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal snk_out : t_wbs_sink_out;
begin -- rtl
p_delay_cyc_and_rd : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_d0 <= '0';
rd_d0 <= '0';
else
if(full = '0') then
cyc_d0 <= snk_i.cyc;
end if;
rd_d0 <= rd;
end if;
end if;
end process;
pre_sof <= snk_i.cyc and not cyc_d0; -- sof
pre_eof <= not snk_i.cyc and cyc_d0; -- eof
pre_bytesel <= not snk_i.sel(0); -- bytesel
pre_dvalid <= snk_i.stb and snk_i.we and snk_i.cyc and not snk_out.stall; -- data valid
fin(c_data_range) <= snk_i.dat;
fin(c_addr_range) <= snk_i.adr;
fin(c_logic_range) <= pre_sof & pre_eof & pre_bytesel & pre_dvalid;
snk_out.stall <= full or (snk_i.cyc and not cyc_d0);
snk_out.err <= '0';
snk_out.rty <= '0';
p_gen_ack : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
snk_out.ack <= '0';
else
snk_out.ack <= snk_i.cyc and snk_i.stb and snk_i.we and not snk_out.stall;
end if;
end if;
end process;
snk_o <= snk_out;
we <= '1' when fin(c_logic_range) /= "0000" and full = '0' else '0';
rd <= q_valid and dreq_i and not post_sof;
U_FIFO : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid
);
p_fout_reg : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fout_reg <= (others => '0');
elsif(rd = '1') then
fout_reg <= fout;
end if;
end if;
end process;
post_data <= fout_reg(c_data_range);
post_addr <= fout_reg(c_addr_range);
post_sof <= fout_reg(c_logic_start+3) and rd_d0; --and q_valid;
post_dvalid <= fout_reg(c_logic_start);
sof_o <= post_sof and rd_d0;
dvalid_o <= post_dvalid and rd_d0;
error_o <= '1' when rd_d0 = '1' and (post_addr = std_logic_vector(c_WRF_STATUS)) and (f_unmarshall_wrf_status(post_data).error = '1') else '0';
eof_o <= fout_reg(c_logic_start+2) and rd_d0;
bytesel_o <= fout_reg(c_logic_start+1);
data_o <= post_data;
addr_o <= post_addr;
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
entity wb_stream_sink is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_dat_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
snk_adr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
snk_sel_i : in std_logic_vector((c_wbs_data_width/8)-1 downto 0);
snk_cyc_i : in std_logic;
snk_stb_i : in std_logic;
snk_we_i : in std_logic;
snk_stall_o : out std_logic;
snk_ack_o : out std_logic;
snk_err_o : out std_logic;
snk_rty_o : out std_logic;
-- Decoded & buffered fabric
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic
);
end wb_stream_sink;
architecture wrapper of wb_stream_sink is
component xwb_stream_sink
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
snk_i : in t_wbs_sink_in;
snk_o : out t_wbs_sink_out;
addr_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
data_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_o : out std_logic;
sof_o : out std_logic;
eof_o : out std_logic;
error_o : out std_logic;
bytesel_o : out std_logic;
dreq_i : in std_logic);
end component;
signal snk_in : t_wbs_sink_in;
signal snk_out : t_wbs_sink_out;
begin -- wrapper
U_Wrapped_Sink : xwb_stream_sink
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
snk_i => snk_in,
snk_o => snk_out,
addr_o => addr_o,
data_o => data_o,
dvalid_o => dvalid_o,
sof_o => sof_o,
eof_o => eof_o,
error_o => error_o,
bytesel_o => bytesel_o,
dreq_i => dreq_i);
snk_in.adr <= snk_adr_i;
snk_in.dat <= snk_dat_i;
snk_in.stb <= snk_stb_i;
snk_in.we <= snk_we_i;
snk_in.cyc <= snk_cyc_i;
snk_in.sel <= snk_sel_i;
snk_stall_o <= snk_out.stall;
snk_ack_o <= snk_out.ack;
snk_err_o <= snk_out.err;
snk_rty_o <= snk_out.rty;
end wrapper;
hdl/modules/custom_wishbone/wb_stream/xwb_stream_source.vhd 0 → 100644
View file @ c9217ac1
-- Based on xwb_fabric_source.vhd from Tomasz Wlostowski
-- Modified by Lucas Russo <lucas.russo@lnls.br>
library ieee;
use ieee.std_logic_1164.all;
use work.genram_pkg.all;
use work.wb_stream_pkg.all;
entity xwb_stream_source is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
-- Decoded & buffered logic
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
);
end xwb_fabric_source;
architecture rtl of xwb_fabric_source is
constant c_logic_width : integer := 4;
constant c_fifo_width : integer := c_wbs_data_width + c_wbs_address_width + 4;
constant c_fifo_depth : integer := 32;
constant c_logic_start : integer := c_wbs_data_width + c_wbs_address_width;
-- FIX. Workaround to vhdl limitation
constant almost_all_ones : std_logic_vector((c_wbs_data_width/8)-2 downto 0) := (others => '1');
-- FIFO out range
subtype c_logic_range is natural range c_wbs_address_width+c_wbs_data_width+c_logic_width-1 downto
c_wbs_address_width+c_wbs_data_width;
subtype c_data_range is natural range c_wbs_data_width-1 downto 0;
subtype c_addr_range is natural range c_wbs_address_width-1+c_wbs_data_width downto c_wbs_data_width;
--subtype c_sel_range is natural range c_wbs_address_width+c_wbs_data_width+(c_wbs_address_width/8)-1 downto c_wbs_address_width+c_wbs_data_width;
signal q_valid, full, we, rd, rd_d0 : std_logic;
signal fin, fout : std_logic_vector(c_fifo_width-1 downto 0);
signal pre_dvalid : std_logic;
signal pre_eof : std_logic;
signal pre_data : std_logic_vector(c_wbs_data_width-1 downto 0);
signal pre_addr : std_logic_vector(c_wbs_address_width-1 downto 0);
signal post_dvalid, post_eof, post_bytesel, post_sof : std_logic;
signal err_status : t_wrf_status_reg;
signal cyc_int : std_logic;
begin -- rtl
err_status.error <= '1';
dreq_o <= not full;
rd <= not src_i.stall;
we <= sof_i or eof_i or error_i or dvalid_i;
pre_dvalid <= dvalid_i or error_i;
pre_data <= data_i when (error_i = '0') else f_marshall_wrf_status(err_status);
pre_addr <= addr_i when (error_i = '0') else std_logic_vector(c_WRF_STATUS);
pre_eof <= error_i or eof_i;
fin <= sof_i & pre_eof & bytesel_i & pre_dvalid & pre_addr & pre_data;
U_FIFO : generic_shiftreg_fifo
generic map (
g_data_width => c_fifo_width,
g_size => c_fifo_depth
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
d_i => fin,
we_i => we,
q_o => fout,
rd_i => rd,
almost_full_o => full,
q_valid_o => q_valid
);
post_sof <= fout(c_logic_start+3);
post_eof <= fout(c_logic_start+2);
post_dvalid <= fout(c_logic_start);
p_gen_cyc : process(clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
cyc_int <= '0';
else
if(src_i.stall = '0' and q_valid = '1') then
if(post_sof = '1')then
cyc_int <= '1';
elsif(post_eof = '1') then
cyc_int <= '0';
end if;
end if;
end if;
end if;
end process;
src_o.cyc <= cyc_int or post_sof;
src_o.we <= '1';
src_o.stb <= post_dvalid and q_valid;
src_o.sel <= almost_all_ones & not fout(c_logic_start+1);
src_o.dat <= fout(c_data_range);
src_o.adr <= fout(c_addr_range);
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use work.wb_stream_pkg.all;
entity wb_stream_source is
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Wishbone Fabric Interface I/O
src_dat_o : out std_logic_vector(c_wbs_address_width-1 downto 0);
src_adr_o : out std_logic_vector(c_wbs_data_width-1 downto 0);
src_sel_o : out std_logic_vector((c_wbs_data_width/8)-1 downto 0);
src_cyc_o : out std_logic;
src_stb_o : out std_logic;
src_we_o : out std_logic;
src_stall_i : in std_logic;
src_ack_i : in std_logic;
src_err_i : in std_logic;
-- Decoded & buffered fabric
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic
);
end wb_stream_source;
architecture wrapper of wb_fabric_source is
component xwb_fabric_source
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
src_i : in t_wbs_source_in;
src_o : out t_wbs_source_out;
addr_i : in std_logic_vector(c_wbs_address_width-1 downto 0);
data_i : in std_logic_vector(c_wbs_data_width-1 downto 0);
dvalid_i : in std_logic;
sof_i : in std_logic;
eof_i : in std_logic;
error_i : in std_logic;
bytesel_i : in std_logic;
dreq_o : out std_logic);
end component;
signal src_in : t_wbs_source_in;
signal src_out : t_wbs_source_out;
begin -- wrapper
U_Wrapped_Source : xwb_fabric_source
port map (
clk_i => clk_i,
rst_n_i => rst_n_i,
src_i => src_in,
src_o => src_out,
addr_i => addr_i,
data_i => data_i,
dvalid_i => dvalid_i,
sof_i => sof_i,
eof_i => eof_i,
error_i => error_i,
bytesel_i => bytesel_i,
dreq_o => dreq_o);
src_cyc_o <= src_out.cyc;
src_stb_o <= src_out.stb;
src_we_o <= src_out.we;
src_sel_o <= src_out.sel;
src_adr_o <= src_out.adr;
src_dat_o <= src_out.dat;
src_in.rty <= '0';
src_in.err <= src_err_i;
src_in.ack <= src_ack_i;
src_in.stall <= src_stall_i;
end wrapper;
hdl/platform/virtex6/chipscope/Manifest.py 0 → 100644
View file @ c9217ac1
files = ["chipscope_icon.ngc", "chipscope_ila.ngc"]
\ No newline at end of file
hdl/platform/virtex6/chipscope/chipscope_icon.ngc 0 → 100644
View file @ c9217ac1
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
hdl/platform/virtex6/chipscope/chipscope_ila.ngc 0 → 100644
View file @ c9217ac1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/sim/regs/xctl_iface_regs.vh 0 → 100644
View file @ c9217ac1
`define ADDR_CTL_IFACE_CTL 3'h0
`define CTL_IFACE_CTL_START_OFFSET 0
`define CTL_IFACE_CTL_START 32'h00000001
`define CTL_IFACE_CTL_DONE_OFFSET 1
`define CTL_IFACE_CTL_DONE 32'h00000002
`define CTL_IFACE_CTL_OVF_OFFSET 2
`define CTL_IFACE_CTL_OVF 32'h00000004
`define ADDR_CTL_IFACE_TR_CNTR 3'h4
hdl/sim/regs/xdata_sink_regs.vh 0 → 100644
View file @ c9217ac1
`define ADDR_DATA_SINK_FIFO_C2B_R0 4'h0
`define DATA_SINK_FIFO_C2B_R0_DATA_OFFSET 0
`define DATA_SINK_FIFO_C2B_R0_DATA 32'hffffffff
`define ADDR_DATA_SINK_FIFO_C2B_R1 4'h4
`define DATA_SINK_FIFO_C2B_R1_LAST_OFFSET 0
`define DATA_SINK_FIFO_C2B_R1_LAST 32'h00000001
`define ADDR_DATA_SINK_FIFO_C2B_CSR 4'h8
`define DATA_SINK_FIFO_C2B_CSR_FULL_OFFSET 16
`define DATA_SINK_FIFO_C2B_CSR_FULL 32'h00010000
`define DATA_SINK_FIFO_C2B_CSR_EMPTY_OFFSET 17
`define DATA_SINK_FIFO_C2B_CSR_EMPTY 32'h00020000
`define DATA_SINK_FIFO_C2B_CSR_USEDW_OFFSET 0
`define DATA_SINK_FIFO_C2B_CSR_USEDW 32'h000000ff
hdl/sim/regs/xdata_src_regs.vh 0 → 100644
View file @ c9217ac1
`define ADDR_DATA_SRC_B2C_R0 3'h0
`define DATA_SRC_B2C_R0_DATA_OFFSET 0
`define DATA_SRC_B2C_R0_DATA 32'hffffffff
`define ADDR_DATA_SRC_B2C_CSR 3'h4
`define DATA_SRC_B2C_CSR_FULL_OFFSET 16
`define DATA_SRC_B2C_CSR_FULL 32'h00010000
`define DATA_SRC_B2C_CSR_EMPTY_OFFSET 17
`define DATA_SRC_B2C_CSR_EMPTY 32'h00020000
`define DATA_SRC_B2C_CSR_USEDW_OFFSET 0
`define DATA_SRC_B2C_CSR_USEDW 32'h000000ff
hdl/sim/regs/xfmc150_regs_regs.vh 0 → 100644
View file @ c9217ac1
`define ADDR_FMC150_FLGS_PULSE 5'h0
`define ADDR_FMC150_FLGS_IN 5'h4
`define FMC150_FLGS_IN_SPI_RW_OFFSET 0
`define FMC150_FLGS_IN_SPI_RW 32'h00000001
`define FMC150_FLGS_IN_EXT_CLK_OFFSET 1
`define FMC150_FLGS_IN_EXT_CLK 32'h00000002
`define ADDR_FMC150_ADDR 5'h8
`define ADDR_FMC150_DATA_IN 5'hc
`define ADDR_FMC150_CS 5'h10
`define FMC150_CS_CDCE72010_OFFSET 0
`define FMC150_CS_CDCE72010 32'h00000001
`define FMC150_CS_ADS62P49_OFFSET 1
`define FMC150_CS_ADS62P49 32'h00000002
`define FMC150_CS_DAC3283_OFFSET 2
`define FMC150_CS_DAC3283 32'h00000004
`define FMC150_CS_AMC7823_OFFSET 3
`define FMC150_CS_AMC7823 32'h00000008
`define ADDR_FMC150_ADC_DLY 5'h14
`define FMC150_ADC_DLY_STR_OFFSET 0
`define FMC150_ADC_DLY_STR 32'h0000001f
`define FMC150_ADC_DLY_CHA_OFFSET 8
`define FMC150_ADC_DLY_CHA 32'h00001f00
`define FMC150_ADC_DLY_CHB_OFFSET 16
`define FMC150_ADC_DLY_CHB 32'h001f0000
`define ADDR_FMC150_DATA_OUT 5'h18
`define ADDR_FMC150_FLGS_OUT 5'h1c
`define FMC150_FLGS_OUT_SPI_BUSY_OFFSET 0
`define FMC150_FLGS_OUT_SPI_BUSY 32'h00000001
`define FMC150_FLGS_OUT_PLL_STATUS_OFFSET 1
`define FMC150_FLGS_OUT_PLL_STATUS 32'h00000002
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED_OFFSET 2
`define FMC150_FLGS_OUT_ADC_CLK_LOCKED 32'h00000004
`define FMC150_FLGS_OUT_FMC_PRST_OFFSET 3
`define FMC150_FLGS_OUT_FMC_PRST 32'h00000008
hdl/sim/wishbone_test_master/wishbone_test_master.v 0 → 100644
View file @ c9217ac1
//
// Title : Software Wishbone master unit for testbenches
//
// File : wishbone_master_tb.v
// Author : Tomasz Wlostowski <tomasz.wlostowski@cern.ch>
// Created : Tue Mar 23 12:19:36 2010
// Standard : Verilog 2001
//
// Default values of certain WB parameters.
// Bus clock period
`ifndef WB_CLOCK_PERIOD
`define WB_CLOCK_PERIOD 100
`define WB_RESET_DELAY (3*`WB_CLOCK_PERIOD)
`endif
// Widths of wishbone address/data/byte select
`ifndef WB_DATA_BUS_WIDTH
`define WB_DATA_BUS_WIDTH 32
`endif
`ifndef WB_ADDRESS_BUS_WIDTH
`define WB_ADDRESS_BUS_WIDTH 32
`endif
`define WB_BWSEL_WIDTH ((`WB_DATA_BUS_WIDTH + 7) / 8)
module WB_TEST_MASTER;
// these signals make the WB bus, which can be accessed from outside the module
reg [`WB_ADDRESS_BUS_WIDTH - 1 : 0] wb_addr = 0;
reg [`WB_DATA_BUS_WIDTH - 1 : 0] wb_data_o = 0;
reg [`WB_BWSEL_WIDTH - 1 : 0] wb_bwsel = 0;
wire [`WB_DATA_BUS_WIDTH -1 : 0] wb_data_i;
wire wb_ack;
reg wb_cyc = 0;
reg wb_stb = 0;
reg wb_we = 0;
reg wb_rst = 0;
reg wb_clk = 1;
reg wb_tb_verbose = 1;
reg wb_monitor_bus = 1;
time last_access_t = 0;
reg [`WB_DATA_BUS_WIDTH -1 : 0] dummy;
// ready signal. 1 indicates that WB_TEST unit is initialized and ready for commands
reg ready = 0;
// generate the WB bus clock
always #(`WB_CLOCK_PERIOD/2) wb_clk <= ~wb_clk;
// generate the reset and ready signals
initial begin
#(`WB_RESET_DELAY) wb_rst <= 1;
#(`WB_CLOCK_PERIOD*2) ready <= 1;
end
// enables/disables displaying information about each read/write operation.
task verbose;
input onoff;
begin
wb_tb_verbose = onoff;
end
endtask // wb_verbose
task monitor_bus;
input onoff;
begin
wb_monitor_bus = onoff;
end
endtask // monitor_bus
task rw_generic;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
input [`WB_DATA_BUS_WIDTH - 1 : 0] data_i;
output [`WB_DATA_BUS_WIDTH - 1 : 0] data_o;
input rw;
input [3:0] size;
begin : rw_generic_main
if(wb_tb_verbose && rw)
$display("WB write %s: addr %x, data %x",
(size==1?"byte":((size==2)?"short":"int")),
addr, data_i);
if($time != last_access_t) begin
@(posedge wb_clk);
end
wb_stb<=1;
wb_cyc<=1;
wb_addr <= {2'b00, addr[31:2]};
wb_we <= rw;
if(rw) begin
case(size)
4: begin wb_data_o<=data_i; wb_bwsel <= 4'b1111; end
2: begin
if(addr[1]) begin
wb_data_o[31:16] = data_i[15:0];
wb_bwsel = 4'b1100;
end else begin
wb_data_o[15:0] = data_i[15:0];
wb_bwsel = 4'b0011;
end
end
1: begin
case(addr[1:0])
0: begin wb_data_o[31:24] = data_i[7:0]; wb_bwsel <= 4'b1000; end
1: begin wb_data_o[23:16] = data_i[7:0]; wb_bwsel <= 4'b0100; end
2: begin wb_data_o[15:8] = data_i[7:0]; wb_bwsel <= 4'b0010; end
3: begin wb_data_o[7:0] = data_i[7:0]; wb_bwsel <= 4'b0001; end
endcase // case(addr[1:0])
end
endcase // case(size)
end // if (rw)
#(`WB_CLOCK_PERIOD-1);
if(wb_ack == 0) begin
while(wb_ack == 0) begin @(posedge wb_clk); end
end
data_o = wb_data_i;
wb_cyc <= 0;
wb_we<=0;
wb_stb<=0;
if(wb_tb_verbose && !rw)
$display("WB read %s: addr %x, data %x",
(size==1?"byte":((size==2)?"short":"int")),
addr, wb_data_i);
last_access_t = $time;
end
endtask // rw_generic
task write8;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
input [7 : 0] data_i;
begin
rw_generic(addr, data_i, dummy, 1, 1);
end
endtask // write8
task read8;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
output [7 : 0] data_o;
begin : read8_body
reg [`WB_DATA_BUS_WIDTH - 1 : 0] rval;
rw_generic(addr, 0, rval, 0, 1);
data_o = rval[7:0];
end
endtask // write8
task write32;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
input [31 : 0] data_i;
begin
rw_generic(addr, data_i, dummy, 1, 4);
end
endtask // write32
task read32;
input [`WB_ADDRESS_BUS_WIDTH - 1 : 0] addr;
output [31 : 0] data_o;
begin : read32_body
reg [`WB_DATA_BUS_WIDTH - 1 : 0] rval;
rw_generic(addr, 0, rval, 0, 4);
data_o = rval[31:0];
end
endtask // write32
// bus monitor
always@(posedge wb_clk) begin
if(wb_monitor_bus && wb_cyc && wb_stb && wb_ack)begin
if(wb_we) $display("ACK-Write: addr %x wdata %x bwsel %b", wb_addr, wb_data_o, wb_bwsel);
else $display("ACK-Read: addr %x rdata %x", wb_addr, wb_data_i);
end
end
endmodule
\ No newline at end of file
hdl/testbench/wishbone/wb_dma_interface_test/Makefile 0 → 100644
View file @ c9217ac1
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
## variables #############################
PWD := $(shell pwd)
TOP_MODULE :=
FUSE_OUTPUT ?= isim_proj
XILINX_INI_PATH := /opt/Xilinx/13.4/ISE_DS/ISE/vhdl/hdp/lin64
VHPCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
ISIM_FLAGS :=
VLOGCOMP_FLAGS := -intstyle default -incremental -initfile xilinxsim.ini
VERILOG_SRC := ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v \
../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v \
../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v \
../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v \
VERILOG_OBJ := work/sockit_owm/.sockit_owm_v \
work/spi_clgen/.spi_clgen_v \
work/spi_shift/.spi_shift_v \
work/spi_top/.spi_top_v \
work/lm32_allprofiles/.lm32_allprofiles_v \
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v \
work/jtag_cores/.jtag_cores_v \
work/lm32_adder/.lm32_adder_v \
work/lm32_addsub/.lm32_addsub_v \
work/lm32_dp_ram/.lm32_dp_ram_v \
work/lm32_logic_op/.lm32_logic_op_v \
work/lm32_ram/.lm32_ram_v \
work/lm32_shifter/.lm32_shifter_v \
work/lm32_multiplier/.lm32_multiplier_v \
work/jtag_tap/.jtag_tap_v \
VHDL_SRC := wb_dma_interface_tb.vhd \
../../../modules/custom_wishbone/custom_wishbone_pkg.vhd \
../../../modules/custom_common/custom_common_pkg.vhd \
../../../modules/custom_wishbone/wb_dma_interface/wb_dma_interface.vhd \
../../../modules/custom_wishbone/wb_dma_interface/xwb_dma_interface.vhd \
../../../modules/custom_common/reset_synch/reset_synch.vhd \
../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd \
../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd \
../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd \
../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd \
../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd \
../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd \
../../../ip_cores/general-cores/modules/common/gc_reset.vhd \
../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd \
../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd \
../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd \
../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd \
../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd \
../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd \
../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd \
../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd \
../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd \
../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd \
../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd \
../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd \
../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd \
../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd \
../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd \
../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd \
../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd \
../../../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd \
../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd \
../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd \
VHDL_OBJ := work/wb_dma_interface_tb/.wb_dma_interface_tb_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd \
work/custom_common_pkg/.custom_common_pkg_vhd \
work/wb_dma_interface/.wb_dma_interface_vhd \
work/xwb_dma_interface/.xwb_dma_interface_vhd \
work/reset_synch/.reset_synch_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/gc_crc_gen/.gc_crc_gen_vhd \
work/gc_moving_average/.gc_moving_average_vhd \
work/gc_extend_pulse/.gc_extend_pulse_vhd \
work/gc_delay_gen/.gc_delay_gen_vhd \
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd \
work/gc_reset/.gc_reset_vhd \
work/gc_serial_dac/.gc_serial_dac_vhd \
work/gc_sync_ffs/.gc_sync_ffs_vhd \
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd \
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd \
work/gc_frequency_meter/.gc_frequency_meter_vhd \
work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd \
work/gc_wfifo/.gc_wfifo_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/memory_loader_pkg/.memory_loader_pkg_vhd \
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/generic_dpram/.generic_dpram_vhd \
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd \
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd \
work/generic_spram/.generic_spram_vhd \
work/generic_async_fifo/.generic_async_fifo_vhd \
work/generic_sync_fifo/.generic_sync_fifo_vhd \
fifo_generator_v6_1/dummy/.dummy_vhd \
work/wb_async_bridge/.wb_async_bridge_vhd \
work/xwb_async_bridge/.xwb_async_bridge_vhd \
work/wb_onewire_master/.wb_onewire_master_vhd \
work/xwb_onewire_master/.xwb_onewire_master_vhd \
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd \
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd \
work/i2c_master_top/.i2c_master_top_vhd \
work/wb_i2c_master/.wb_i2c_master_vhd \
work/xwb_i2c_master/.xwb_i2c_master_vhd \
work/xwb_bus_fanout/.xwb_bus_fanout_vhd \
work/xwb_dpram/.xwb_dpram_vhd \
work/wb_gpio_port/.wb_gpio_port_vhd \
work/xwb_gpio_port/.xwb_gpio_port_vhd \
work/wb_tics/.wb_tics_vhd \
work/xwb_tics/.xwb_tics_vhd \
work/uart_async_rx/.uart_async_rx_vhd \
work/uart_async_tx/.uart_async_tx_vhd \
work/uart_baud_gen/.uart_baud_gen_vhd \
work/simple_uart_wb/.simple_uart_wb_vhd \
work/simple_uart_pkg/.simple_uart_pkg_vhd \
work/wb_simple_uart/.wb_simple_uart_vhd \
work/xwb_simple_uart/.xwb_simple_uart_vhd \
work/vic_prio_enc/.vic_prio_enc_vhd \
work/wb_slave_vic/.wb_slave_vic_vhd \
work/wb_vic/.wb_vic_vhd \
work/xwb_vic/.xwb_vic_vhd \
work/wb_spi/.wb_spi_vhd \
work/xwb_spi/.xwb_spi_vhd \
work/sdb_rom/.sdb_rom_vhd \
work/xwb_crossbar/.xwb_crossbar_vhd \
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd \
work/xwb_lm32/.xwb_lm32_vhd \
work/wb_slave_adapter/.wb_slave_adapter_vhd \
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd \
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd \
work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
work/xloader_wb/.xloader_wb_vhd \
work/xwb_clock_crossing/.xwb_clock_crossing_vhd \
work/xwb_dma/.xwb_dma_vhd \
work/wbgen2_dpssram/.wbgen2_dpssram_vhd \
work/wbgen2_eic/.wbgen2_eic_vhd \
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd \
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd \
LIBS := work fifo_generator_v6_1
LIB_IND := work/.work fifo_generator_v6_1/.fifo_generator_v6_1
## rules #################################
sim: xilinxsim.ini $(LIB_IND) $(VERILOG_OBJ) $(VHDL_OBJ)
$(VERILOG_OBJ): $(VHDL_OBJ)
$(VHDL_OBJ): $(LIB_IND) xilinxsim.ini
xilinxsim.ini: $(XILINX_INI_PATH)/xilinxsim.ini
cp $< .
fuse: ;
ifeq ($(TOP_MODULE),)
@echo "Environment variable TOP_MODULE not set!"
else
fuse work.$(TOP_MODULE) -intstyle ise -incremental -o $(FUSE_OUTPUT)
endif
clean:
rm -rf ./xilinxsim.ini $(LIBS) fuse.xmsgs fuse.log fuseRelaunch.cmd isim isim.log isim.wdb
.PHONY: clean
work/.work:
(mkdir work && touch work/.work && echo "work=work" >> xilinxsim.ini) || rm -rf work
fifo_generator_v6_1/.fifo_generator_v6_1:
(mkdir fifo_generator_v6_1 && touch fifo_generator_v6_1/.fifo_generator_v6_1 && echo "fifo_generator_v6_1=fifo_generator_v6_1" >> xilinxsim.ini) || rm -rf fifo_generator_v6_1
work/sockit_owm/.sockit_owm_v: ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master $<
@mkdir -p $(dir $@) && touch $@
work/spi_clgen/.spi_clgen_v: ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/spi_shift/.spi_shift_v: ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/spi_top/.spi_top_v: ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v ../../../ip_cores/general-cores/modules/wishbone/wb_spi/spi_defines.v ../../../ip_cores/general-cores/modules/wishbone/wb_spi/timescale.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_spi $<
@mkdir -p $(dir $@) && touch $@
work/lm32_allprofiles/.lm32_allprofiles_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated $<
@mkdir -p $(dir $@) && touch $@
work/lm32_mc_arithmetic/.lm32_mc_arithmetic_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/jtag_cores/.jtag_cores_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_adder/.lm32_adder_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_addsub/.lm32_addsub_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_dp_ram/.lm32_dp_ram_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_logic_op/.lm32_logic_op_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_ram/.lm32_ram_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_shifter/.lm32_shifter_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_include.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/src $<
@mkdir -p $(dir $@) && touch $@
work/lm32_multiplier/.lm32_multiplier_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/../../src/lm32_include.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
@mkdir -p $(dir $@) && touch $@
work/jtag_tap/.jtag_tap_v: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
vlogcomp -work work=./work $(VLOGCOMP_FLAGS) -i ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic $<
@mkdir -p $(dir $@) && touch $@
work/wb_dma_interface_tb/.wb_dma_interface_tb_vhd: wb_dma_interface_tb.vhd work/wb_dma_interface_tb/.wb_dma_interface_tb
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_dma_interface_tb/.wb_dma_interface_tb: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd: ../../../modules/custom_wishbone/custom_wishbone_pkg.vhd work/custom_wishbone_pkg/.custom_wishbone_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/custom_wishbone_pkg/.custom_wishbone_pkg: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/custom_common_pkg/.custom_common_pkg_vhd: ../../../modules/custom_common/custom_common_pkg.vhd work/custom_common_pkg/.custom_common_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/custom_common_pkg/.custom_common_pkg:
work/wb_dma_interface/.wb_dma_interface_vhd: ../../../modules/custom_wishbone/wb_dma_interface/wb_dma_interface.vhd work/wb_dma_interface/.wb_dma_interface
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_dma_interface/.wb_dma_interface: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd \
work/custom_common_pkg/.custom_common_pkg_vhd
work/xwb_dma_interface/.xwb_dma_interface_vhd: ../../../modules/custom_wishbone/wb_dma_interface/xwb_dma_interface.vhd work/xwb_dma_interface/.xwb_dma_interface
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_dma_interface/.xwb_dma_interface: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/custom_wishbone_pkg/.custom_wishbone_pkg_vhd
work/reset_synch/.reset_synch_vhd: ../../../modules/custom_common/reset_synch/reset_synch.vhd work/reset_synch/.reset_synch
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/reset_synch/.reset_synch:
work/gencores_pkg/.gencores_pkg_vhd: ../../../ip_cores/general-cores/modules/common/gencores_pkg.vhd work/gencores_pkg/.gencores_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gencores_pkg/.gencores_pkg: \
work/genram_pkg/.genram_pkg_vhd
work/gc_crc_gen/.gc_crc_gen_vhd: ../../../ip_cores/general-cores/modules/common/gc_crc_gen.vhd work/gc_crc_gen/.gc_crc_gen
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_crc_gen/.gc_crc_gen: \
work/gencores_pkg/.gencores_pkg_vhd
work/gc_moving_average/.gc_moving_average_vhd: ../../../ip_cores/general-cores/modules/common/gc_moving_average.vhd work/gc_moving_average/.gc_moving_average
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_moving_average/.gc_moving_average: \
work/gencores_pkg/.gencores_pkg_vhd
work/gc_extend_pulse/.gc_extend_pulse_vhd: ../../../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd work/gc_extend_pulse/.gc_extend_pulse
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_extend_pulse/.gc_extend_pulse: \
work/gencores_pkg/.gencores_pkg_vhd
work/gc_delay_gen/.gc_delay_gen_vhd: ../../../ip_cores/general-cores/modules/common/gc_delay_gen.vhd work/gc_delay_gen/.gc_delay_gen
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_delay_gen/.gc_delay_gen: \
work/gencores_pkg/.gencores_pkg_vhd
work/gc_dual_pi_controller/.gc_dual_pi_controller_vhd: ../../../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd work/gc_dual_pi_controller/.gc_dual_pi_controller
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_dual_pi_controller/.gc_dual_pi_controller: \
work/gencores_pkg/.gencores_pkg_vhd
work/gc_reset/.gc_reset_vhd: ../../../ip_cores/general-cores/modules/common/gc_reset.vhd work/gc_reset/.gc_reset
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_reset/.gc_reset:
work/gc_serial_dac/.gc_serial_dac_vhd: ../../../ip_cores/general-cores/modules/common/gc_serial_dac.vhd work/gc_serial_dac/.gc_serial_dac
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_serial_dac/.gc_serial_dac:
work/gc_sync_ffs/.gc_sync_ffs_vhd: ../../../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd work/gc_sync_ffs/.gc_sync_ffs
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_sync_ffs/.gc_sync_ffs:
work/gc_arbitrated_mux/.gc_arbitrated_mux_vhd: ../../../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd work/gc_arbitrated_mux/.gc_arbitrated_mux
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_arbitrated_mux/.gc_arbitrated_mux: \
work/genram_pkg/.genram_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd
work/gc_pulse_synchronizer/.gc_pulse_synchronizer_vhd: ../../../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd work/gc_pulse_synchronizer/.gc_pulse_synchronizer
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_pulse_synchronizer/.gc_pulse_synchronizer: \
work/gencores_pkg/.gencores_pkg_vhd
work/gc_frequency_meter/.gc_frequency_meter_vhd: ../../../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd work/gc_frequency_meter/.gc_frequency_meter
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_frequency_meter/.gc_frequency_meter: \
work/gencores_pkg/.gencores_pkg_vhd
work/gc_dual_clock_ram/.gc_dual_clock_ram_vhd: ../../../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd work/gc_dual_clock_ram/.gc_dual_clock_ram
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_dual_clock_ram/.gc_dual_clock_ram:
work/gc_wfifo/.gc_wfifo_vhd: ../../../ip_cores/general-cores/modules/common/gc_wfifo.vhd work/gc_wfifo/.gc_wfifo
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/gc_wfifo/.gc_wfifo: \
work/gencores_pkg/.gencores_pkg_vhd
work/genram_pkg/.genram_pkg_vhd: ../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd work/genram_pkg/.genram_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/genram_pkg/.genram_pkg:
work/memory_loader_pkg/.memory_loader_pkg_vhd: ../../../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd work/memory_loader_pkg/.memory_loader_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/memory_loader_pkg/.memory_loader_pkg: \
work/genram_pkg/.genram_pkg_vhd
work/generic_shiftreg_fifo/.generic_shiftreg_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd work/generic_shiftreg_fifo/.generic_shiftreg_fifo
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/generic_shiftreg_fifo/.generic_shiftreg_fifo: \
work/genram_pkg/.genram_pkg_vhd
work/wishbone_pkg/.wishbone_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd work/wishbone_pkg/.wishbone_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wishbone_pkg/.wishbone_pkg: \
work/genram_pkg/.genram_pkg_vhd
work/generic_dpram/.generic_dpram_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd work/generic_dpram/.generic_dpram
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram/.generic_dpram: \
work/genram_pkg/.genram_pkg_vhd \
work/memory_loader_pkg/.memory_loader_pkg_vhd
work/generic_dpram_sameclock/.generic_dpram_sameclock_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd work/generic_dpram_sameclock/.generic_dpram_sameclock
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram_sameclock/.generic_dpram_sameclock: \
work/genram_pkg/.genram_pkg_vhd \
work/memory_loader_pkg/.memory_loader_pkg_vhd
work/generic_dpram_dualclock/.generic_dpram_dualclock_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd work/generic_dpram_dualclock/.generic_dpram_dualclock
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/generic_dpram_dualclock/.generic_dpram_dualclock: \
work/genram_pkg/.genram_pkg_vhd \
work/memory_loader_pkg/.memory_loader_pkg_vhd
work/generic_spram/.generic_spram_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd work/generic_spram/.generic_spram
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/generic_spram/.generic_spram: \
work/genram_pkg/.genram_pkg_vhd
work/generic_async_fifo/.generic_async_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd work/generic_async_fifo/.generic_async_fifo
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/generic_async_fifo/.generic_async_fifo: \
work/genram_pkg/.genram_pkg_vhd
work/generic_sync_fifo/.generic_sync_fifo_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd work/generic_sync_fifo/.generic_sync_fifo
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/generic_sync_fifo/.generic_sync_fifo: \
work/genram_pkg/.genram_pkg_vhd
fifo_generator_v6_1/dummy/.dummy_vhd: ../../../ip_cores/general-cores/modules/genrams/xilinx/sim_stub/dummy.vhd fifo_generator_v6_1/dummy/.dummy
vhpcomp $(VHPCOMP_FLAGS) -work fifo_generator_v6_1=./fifo_generator_v6_1 $<
@mkdir -p $(dir $@) && touch $@
fifo_generator_v6_1/dummy/.dummy:
work/wb_async_bridge/.wb_async_bridge_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd work/wb_async_bridge/.wb_async_bridge
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_async_bridge/.wb_async_bridge: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd
work/xwb_async_bridge/.xwb_async_bridge_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd work/xwb_async_bridge/.xwb_async_bridge
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_async_bridge/.xwb_async_bridge: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/wb_onewire_master/.wb_onewire_master_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd work/wb_onewire_master/.wb_onewire_master
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_onewire_master/.wb_onewire_master: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd
work/xwb_onewire_master/.xwb_onewire_master_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd work/xwb_onewire_master/.xwb_onewire_master
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_onewire_master/.xwb_onewire_master: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_bit_ctrl/.i2c_master_bit_ctrl:
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_byte_ctrl/.i2c_master_byte_ctrl:
work/i2c_master_top/.i2c_master_top_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd work/i2c_master_top/.i2c_master_top
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/i2c_master_top/.i2c_master_top:
work/wb_i2c_master/.wb_i2c_master_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd work/wb_i2c_master/.wb_i2c_master
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_i2c_master/.wb_i2c_master: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_i2c_master/.xwb_i2c_master_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd work/xwb_i2c_master/.xwb_i2c_master
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_i2c_master/.xwb_i2c_master: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_bus_fanout/.xwb_bus_fanout_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd work/xwb_bus_fanout/.xwb_bus_fanout
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_bus_fanout/.xwb_bus_fanout: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_dpram/.xwb_dpram_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd work/xwb_dpram/.xwb_dpram
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_dpram/.xwb_dpram: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/genram_pkg/.genram_pkg_vhd
work/wb_gpio_port/.wb_gpio_port_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd work/wb_gpio_port/.wb_gpio_port
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_gpio_port/.wb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd
work/xwb_gpio_port/.xwb_gpio_port_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd work/xwb_gpio_port/.xwb_gpio_port
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_gpio_port/.xwb_gpio_port: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/wb_tics/.wb_tics_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd work/wb_tics/.wb_tics
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_tics/.wb_tics: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_tics/.xwb_tics_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd work/xwb_tics/.xwb_tics
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_tics/.xwb_tics: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/uart_async_rx/.uart_async_rx_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd work/uart_async_rx/.uart_async_rx
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_rx/.uart_async_rx:
work/uart_async_tx/.uart_async_tx_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd work/uart_async_tx/.uart_async_tx
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/uart_async_tx/.uart_async_tx:
work/uart_baud_gen/.uart_baud_gen_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd work/uart_baud_gen/.uart_baud_gen
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/uart_baud_gen/.uart_baud_gen:
work/simple_uart_wb/.simple_uart_wb_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd work/simple_uart_wb/.simple_uart_wb
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/simple_uart_wb/.simple_uart_wb: \
work/simple_uart_pkg/.simple_uart_pkg_vhd
work/simple_uart_pkg/.simple_uart_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd work/simple_uart_pkg/.simple_uart_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/simple_uart_pkg/.simple_uart_pkg:
work/wb_simple_uart/.wb_simple_uart_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd work/wb_simple_uart/.wb_simple_uart
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_simple_uart/.wb_simple_uart: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/genram_pkg/.genram_pkg_vhd \
work/simple_uart_pkg/.simple_uart_pkg_vhd
work/xwb_simple_uart/.xwb_simple_uart_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd work/xwb_simple_uart/.xwb_simple_uart
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_simple_uart/.xwb_simple_uart: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/vic_prio_enc/.vic_prio_enc_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd work/vic_prio_enc/.vic_prio_enc
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/vic_prio_enc/.vic_prio_enc:
work/wb_slave_vic/.wb_slave_vic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd work/wb_slave_vic/.wb_slave_vic
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_vic/.wb_slave_vic: \
work/wbgen2_pkg/.wbgen2_pkg_vhd
work/wb_vic/.wb_vic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd work/wb_vic/.wb_vic
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_vic/.wb_vic: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_vic/.xwb_vic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd work/xwb_vic/.xwb_vic
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_vic/.xwb_vic: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/wb_spi/.wb_spi_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd work/wb_spi/.wb_spi
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_spi/.wb_spi: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_spi/.xwb_spi_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd work/xwb_spi/.xwb_spi
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_spi/.xwb_spi: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/sdb_rom/.sdb_rom_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd work/sdb_rom/.sdb_rom
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/sdb_rom/.sdb_rom: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_crossbar/.xwb_crossbar_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd work/xwb_crossbar/.xwb_crossbar
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_crossbar/.xwb_crossbar: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_sdb_crossbar/.xwb_sdb_crossbar_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd work/xwb_sdb_crossbar/.xwb_sdb_crossbar
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_sdb_crossbar/.xwb_sdb_crossbar: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xwb_lm32/.xwb_lm32_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd work/xwb_lm32/.xwb_lm32
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_lm32/.xwb_lm32: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/wb_slave_adapter/.wb_slave_adapter_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd work/wb_slave_adapter/.wb_slave_adapter
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_slave_adapter/.wb_slave_adapter: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wb_xilinx_fpga_loader/.wb_xilinx_fpga_loader: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd \
work/xloader_registers_pkg/.xloader_registers_pkg_vhd
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_xilinx_fpga_loader/.xwb_xilinx_fpga_loader: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/xloader_registers_pkg/.xloader_registers_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd work/xloader_registers_pkg/.xloader_registers_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xloader_registers_pkg/.xloader_registers_pkg: \
work/wbgen2_pkg/.wbgen2_pkg_vhd
work/xloader_wb/.xloader_wb_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd work/xloader_wb/.xloader_wb
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xloader_wb/.xloader_wb: \
work/xloader_registers_pkg/.xloader_registers_pkg_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd
work/xwb_clock_crossing/.xwb_clock_crossing_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd work/xwb_clock_crossing/.xwb_clock_crossing
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_clock_crossing/.xwb_clock_crossing: \
work/wishbone_pkg/.wishbone_pkg_vhd \
work/gencores_pkg/.gencores_pkg_vhd
work/xwb_dma/.xwb_dma_vhd: ../../../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd work/xwb_dma/.xwb_dma
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/xwb_dma/.xwb_dma: \
work/wishbone_pkg/.wishbone_pkg_vhd
work/wbgen2_dpssram/.wbgen2_dpssram_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd work/wbgen2_dpssram/.wbgen2_dpssram
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_dpssram/.wbgen2_dpssram: \
work/wbgen2_pkg/.wbgen2_pkg_vhd
work/wbgen2_eic/.wbgen2_eic_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd work/wbgen2_eic/.wbgen2_eic
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_eic/.wbgen2_eic: \
work/wbgen2_pkg/.wbgen2_pkg_vhd
work/wbgen2_fifo_async/.wbgen2_fifo_async_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd work/wbgen2_fifo_async/.wbgen2_fifo_async
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_fifo_async/.wbgen2_fifo_async: \
work/genram_pkg/.genram_pkg_vhd \
work/wbgen2_pkg/.wbgen2_pkg_vhd
work/wbgen2_fifo_sync/.wbgen2_fifo_sync_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd work/wbgen2_fifo_sync/.wbgen2_fifo_sync
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_fifo_sync/.wbgen2_fifo_sync: \
work/wbgen2_pkg/.wbgen2_pkg_vhd
work/wbgen2_pkg/.wbgen2_pkg_vhd: ../../../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd work/wbgen2_pkg/.wbgen2_pkg
vhpcomp $(VHPCOMP_FLAGS) -work work=./work $<
@mkdir -p $(dir $@) && touch $@
work/wbgen2_pkg/.wbgen2_pkg:
hdl/testbench/wishbone/wb_dma_interface_test/Manifest.py 0 → 100644
View file @ c9217ac1
action = "simulation"
target = "xilinx"
modules = {"local" : [ "../../.." ] };
files = ["wb_dma_interface_tb.vhd"]
hdl/testbench/wishbone/wb_dma_interface_test/fuse.log 0 → 100644
View file @ c9217ac1
Running: /opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse work.wb_dma_interface_tb -intstyle ise -incremental -o isim_proj
ISim O.87xd (signature 0x8ddf5b5d)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Starting static elaboration
WARNING:HDLCompiler:746 - "../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" Line 50: Range is empty (null range)
Completed static elaboration
Fuse Memory Usage: 100984 KB
Fuse CPU Usage: 1090 ms
Compiling package standard
Compiling package std_logic_1164
Compiling package numeric_std
Compiling package genram_pkg
Compiling package wishbone_pkg
FATAL_ERROR:Simulator:CompilerAssert.h:40:1.45 - Internal Compiler Error in file ../src/VhdlDecl.cpp at line 3154 Process will terminate. For technical support on this issue, please open a WebCase with this project attached at http://www.xilinx.com/support.
hdl/testbench/wishbone/wb_dma_interface_test/fuse.xmsgs 0 → 100644
View file @ c9217ac1
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="746" delta="unknown" >"../../../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" Line 50: Range is empty (null range)
</msg>
<msg type="fatal" file="Simulator" num="0" delta="unknown" srcfile="/build/xfndry10/O.87xd/env/Jobs/Simulator/Compiler/common/src/CompilerAssert.h" srcline="40" srcrcs="1.45" >Internal Compiler Error in file <arg fmt="%s" index="1">../src/VhdlDecl.cpp</arg> at line <arg fmt="%d" index="2">3154</arg>
</msg>
</messages>
hdl/testbench/wishbone/wb_dma_interface_test/fuseRelaunch.cmd 0 → 100644
View file @ c9217ac1
"work.wb_dma_interface_tb" -intstyle "ise" -incremental -o "isim_proj"
hdl/testbench/wishbone/wb_dma_interface_test/isim/isim_proj.sim/work/p_3157354128.c 0 → 100644
View file @ c9217ac1
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0x8ddf5b5d */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
extern char *IEEE_P_2592010699;
int work_p_3157354128_sub_1165966991973796083_2599174331(char *t1, int t2)
{
char t4[8];
int t0;
char *t5;
int t6;
int t7;
int t8;
unsigned char t9;
LAB0: t5 = (t4 + 4U);
*((int *)t5) = t2;
t6 = 1;
t7 = 64;
LAB2: if (t6 <= t7)
goto LAB3;
LAB5: t0 = 63;
LAB1: return t0;
LAB3: t8 = xsi_vhdl_pow(2, t6);
t9 = (t8 >= t2);
if (t9 != 0)
goto LAB6;
LAB8:
LAB7:
LAB4: if (t6 == t7)
goto LAB5;
LAB10: t8 = (t6 + 1);
t6 = t8;
goto LAB2;
LAB6: t0 = t6;
goto LAB1;
LAB9: goto LAB7;
LAB11:;
}
char *work_p_3157354128_sub_15107438780999777091_2599174331(char *t1, char *t2, unsigned char t3, int t4)
{
char t5[128];
char t6[16];
char t10[16];
char *t0;
int t7;
int t8;
unsigned int t9;
int t11;
char *t12;
char *t13;
int t14;
unsigned int t15;
char *t16;
char *t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
int t24;
int t25;
int t26;
char *t27;
char *t28;
int t29;
char *t30;
int t31;
int t32;
char *t33;
int t34;
unsigned int t35;
unsigned int t36;
char *t37;
LAB0: t7 = (t4 - 1);
t8 = (0 - t7);
t9 = (t8 * -1);
t9 = (t9 + 1);
t9 = (t9 * 1U);
t11 = (t4 - 1);
t12 = (t10 + 0U);
t13 = (t12 + 0U);
*((int *)t13) = t11;
t13 = (t12 + 4U);
*((int *)t13) = 0;
t13 = (t12 + 8U);
*((int *)t13) = -1;
t14 = (0 - t11);
t15 = (t14 * -1);
t15 = (t15 + 1);
t13 = (t12 + 12U);
*((unsigned int *)t13) = t15;
t13 = (t5 + 4U);
t16 = ((IEEE_P_2592010699) + 4000);
t17 = (t13 + 88U);
*((char **)t17) = t16;
t18 = (char *)alloca(t9);
t19 = (t13 + 56U);
*((char **)t19) = t18;
xsi_type_set_default_value(t16, t18, t10);
t20 = (t13 + 64U);
*((char **)t20) = t10;
t21 = (t13 + 80U);
*((unsigned int *)t21) = t9;
t22 = (t6 + 4U);
*((unsigned char *)t22) = t3;
t23 = (t6 + 5U);
*((int *)t23) = t4;
t24 = (t4 - 1);
t25 = 0;
t26 = t24;
LAB2: if (t25 <= t26)
goto LAB3;
LAB5: t12 = (t13 + 56U);
t16 = *((char **)t12);
t12 = (t10 + 12U);
t9 = *((unsigned int *)t12);
t9 = (t9 * 1U);
t0 = xsi_get_transient_memory(t9);
memcpy(t0, t16, t9);
t17 = (t10 + 0U);
t7 = *((int *)t17);
t19 = (t10 + 4U);
t8 = *((int *)t19);
t20 = (t10 + 8U);
t11 = *((int *)t20);
t21 = (t2 + 0U);
t27 = (t21 + 0U);
*((int *)t27) = t7;
t27 = (t21 + 4U);
*((int *)t27) = t8;
t27 = (t21 + 8U);
*((int *)t27) = t11;
t14 = (t8 - t7);
t15 = (t14 * t11);
t15 = (t15 + 1);
t27 = (t21 + 12U);
*((unsigned int *)t27) = t15;
LAB1: return t0;
LAB3: t27 = (t13 + 56U);
t28 = *((char **)t27);
t27 = (t10 + 0U);
t29 = *((int *)t27);
t30 = (t10 + 8U);
t31 = *((int *)t30);
t32 = (t25 - t29);
t15 = (t32 * t31);
t33 = (t10 + 4U);
t34 = *((int *)t33);
xsi_vhdl_check_range_of_index(t29, t34, t31, t25);
t35 = (1U * t15);
t36 = (0 + t35);
t37 = (t28 + t36);
*((unsigned char *)t37) = t3;
LAB4: if (t25 == t26)
goto LAB5;
LAB6: t7 = (t25 + 1);
t25 = t7;
goto LAB2;
LAB7:;
}
extern void work_p_3157354128_init()
{
static char *se[] = {(void *)work_p_3157354128_sub_1165966991973796083_2599174331,(void *)work_p_3157354128_sub_15107438780999777091_2599174331};
xsi_register_didat("work_p_3157354128", "isim/isim_proj.sim/work/p_3157354128.didat");
xsi_register_subprogram_executes(se);
}
hdl/testbench/wishbone/wb_dma_interface_test/isim/precompiled.exe.sim/ieee/p_1242562249.c 0 → 100644
View file @ c9217ac1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/wishbone/wb_dma_interface_test/isim/precompiled.exe.sim/ieee/p_2592010699.c 0 → 100644
View file @ c9217ac1
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/testbench/wishbone/wb_dma_interface_test/run.do 0 → 100644
View file @ c9217ac1
make
vsim -L XilinxCoreLib -L secureip -L unisim work.main -voptargs="+acc"
radix -hexadecimal
do wave.do
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run 100us
wave zoomfull
\ No newline at end of file
hdl/testbench/wishbone/wb_dma_interface_test/wave.do 0 → 100644
View file @ c9217ac1
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /main/clk_sys
add wave -noupdate /main/DUT/U_CPU/dwb_o
add wave -noupdate /main/DUT/U_CPU/dwb_i
add wave -noupdate /main/DUT/U_Intercon/granted
add wave -noupdate /main/DUT/U_CPU/gen_profile_medium/U_Wrapped_LM32/D_STB_O
add wave -noupdate /main/DUT/U_CPU/gen_profile_medium/U_Wrapped_LM32/D_ACK_I
add wave -noupdate /main/DUT/U_CPU/data_was_busy
add wave -noupdate /main/DUT/U_CPU/data_addr_reg
add wave -noupdate /main/DUT/U_CPU/data_remaining
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2672526 ps} 0}
configure wave -namecolwidth 350
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {2262366 ps} {3082686 ps}
hdl/testbench/wishbone/wb_dma_interface_test/wb_dma_interface_tb.vhd 0 → 100644
View file @ c9217ac1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.custom_wishbone_pkg.all;
entity wb_dma_interface_tb is
end wb_dma_interface_tb;
architecture sim of wb_dma_interface_tb is
-- 100.00 MHz clock
constant c_data_clk_period : time := 10.00 ns;
-- 200.00 MHz clock
constant c_dma_clk_period : time := 5.00 ns;
constant c_sim_time : time := 10000.00 ns;
signal g_end_simulation : boolean := false; -- Set to true to halt the simulation
signal arst_n_i : std_logic;
signal dma_clk_i : std_logic := '0';
signal data_clk_i : std_logic := '0';
signal dma_slave_i : t_wishbone_slave_in;
signal dma_slave_o : t_wishbone_slave_out;
signal data_i : std_logic_vector(c_wishbone_data_width-1 downto 0);
signal data_valid_i : std_logic;
signal data_ready_o : std_logic;
signal capture_ctl_i : std_logic_vector(c_wishbone_data_width-1 downto 0);
signal dma_complete_o : std_logic;
signal dma_ovf_o : std_logic;
begin -- sim
p_data_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_data_clk_period/2;
data_clk_i <= not data_clk_i;
wait for c_data_clk_period/2;
data_clk_i <= not data_clk_i;
end loop;
wait; -- simulation stops here
end process;
p_dma_clk_gen : process
begin
while g_end_simulation = false loop
wait for c_dma_clk_period/2;
dma_clk_i <= not dma_clk_i;
wait for c_dma_clk_period/2;
dma_clk_i <= not dma_clk_i;
end loop;
wait; -- simulation stops here
end process;
p_main_simulation : process
begin
wait for c_sim_time;
g_end_simulation <= true;
wait;
end process;
cmp_dut : xwb_dma_interface
port map(
-- Asynchronous Reset signal
arst_n_i => arst_n_i,
-- Write Domain Clock
dma_clk_i => dma_clk_i,
--dma_valid_o : out std_logic;
--dma_data_o : out std_logic_vector(C_NBITS_DATA_INPUT-1 downto 0);
--dma_be_o : out std_logic_vector(C_NBITS_DATA_INPUT/8 - 1 downto 0);
--dma_last_o : out std_logic;
--dma_ready_i : in std_logic;
-- Slave Data Flow port
dma_slave_i => dma_slave_i,
dma_slave_o => dma_slave_o,
-- Slave Data Input Port
--data_slave_i : in t_wishbone_slave_in;
--data_slave_o : out t_wishbone_slave_out;
data_clk_i => data_clk_i,
data_i => data_i,
data_valid_i => data_valid_i,
data_ready_o => data_ready_o,
-- Slave control port. use wbgen2 tool or not if it is simple.
--control_slave_i : in t_wishbone_slave_in;
--control_slave_o : out t_wishbone_slave_out;
capture_ctl_i => capture_ctl_i,
dma_complete_o => dma_complete_o,
dma_ovf_o => dma_ovf_o
-- Debug Signals
--dma_debug_clk_o : out std_logic;
--dma_debug_data_o : out std_logic_vector(255 downto 0);
--dma_debug_trigger_o : out std_logic_vector(15 downto 0)
);
end sim;
hdl/testbench/wishbone/wb_dma_interface_test/xilinxsim.ini 0 → 100644
View file @ c9217ac1
-- Default lib mapping for Simulator
std=$XILINX/vhdl/hdp/lin64/std
ieee=$XILINX/vhdl/hdp/lin64/ieee
ieee_proposed=$XILINX/vhdl/hdp/lin64/ieee_proposed
vl=$XILINX/vhdl/hdp/lin64/vl
synopsys=$XILINX/vhdl/hdp/lin64/synopsys
simprim=$XILINX/vhdl/hdp/lin64/simprim
unisim=$XILINX/vhdl/hdp/lin64/unisim
unimacro=$XILINX/vhdl/hdp/lin64/unimacro
aim=$XILINX/vhdl/hdp/lin64/aim
cpld=$XILINX/vhdl/hdp/lin64/cpld
pls=$XILINX/vhdl/hdp/lin64/pls
xilinxcorelib=$XILINX/vhdl/hdp/lin64/xilinxcorelib
aim_ver=$XILINX/verilog/hdp/lin64/aim_ver
cpld_ver=$XILINX/verilog/hdp/lin64/cpld_ver
simprims_ver=$XILINX/verilog/hdp/lin64/simprims_ver
unisims_ver=$XILINX/verilog/hdp/lin64/unisims_ver
uni9000_ver=$XILINX/verilog/hdp/lin64/uni9000_ver
unimacro_ver=$XILINX/verilog/hdp/lin64/unimacro_ver
xilinxcorelib_ver=$XILINX/verilog/hdp/lin64/xilinxcorelib_ver
secureip=$XILINX/verilog/hdp/lin64/xip/secureip
work=work
fifo_generator_v6_1=fifo_generator_v6_1
hdl/top/ml_605/dbe_bpm/Manifest.py 0 → 100644
View file @ c9217ac1
files = [ "dbe_demo_top.vhd", "sys_pll.vhd", "clk_gen.vhd", "dbe_demo_top.ucf" ];
modules = { "local" : ["../../.." ] };
hdl/top/ml_605/dbe_bpm/clk_gen.vhd 0 → 100644
View file @ c9217ac1
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end clk_gen;
architecture syn of clk_gen is
-- Internal clock signal
signal s_sys_clk : std_logic;
begin
-- IBUFGDS: Differential Global Clock Input Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cpm_ibufgds_clk_gen : IBUFGDS
generic map (
DIFF_TERM => FALSE, -- Differential Termination
IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => s_sys_clk, -- Clock buffer output
I => sys_clk_p_i, -- Diff_p clock buffer input (connect directly to top-level port)
IB => sys_clk_n_i -- Diff_n clock buffer input (connect directly to top-level port)
);
-- BUFG: Global Clock Buffer
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
cmp_bufg_clk_gen : BUFG
port map (
O => sys_clk_o, -- 1-bit output: Clock buffer output
I => s_sys_clk -- 1-bit input: Clock buffer input
);
end syn;
hdl/top/ml_605/dbe_bpm/dbe_bpm_top.ucf 0 → 100644
View file @ c9217ac1
NET "buttons_i[0]" LOC = D22;
NET "buttons_i[1]" LOC = C22;
NET "buttons_i[2]" LOC = L21;
NET "buttons_i[3]" LOC = L20;
NET "buttons_i[4]" LOC = C18;
NET "buttons_i[5]" LOC = B18;
NET "buttons_i[6]" LOC = K22;
NET "buttons_i[7]" LOC = K21;
NET "leds_o[0]" LOC = AC22;
NET "leds_o[1]" LOC = AC24;
NET "leds_o[2]" LOC = AE22;
NET "leds_o[3]" LOC = AE23;
NET "leds_o[4]" LOC = AB23;
NET "leds_o[5]" LOC = AG23;
NET "leds_o[6]" LOC = AE24;
NET "leds_o[7]" LOC = AD24;
NET "buttons_i[7]" IOSTANDARD = LVCMOS25;
NET "buttons_i[6]" IOSTANDARD = LVCMOS25;
NET "buttons_i[5]" IOSTANDARD = LVCMOS25;
NET "buttons_i[4]" IOSTANDARD = LVCMOS25;
NET "buttons_i[3]" IOSTANDARD = LVCMOS25;
NET "buttons_i[2]" IOSTANDARD = LVCMOS25;
NET "buttons_i[1]" IOSTANDARD = LVCMOS25;
NET "buttons_i[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[7]" IOSTANDARD = LVCMOS25;
NET "leds_o[7]" DRIVE = 12;
NET "leds_o[7]" SLEW = SLOW;
NET "leds_o[6]" IOSTANDARD = LVCMOS25;
NET "leds_o[6]" DRIVE = 12;
NET "leds_o[6]" SLEW = SLOW;
NET "leds_o[5]" IOSTANDARD = LVCMOS25;
NET "leds_o[5]" DRIVE = 12;
NET "leds_o[5]" SLEW = SLOW;
NET "leds_o[4]" IOSTANDARD = LVCMOS25;
NET "leds_o[4]" DRIVE = 12;
NET "leds_o[4]" SLEW = SLOW;
NET "leds_o[3]" IOSTANDARD = LVCMOS25;
NET "leds_o[3]" DRIVE = 12;
NET "leds_o[3]" SLEW = SLOW;
NET "leds_o[2]" IOSTANDARD = LVCMOS25;
NET "leds_o[2]" DRIVE = 12;
NET "leds_o[2]" SLEW = SLOW;
NET "leds_o[1]" IOSTANDARD = LVCMOS25;
NET "leds_o[1]" DRIVE = 12;
NET "leds_o[1]" SLEW = SLOW;
NET "leds_o[0]" IOSTANDARD = LVCMOS25;
NET "leds_o[0]" DRIVE = 12;
NET "leds_o[0]" SLEW = SLOW;
NET "sys_clk_p_i" IOSTANDARD = LVDS_25;
NET "sys_clk_n_i" IOSTANDARD = LVDS_25;
# PlanAhead Generated physical constraints
NET "sys_clk_n_i" LOC = H9;
NET "sys_clk_p_i" LOC = J9;
hdl/top/ml_605/dbe_bpm/dbe_bpm_top.vhd 0 → 100755
View file @ c9217ac1
-- Example Design based on genral-cores top example design
-- from OHWR repositories http://www.ohwr.org/projects/general-cores
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.wishbone_pkg.all;
use work.gencores_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity dbe_bpm_top is
port(
-----------------------------------------
-- Clocking pins
-----------------------------------------
--clk100_i : in std_logic;
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
-----------------------------------------
-- Button pins
-----------------------------------------
buttons_i : in std_logic_vector(7 downto 0);
-----------------------------------------
-- User LEDs
-----------------------------------------
leds_o : out std_logic_vector(7 downto 0)
);
end dbe_bpm_top;
architecture rtl of dbe_bpm_top is
-- Simple GPIO interface device
constant c_xwb_gpio32_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF", -- Max of 256 pins. Max of 8 32-bit registers
product => (
vendor_id => x"0000000000000651", -- GSI
device_id => x"35aa6b95",
version => x"00000001",
date => x"20120305",
name => "GSI_GPIO_32 ")));
-- Simple IRQ manager interface device
constant c_xwb_irqmngr_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"00",
wbd_endian => c_sdb_endian_big,
wbd_width => x"7", -- 8/16/32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"0000000000000007", -- Two 4 byte registers
product => (
vendor_id => x"1000000000001215", -- LNLS
device_id => x"15ff65e1",
version => x"00000001",
date => x"20120903", -- YY/MM/DD ??
name => "LNLS_IRQMNGR ")));
-- Top crossbar layout
constant c_slaves : natural := 5; -- LED, Button, Dual-port memory, DMA control port
constant c_masters : natural := 4; -- LM32 master. Data + Instruction, DMA read+write master
constant c_dpram_size : natural := 16384; -- in 32-bit words (64KB)
-- GPIO num pins
constant c_leds_num_pins : natural := 8;
constant c_buttons_num_pins : natural := 8;
-- Counter width. It willl count up to 2^27 clock cycles
--constant c_counter_width : natural := 27;
-- WB SDB (Self describing bus) layout
constant c_layout : t_sdb_record_array(c_slaves-1 downto 0) :=
(0 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"00000000"), -- 64KB RAM
1 => f_sdb_embed_device(f_xwb_dpram(c_dpram_size), x"10000000"), -- Second port to the same memory
2 => f_sdb_embed_device(c_xwb_dma_sdb, x"20000400") -- DMA control port
3 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000500"), -- GPIO LED
4 => f_sdb_embed_device(c_xwb_gpio32_sdb, x"20000600"), -- GPIO Button
--4 => f_sdb_embed_device(c_xwb_irqmngr_sdb, x"00100600") -- IRQ_MNGR
);
-- Self Describing Bus ROM Address. It is addressed as slave as well.
constant c_sdb_address : t_wishbone_address := x"20000000";
-- Crossbar master/slave arrays
signal cbar_slave_i : t_wishbone_slave_in_array (c_masters-1 downto 0);
signal cbar_slave_o : t_wishbone_slave_out_array(c_masters-1 downto 0);
signal cbar_master_i : t_wishbone_master_in_array(c_slaves-1 downto 0);
signal cbar_master_o : t_wishbone_master_out_array(c_slaves-1 downto 0);
-- LM32 signals
signal clk_sys : std_logic;
signal lm32_interrupt : std_logic_vector(31 downto 0);
signal lm32_rstn : std_logic;
-- Global clock and reset signals
signal locked : std_logic;
signal clk_sys_rstn : std_logic;
-- Only one clock domain
signal reset_clks : std_logic_vector(0 downto 0);
signal reset_rstn : std_logic_vector(0 downto 0);
-- Global Clock Single ended
signal sys_clk_gen : std_logic;
-- GPIO LED signals
signal gpio_slave_led_o : t_wishbone_slave_out;
signal gpio_slave_led_i : t_wishbone_slave_in;
signal s_leds : std_logic_vector(c_leds_num_pins-1 downto 0);
-- signal leds_gpio_dummy_in : std_logic_vector(c_leds_num_pins-1 downto 0);
-- GPIO Button signals
signal gpio_slave_button_o : t_wishbone_slave_out;
signal gpio_slave_button_i : t_wishbone_slave_in;
-- IRQ manager signals
--signal gpio_slave_irqmngr_o : t_wishbone_slave_out;
--signal gpio_slave_irqmngr_i : t_wishbone_slave_in;
-- LEDS, button and irq manager signals
--signal r_leds : std_logic_vector(7 downto 0);
--signal r_reset : std_logic;
-- Counter signal
--signal s_counter : unsigned(c_counter_width-1 downto 0);
-- 100MHz period or 1 second
--constant s_counter_full : integer := 100000000;
-- Chipscope signals
signal clk_25mhz : std_logic;
signal CONTROL : std_logic_vector(35 downto 0);
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
---------------------------
-- Components --
---------------------------
-- Clock generation
component clk_gen is
port(
sys_clk_p_i : in std_logic;
sys_clk_n_i : in std_logic;
sys_clk_o : out std_logic
);
end component;
-- Xilinx Megafunction
component sys_pll is
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end component;
-- Xilinx Chipscope Controller
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector(35 downto 0)
);
end component;
-- Xilinx Chipscope Logic Analyser
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0)
);
end component;
begin
-- Clock generation
cmp_clk_gen : clk_gen
port map (
sys_clk_p_i => sys_clk_p_i,
sys_clk_n_i => sys_clk_n_i,
sys_clk_o => sys_clk_gen
);
-- Obtain core locking!
cmp_sys_pll_inst : sys_pll
port map (
rst_i => '0',
clk_i => sys_clk_gen,
clk0_o => clk_sys, -- 100MHz locked clock
clk1_o => clk_25mhz, -- 25MHz locked clock
locked_o => locked -- '1' when the PLL has locked
);
-- Reset synchronization. Hold reset line until few locked cycles hava passed
cmp_reset : gc_reset
port map(
free_clk_i => sys_clk_gen,
locked_i => locked,
clks_i => reset_clks,
rstn_o => reset_rstn
);
reset_clks(0) <= clk_sys;
clk_sys_rstn <= reset_rstn(0);
-- The top-most Wishbone B.4 crossbar
cmp_interconnect : xwb_sdb_crossbar
generic map(
g_num_masters => c_masters,
g_num_slaves => c_slaves,
g_registered => true,
g_wraparound => false, -- Should be true for nested buses
g_layout => c_layout,
g_sdb_addr => c_sdb_address
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Master connections (INTERCON is a slave)
slave_i => cbar_slave_i,
slave_o => cbar_slave_o,
-- Slave connections (INTERCON is a master)
master_i => cbar_master_i,
master_o => cbar_master_o
);
-- The LM32 is master 0+1
lm32_rstn <= clk_sys_rstn; -- and not r_reset;
cmp_lm32 : xwb_lm32
generic map(
g_profile => "medium_icache_debug"
) -- Including JTAG and I-cache (no divide)
port map(
clk_sys_i => clk_sys,
rst_n_i => lm32_rstn,
irq_i => lm32_interrupt,
dwb_o => cbar_slave_i(0), -- Data bus
dwb_i => cbar_slave_o(0),
iwb_o => cbar_slave_i(1), -- Instruction bus
iwb_i => cbar_slave_o(1)
);
-- Interrupts 31 downto 1 disabled for now.
-- Interrupt '0' is DMA completion.
lm32_interrupt(31 downto 1) <= (others => '0');
-- A DMA controller is master 2+3, slave 2, and interrupt 0
cmp_dma : xwb_dma
port map(
clk_i => clk_sys,
rst_n_i => clk_sys_rstn,
slave_i => cbar_master_o(2),
slave_o => cbar_master_i(2),
r_master_i => cbar_slave_o(2),
r_master_o => cbar_slave_i(2),
w_master_i => cbar_slave_o(3),
w_master_o => cbar_slave_i(3),
interrupt_o => lm32_interrupt(0)
);
-- Slave 0+1 is the RAM. Load a input file containing a simple led blink program!
cmp_ram : xwb_dpram
generic map(
g_size => c_dpram_size, -- must agree with sw/target/lm32/ram.ld:LENGTH / 4
g_init_file => "../../top/ml_605/dbe_bpm/sw/main.ram",
g_must_have_init_file => true,
g_slave1_interface_mode => PIPELINED,
g_slave2_interface_mode => PIPELINED,
g_slave1_granularity => BYTE,
g_slave2_granularity => BYTE
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- First port connected to the crossbar
slave1_i => cbar_master_o(0),
slave1_o => cbar_master_i(0),
-- Second port connected to the crossbar
slave2_i => cbar_master_o(1),
slave2_o => cbar_master_i(1)
--slave2_i => cc_dummy_slave_in, -- CYC always low
--slave2_o => open
);
-- Slave 3 is the example LED driver
cmp_leds : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE,
g_num_pins => c_leds_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(3),
slave_o => cbar_master_i(3),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => s_leds,
--gpio_out_o => open,
gpio_in_i => s_leds,
gpio_oen_o => open
);
--leds_o <= x"55";
leds_o <= s_leds;
--p_test_leds : process (clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- if clk_sys_rstn = '0' then
-- s_counter <= (others => '0');
-- s_leds <= x"55";
-- else
-- if (s_counter = s_counter_full-1) then
-- s_counter <= (others => '0');
-- s_leds <= s_leds(c_leds_num_pins-2 downto 0) & s_leds(c_leds_num_pins-1);
-- else
-- s_counter <= s_counter + 1;
-- end if;
-- end if;
-- end if;
--end process;
-- Slave 1 is the example LED driver
--gpio_slave_led_i <= cbar_master_o(1);
--cbar_master_i(1) <= gpio_slave_led_o;
--leds_o <= not r_leds;
-- There is a tool called 'wbgen2' which can autogenerate a Wishbone
-- interface and C header file, but this is a simple example.
--gpio : process(clk_sys)
--begin
-- if rising_edge(clk_sys) then
-- It is vitally important that for each occurance of
-- (cyc and stb and not stall) there is (ack or rty or err)
-- sometime later on the bus.
--
-- This is an easy solution for a device that never stalls:
-- gpio_slave_led_o.ack <= gpio_slave_led_i.cyc and gpio_slave_led_i.stb;
-- Detect a write to the register byte
-- if gpio_slave_led_i.cyc = '1' and gpio_slave_led_i.stb = '1' and
-- gpio_slave_led_i.we = '1' and gpio_slave_led_i.sel(0) = '1' then
-- Register 0x0 = LEDs, 0x4 = CPU reset
-- if gpio_slave_led_i.adr(2) = '0' then
-- r_leds <= gpio_slave_led_i.dat(7 downto 0);
-- else
-- r_reset <= gpio_slave_led_i.dat(0);
-- end if;
-- end if;
-- Read to the register byte
-- if gpio_slave_led_i.adr(2) = '0' then
-- gpio_slave_led_o.dat(31 downto 8) <= (others => '0');
-- gpio_slave_led_o.dat(7 downto 0) <= r_leds;
-- else
-- gpio_slave_led_o.dat(31 downto 2) <= (others => '0');
-- gpio_slave_led_o.dat(0) <= r_reset;
-- end if;
--end if;
--end process;
--gpio_slave_led_o.int <= '0';
--gpio_slave_led_o.err <= '0';
--gpio_slave_led_o.rty <= '0';
--gpio_slave_led_o.stall <= '0'; -- This simple example is always ready
-- Slave 4 is the example Button driver
cmp_buttons : xwb_gpio_port
generic map(
--g_interface_mode => CLASSIC;
g_address_granularity => BYTE;
g_num_pins => c_buttons_num_pins,
g_with_builtin_tristates => false
)
port map(
clk_sys_i => clk_sys,
rst_n_i => clk_sys_rstn,
-- Wishbone
slave_i => cbar_master_o(4),
slave_o => cbar_master_i(4),
desc_o => open, -- Not implemented
--gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o => open,
gpio_in_i => buttons_i,
gpio_oen_o => open
);
-- Xilinx Chipscope
cmp_chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL
);
cmp_chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_25mhz,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3
);
-- DMA Write Master output
TRIG0 <= cbar_slave_i(3).dat(31 downto 0);
-- DMA Read Master input
TRIG1 <= cbar_slave_o(2).dat(31 downto 0);
-- Global reset
TRIG2(0) <= clk_sys_rstn;
TRIG2(31 downto 1) <= (others => '0');
TRIG3(31 downto 0) <= (others => '0');
end rtl;
hdl/top/ml_605/dbe_bpm/sw/Makefile 0 → 100644
View file @ c9217ac1
PLATFORM = lm32
OBJS_WRC = main.o gpio.o dma.o target/lm32/crt0.o
CROSS_COMPILE ?= /opt/gcc-lm32/bin/lm32-elf-
CFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -I.
LDFLAGS_PLATFORM = -mmultiply-enabled -mbarrel-shift-enabled -nostdlib -T target/lm32/ram.ld
CC=$(CROSS_COMPILE)gcc
OBJCOPY=$(CROSS_COMPILE)objcopy
OBJDUMP=$(CROSS_COMPILE)objdump
CFLAGS= $(CFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Os -Iinclude $(PTPD_CFLAGS) -Iptp-noposix/PTPWRd
LDFLAGS= $(LDFLAGS_PLATFORM) -ffunction-sections -fdata-sections -Os -Iinclude
SIZE = $(CROSS_COMPILE)size
OBJS=$(OBJS_PLATFORM) $(OBJS_WRC) $(OBJS_PTPD) $(OBJS_PTPD_FREE)
OUTPUT=main
all: $(OBJS)
$(SIZE) -t $(OBJS)
${CC} -o $(OUTPUT).elf $(OBJS) $(LDFLAGS)
${OBJCOPY} -O binary $(OUTPUT).elf $(OUTPUT).bin
${OBJDUMP} -d $(OUTPUT).elf > $(OUTPUT)_disasm.S
./genraminit $(OUTPUT).bin 0 > $(OUTPUT).ram
clean:
rm -f $(OBJS) $(OUTPUT).elf $(OUTPUT).bin $(OUTPUT).ram $(OUTPUT)_disasm.S
%.o: %.c
${CC} $(CFLAGS) $(PTPD_CFLAGS) $(INCLUDE_DIR) $(LIB_DIR) -c $^ -o $@
hdl/top/ml_605/dbe_bpm/sw/board.h 0 → 100644
View file @ c9217ac1
#ifndef __BOARD_H
#define __BOARD_H
/* Automate the address peripheral discover */
#define BASE_DMA_ADDR 0x20000400
#define BASE_LEDS_ADDR 0x20000500
#define BASE_BUTTONS_ADDR 0x20000600
static inline int delay(int x)
{
while(x--) asm volatile("nop");
}
#endif
hdl/top/ml_605/dbe_bpm/sw/dma.c 0 → 100644
View file @ c9217ac1
#include "dma.h"
/* DMA user interface definition */
static inline int read_is_addr(dma_t dma)
{
return dma->RD_ADDR;
}
static inline void write_is_addr(dma_t dma, int addr)
{
dma->WR_ADDR = (uint32_t) addr;
}
static inline int read_strd(dma_t dma)
{
return dma->RD_STRD;
}
static inline void write_strd(dma_t dma, int strd)
{
dma->WR_STRD = (uint32_t) strd;
}
static inline int read_tr_count(dma_t dma)
{
return dma->TR_COUNT;
}
#endif
hdl/top/ml_605/dbe_bpm/sw/genraminit.c 0 → 100644
View file @ c9217ac1
#include <stdio.h>
#include <stdlib.h>
int main(int argc, char *argv[])
{
if(argc < 3) return -1;
FILE *f = fopen(argv[1],"rb");
if(!f) return -1;
unsigned char x[4];
int i=0;
int n = atoi(argv[2]);
while(!feof(f)){
fread(x,1,4,f);
printf("write %x %02X%02X%02X%02X\n", i++, x[0],x[1],x[2],x[3]);
}
for(;i<n;){
printf("write %x %02X%02X%02X%02X\n", i++, 0,0,0,0);
}
fclose(f);
return 0;
}
hdl/top/ml_605/dbe_bpm/sw/gpio.c 0 → 100644
View file @ c9217ac1
#include "gpio.h"
/* GPIO user interface definition */
static inline void gpio_out(gpio_t gpio, int pin, int val)
{
if(val)
gpio->SODR = (1<<pin);
else
gpio->CODR = (1<<pin);
}
static inline void gpio_dir(gpio_t gpio, int pin, int val)
{
if(val)
gpio->DDR |= (1<<pin);
else
gpio->DDR &= ~(1<<pin);
}
static inline int gpio_in(gpio_t gpio, int pin)
{
return gpio->PSR & (1<<pin) ? 1 : 0;
}
hdl/top/ml_605/dbe_bpm/sw/include/board.h 0 → 100644
View file @ c9217ac1
#ifndef __BOARD_H
#define __BOARD_H
/* Automate the address peripheral discover */
#define BASE_DMA_ADDR 0x20000400
#define BASE_LEDS_ADDR 0x20000500
#define BASE_BUTTONS_ADDR 0x20000600
static inline int delay(int x)
{
while(x--) asm volatile("nop");
}
#endif
hdl/top/ml_605/dbe_bpm/sw/include/dma.h 0 → 100644
View file @ c9217ac1
#ifndef __DMA_H
#define __DMA_H
#include "inttypes.h"
#include "board.h"
/*
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_dma.vhd
*/
struct DMA_WB
{
uint32_t RD_ADDR; /* Read issue address register */
uint32_t WR_ADDR; /* Write issue address register */
uint32_t RD_STRD; /* Read stride */
uint32_t WR_STRD; /* Write stride */
uint32_t TR_COUNT /* Transfer count */
};
typedef volatile struct DMA_WB * dma_t;
/* DMA user interface */
static inline int read_is_addr(dma_t dma);
static inline void write_is_addr(dma_t dma, int addr);
static inline int read_strd(dma_t dma);
static inline void write_strd(dma_t dma, int strd);
static inline int read_tr_count(dma_t dma);
#endif
hdl/top/ml_605/dbe_bpm/sw/include/gpio.h 0 → 100644
View file @ c9217ac1
#ifndef __GPIO_H
#define __GPIO_H
#include "inttypes.h"
#include "board.h"
/*
This structure must conform to what it is specified in the
FPGA software-acessible registers. See general-cores/cores/wishbone/wb_gpio_port.vhd
*/
struct GPIO_WB
{
uint32_t CODR; /* Clear output register */
uint32_t SODR; /* Set output register */
uint32_t DDR; /* Data direction register (1 means out) */
uint32_t PSR; /* Pin state register */
};
typedef volatile struct GPIO_WB * gpio_t;
//static volatile struct GPIO_WB *__gpio = (volatile struct GPIO_WB *) BASE_GPIO;
/* GPIO user interface */
static inline void gpio_out(gpio_t gpio, int pin, int val);
static inline void gpio_dir(gpio_t gpio, int pin, int val);
static inline int gpio_in(gpio_t gpio, int pin);
#endif
hdl/top/ml_605/dbe_bpm/sw/include/inttypes.h 0 → 100644
View file @ c9217ac1
#ifndef __WRAPPED_INTTYPES_H
#define __WRAPPED_INTTYPES_H
typedef unsigned char uint8_t;
typedef unsigned short uint16_t;
typedef unsigned int uint32_t;
typedef signed long long uint64_t;
typedef signed char int8_t;
typedef signed short int16_t;
typedef signed int int32_t;
typedef signed long long int64_t;
#endif
hdl/top/ml_605/dbe_bpm/sw/main.c 0 → 100644
View file @ c9217ac1
#include "gpio.h"
#include "dma.h"
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz.
* Sleep 0.2 second.
*/
#define LED_DELAY (100000000/4/5)
//#define LED_DELAY 100000000
/* Placeholder for IRQ vector */
void _irq_entry(void){}
int main(void)
{
int i, j;
gpio_t leds = (volatile struct GPIO_WB *) BASE_LEDS_ADDR;
gpio_t buttons = (volatile struct GPIO_WB *) BASE_BUTTONS_ADDR;
dma_t buttons = (volatile struct DMA_WB *) BASE_DMA_ADDR;
while (1) {
/* Rotate the LEDs */
for (i = 0; i < 8; ++i) {
// Set led at position i
gpio_out(leds, i, 1);
/* Each loop iteration takes 4 cycles.
* It runs at 100MHz.
* Sleep 0.2 second.
*/
delay(LED_DELAY);
// Clear led at position i
gpio_out(leds, i, 0);
}
/* Rotate the LEDs */
}
return 0;
}
hdl/top/ml_605/dbe_bpm/sw/target/lm32/crt0.S 0 → 100755
View file @ c9217ac1
/****************************************************************************
**
** Name: crt0ram.S
**
** Description:
** Implements boot-code that calls LatticeDDInit (that calls main())
** Implements exception handlers (actually, redirectors)
**
** $Revision: $
**
** Disclaimer:
**
** This source code is intended as a design reference which
** illustrates how these types of functions can be implemented. It
** is the user's responsibility to verify their design for
** consistency and functionality through the use of formal
** verification methods. Lattice Semiconductor provides no warranty
** regarding the use or functionality of this code.
**
** --------------------------------------------------------------------
**
** Lattice Semiconductor Corporation
** 5555 NE Moore Court
** Hillsboro, OR 97214
** U.S.A
**
** TEL: 1-800-Lattice (USA and Canada)
** (503)268-8001 (other locations)
**
** web: http://www.latticesemi.com
** email: techsupport@latticesemi.com
**
** --------------------------------------------------------------------------
**
** Change History (Latest changes on top)
**
** Ver Date Description
** --------------------------------------------------------------------------
** 3.8 Apr-15-2011 Added __MICO_USER_<handler>_HANDLER__ preprocessor to
** allow customers to implement their own handlers for:
** DATA_ABORT, INST_ABORT
**
** 3.1 Jun-18-2008 Added __MICO_NO_INTERRUPTS__ preprocessor
** option to exclude invoking MicoISRHandler
** to reduce code-size in apps that don't use
** interrupts
**
** 3.0 Mar-25-2008 Added Header
**
**---------------------------------------------------------------------------
*****************************************************************************/
/*
* LatticeMico32 C startup code.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/* From include/sys/signal.h */
#define SIGINT 2 /* interrupt */
#define SIGTRAP 5 /* trace trap */
#define SIGFPE 8 /* arithmetic exception */
#define SIGSEGV 11 /* segmentation violation */
//#define MICO32_FULL_CONTEXT_SAVE_RESTORE
/* Exception handlers - Must be 32 bytes long. */
.section .boot, "ax", @progbits
.global _start
_start:
.global _reset_handler
.type _reset_handler, @function
_reset_handler:
xor r0, r0, r0
wcsr IE, r0
wcsr IM, r0
mvhi r1, hi(_reset_handler)
ori r1, r1, lo(_reset_handler)
wcsr EBA, r1
calli _crt0
nop
.size _reset_handler, .-_reset_handler
.extern _irq_entry
.org 0xc0
.global _interrupt_handler
.type _interrupt_handler, @function
_interrupt_handler:
sw (sp+0), ra
calli _save_all
mvi r1, SIGINT
#ifndef __MICO_NO_INTERRUPTS__
calli _irq_entry
#else
wcsr IE, r0
#endif
bi _restore_all_and_return
nop
nop
nop
.org 0x100
.global _crt0
.type _crt0, @function
_crt0:
/* Clear r0 */
xor r0, r0, r0
/* Setup stack and global pointer */
mvhi sp, hi(_fstack)
ori sp, sp, lo(_fstack)
mvhi gp, hi(_gp)
ori gp, gp, lo(_gp)
mvhi r1, hi(_fbss)
ori r1, r1, lo(_fbss)
mvi r2, 0
mvhi r3, hi(_ebss)
ori r3, r3, lo(_ebss)
sub r3, r3, r1
calli memset
mvi r1, 0
mvi r2, 0
mvi r3, 0
calli main
loopf:
bi loopf
.global _save_all
.type _save_all, @function
_save_all:
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
addi sp, sp, -128
#else
addi sp, sp, -60
#endif
sw (sp+4), r1
sw (sp+8), r2
sw (sp+12), r3
sw (sp+16), r4
sw (sp+20), r5
sw (sp+24), r6
sw (sp+28), r7
sw (sp+32), r8
sw (sp+36), r9
sw (sp+40), r10
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
sw (sp+44), r11
sw (sp+48), r12
sw (sp+52), r13
sw (sp+56), r14
sw (sp+60), r15
sw (sp+64), r16
sw (sp+68), r17
sw (sp+72), r18
sw (sp+76), r19
sw (sp+80), r20
sw (sp+84), r21
sw (sp+88), r22
sw (sp+92), r23
sw (sp+96), r24
sw (sp+100), r25
sw (sp+104), r26
sw (sp+108), r27
sw (sp+120), ea
sw (sp+124), ba
/* ra and sp need special handling, as they have been modified */
lw r1, (sp+128)
sw (sp+116), r1
mv r1, sp
addi r1, r1, 128
sw (sp+112), r1
#else
sw (sp+52), ea
sw (sp+56), ba
/* ra and sp need special handling, as they have been modified */
lw r1, (sp+60)
sw (sp+48), r1
mv r1, sp
addi r1, r1, 60
sw (sp+44), r1
#endif
// xor r1, r1, r1
// wcsr ie, r1
ret
.size _save_all, .-_save_all
.global _restore_all_and_return
.type _restore_all_and_return, @function
/* Restore all registers and return from exception */
_restore_all_and_return:
// addi r1, r0, 2
// wcsr ie, r1
lw r1, (sp+4)
lw r2, (sp+8)
lw r3, (sp+12)
lw r4, (sp+16)
lw r5, (sp+20)
lw r6, (sp+24)
lw r7, (sp+28)
lw r8, (sp+32)
lw r9, (sp+36)
lw r10, (sp+40)
#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
lw r11, (sp+44)
lw r12, (sp+48)
lw r13, (sp+52)
lw r14, (sp+56)
lw r15, (sp+60)
lw r16, (sp+64)
lw r17, (sp+68)
lw r18, (sp+72)
lw r19, (sp+76)
lw r20, (sp+80)
lw r21, (sp+84)
lw r22, (sp+88)
lw r23, (sp+92)
lw r24, (sp+96)
lw r25, (sp+100)
lw r26, (sp+104)
lw r27, (sp+108)
lw ra, (sp+116)
lw ea, (sp+120)
lw ba, (sp+124)
/* Stack pointer must be restored last, in case it has been updated */
lw sp, (sp+112)
#else
lw ra, (sp+48)
lw ea, (sp+52)
lw ba, (sp+56)
/* Stack pointer must be restored last, in case it has been updated */
lw sp, (sp+44)
#endif
nop
eret
.size _restore_all_and_return, .-_restore_all_and_return
hdl/top/ml_605/dbe_bpm/sw/target/lm32/irq.c 0 → 100644
View file @ c9217ac1
#include "irq.h"
void disable_irq()
{
unsigned int ie, im;
unsigned int Mask = ~1;
/* disable peripheral interrupts in case they were enabled */
asm volatile ("rcsr %0,ie":"=r"(ie));
ie &= (~0x1);
asm volatile ("wcsr ie, %0"::"r"(ie));
/* disable mask-bit in im */
asm volatile ("rcsr %0, im":"=r"(im));
im &= Mask;
asm volatile ("wcsr im, %0"::"r"(im));
}
void enable_irq()
{
unsigned int ie, im;
unsigned int Mask = 1;
/* disable peripheral interrupts in-case they were enabled*/
asm volatile ("rcsr %0,ie":"=r"(ie));
ie &= (~0x1);
asm volatile ("wcsr ie, %0"::"r"(ie));
/* enable mask-bit in im */
asm volatile ("rcsr %0, im":"=r"(im));
im |= Mask;
asm volatile ("wcsr im, %0"::"r"(im));
ie |= 0x1;
asm volatile ("wcsr ie, %0"::"r"(ie));
}
hdl/top/ml_605/dbe_bpm/sw/target/lm32/ram.ld 0 → 100644
View file @ c9217ac1
/*
* Simulator Link script for Lattice Mico32.
* Contributed by Jon Beniston <jon@beniston.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
OUTPUT_FORMAT("elf32-lm32")
ENTRY(_start)
/*INPUT() */
GROUP(-lgcc -lc)
MEMORY
{
ram : ORIGIN = 0x00000000, LENGTH = 0x10000
}
SECTIONS
{
.boot : { *(.boot) } > ram
/* Code */
.text :
{
. = ALIGN(4);
_ftext = .;
_ftext_rom = LOADADDR(.text);
*(.text .stub .text.* .gnu.linkonce.t.*)
*(.gnu.warning)
KEEP (*(.init))
KEEP (*(.fini))
/* Constructors and destructors */
KEEP (*crtbegin*.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*(.ctors))
KEEP (*crtbegin*.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend*.o ) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*(.dtors))
KEEP (*(.jcr))
_etext = .;
} > ram =0
/* Exception handlers */
.eh_frame_hdr : { *(.eh_frame_hdr) } > ram
.eh_frame : { KEEP (*(.eh_frame)) } > ram
.gcc_except_table : { *(.gcc_except_table) *(.gcc_except_table.*) } > ram
/* Read-only data */
.rodata :
{
. = ALIGN(4);
_frodata = .;
_frodata_rom = LOADADDR(.rodata);
*(.rodata .rodata.* .gnu.linkonce.r.*)
*(.rodata1)
_erodata = .;
} > ram
/* Data */
.data :
{
. = ALIGN(4);
_fdata = .;
_fdata_rom = LOADADDR(.data);
*(.data .data.* .gnu.linkonce.d.*)
*(.data1)
SORT(CONSTRUCTORS)
_gp = ALIGN(16) + 0x7ff0;
*(.sdata .sdata.* .gnu.linkonce.s.*)
_edata = .;
} > ram
/* BSS */
.bss :
{
. = ALIGN(4);
_fbss = .;
*(.dynsbss)
*(.sbss .sbss.* .gnu.linkonce.sb.*)
*(.scommon)
*(.dynbss)
*(.bss .bss.* .gnu.linkonce.b.*)
*(COMMON)
. = ALIGN(4);
_ebss = .;
_end = .;
PROVIDE (end = .);
} > ram
/* First location in stack is highest address in RAM */
PROVIDE(_fstack = ORIGIN(ram) + LENGTH(ram) - 4);
/* Stabs debugging sections. */
.stab 0 : { *(.stab) }
.stabstr 0 : { *(.stabstr) }
.stab.excl 0 : { *(.stab.excl) }
.stab.exclstr 0 : { *(.stab.exclstr) }
.stab.index 0 : { *(.stab.index) }
.stab.indexstr 0 : { *(.stab.indexstr) }
.comment 0 : { *(.comment) }
/* DWARF debug sections.
Symbols in the DWARF debugging sections are relative to the beginning
of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
}
hdl/top/ml_605/dbe_bpm/sys_pll.vhd 0 → 100644
View file @ c9217ac1
-- MMCM_BASE : In order to incorporate this function into the design,
-- VHDL : the following instance declaration needs to be placed
-- instance : in the body of the design code. The instance name
-- declaration : (MMCM_BASE_inst) and/or the port declarations after the
-- code : "=>" declaration maybe changed to properly reference and
-- : connect this function to the design. All inputs and outputs
-- : must be connected.
-- Library : In addition to adding the instance declaration, a use
-- declaration : statement for the UNISIM.vcomponents library needs to be
-- for : added before the entity declaration. This library
-- Xilinx : contains the component declarations for all Xilinx
-- primitives : primitives and points to the models that will be used
-- : for simulation.
-- Copy the following two statements and paste them before the
-- Entity declaration, unless they already exist.
library UNISIM;
use UNISIM.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
entity sys_pll is
generic(
-- 200 MHz input clock
g_clkin_period : real := 5.000;
g_clkbout_mult_f : real := 5.000;
-- 100 MHz output clock
g_clk0_divide_f : real := 10.000;
-- 25 MHz output clock
g_clk1_divide : integer := 40;
);
port(
rst_i : in std_logic := '0';
clk_i : in std_logic := '0';
clk0_o : out std_logic;
clk1_o : out std_logic;
locked_o : out std_logic
);
end sys_pll;
architecture syn of sys_pll is
signal s_mmcm_fbin : std_logic;
signal s_mmcm_fbout : std_logic;
signal s_clk0 : std_logic;
signal s_clk1 : std_logic;
begin
-- MMCM_BASE: Base Mixed Mode Clock Manager
-- Virtex-6
-- Xilinx HDL Language Template, version 13.4
-- Clock PLL
cmp_mmcm : MMCM_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
CLOCK_HOLD => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => g_clkbout_mult_f,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => g_clk0_divide_f,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKOUT1_DIVIDE => g_clk1_divide,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT1_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => g_clkin_period,
REF_JITTER1 => 0.010
)
port map(
-- Output clocks
CLKFBOUT => s_mmcm_fbout,
CLKFBOUTB => open,
CLKOUT0 => s_clk0,
CLKOUT0B => open,
CLKOUT1 => s_clk1,
CLKOUT1B => open,
CLKOUT2 => open,
CLKOUT2B => open,
CLKOUT3 => open,
CLKOUT3B => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKOUT6 => open,
-- Input clock control
CLKFBIN => s_mmcm_fbin,
CLKIN1 => clk_i,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => locked_o,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => rst_i
);
-- Global clock buffers for "cmp_mmcm" instance
cmp_clkf_bufg : BUFG
port map(
O => s_mmcm_fbin,
I => s_mmcm_fbout
);
cmp_clkout0_buf : BUFG
port map(
O => clk0_o,
I => s_clk0
);
cmp_clkout1_buf : BUFG
port map(
O => clk1_o,
I => s_clk1
);
end syn;
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