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## BabyWR Main Features
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![BabyWR_v2_0](uploads/b98adba1124e8d9601472ea6fda65250/BabyWR_v2_0.jpg)
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_Figure 1: BabyWR PCB._
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_Figure 1: BabyWR PCB (11300.09.01.1)._
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![BabyWR_v2_0](uploads/d0fe9032509647924348595bb1ec441e/BabyWR_Sn5_10MHz_gs2kp600ki2_sit5359_100MHz.png)
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_Figure 2: BabyWR Phase Noise performance._
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... | ... | @@ -22,13 +22,13 @@ It can be seen that from ~30 Hz and beyond the noise floor is dominated by the F |
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- Form-factor 22x60 mm
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- Key-M (Socket 3 PCIe-based Adapter)
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- PCIe x1 Gen3
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- [Xilinx Artix UltraScale+](https://www.xilinx.com/content/dam/xilinx/publications/product-briefs/xilinx-artix-ultrascale-plus-product-brief.pdf) xcau10p-sbvb484-1 or xcau15p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications)
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- [Xilinx Artix UltraScale+](https://www.xilinx.com/content/dam/xilinx/publications/product-briefs/xilinx-artix-ultrascale-plus-product-brief.pdf) xcau10p-sbvb484-1 (-1= slowest, commercial temp range, fast enough for most applications). Note that xcau15p-sbvb484-1 is pin compatible.
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- 12 GTH (12.5 Gb/s: 1 used for PCIe, 1 used for SFP)
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- 2 GTH reference clocks (PCIe clock, Local WR refclk, External WR refclk via M.2 connector, External WR refclk via U.FL coax or M.2 connector)
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- Clocking resources
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-125.000 (or 100.000) MHz DCTCXO WR local reference clock (-85 dBc/Hz @ 10 Hz)
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- 1x [SiTime5359](https://www.sitime.com/products/super-tcxos/sit5359)-124.992 MHz DCTCXO WR dmtd helper clock (-85 dBc/Hz @ 10 Hz)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via U.FL connectors (3, 4)
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- Possibility for connecting high precision low phase noise external reference oscillator via either M.2 connector (pin 17, 19) or via U.FL connectors (2, 3)
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- On board memory
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- 128 Mbit FLASH (can contain 2 FPGA configuration images)
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- 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data
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- 4x U.FL coaxial conectors (1-2 for absolute calibration or general purpose, 3-4 for external reference clock)
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- JTAG interface via M.2 connector pins
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- SFP logical signals (I2C, LOS_Fault, Mod_ABS) via M.2 connector pins
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- 10 MHz, 1 PPS differential outputs via M.2 connector pins
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- WRCLK (default 10 MHz), 1 PPS differential outputs via M.2 connector pins
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- 9 GPIO3V3 lines (can be used for: UART, SPI DAC interface for external reference oscillator, reset, auxiliary I2C, etc.)
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- 3 GPIO1V8 lines (can be used for: reset etc.)
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- 10 MHz, 1 PPS differential inputs on testpads (possibility to use BabyWR in Grand-Master mode)
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- 8 layer PCB
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- All signals ESD protected
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- Power consumption
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- 3V3 estimated 1,8 Watt
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- 1,6 Watt (3V3)
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## BabyWR-Carrier
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![BabyWR_Carrier](uploads/2d0a3f82e303ca6bb4ea8f96853a037b/_MG_8020-3.jpg)
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- UART signals available on programmable BabyWR GPIO signals
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- 10x SMA connectors
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- 2x for differential external 125 MHz WR reference clock input from optional high precision external oscillator
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- 2x for differential 10 MHz output clock (or other signal depending on BabyWR configuration)
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- 2x for differential WRCLK (default 10 MHz) output clock (or other signal depending on BabyWR configuration)
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- 2x for differential PPS output (or other signal depending on BabyWR configuration)
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- 4x SMA connectors that translate to 4x U.FL connectors
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- 4x U.FL connectors that can connected the BabyWR U.FL connectors via coax
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- 1x Button on programmable BabyWR GPIO line (e.g. for Reset)
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- All signals ESD protected
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- 8 layer PCB
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- Power consumption estimated 2-3 W
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- Power consumption 400 mW (Bare, without BabyWR module plugged).
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## Project information
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- Official production documentation
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- [BabyWR Schematics](uploads/d3dd3b14852122ba2c5e8ba4596368dd/11300.09.02.1_SCH.PDF) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR Manufacturing files](uploads/069672cac79fbf2d7d9d8ce451c08f9b/11300.09.02.1_PCB.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [BabyWR-Carrier Schematics](uploads/74d9b05c821e945153158e17f3ecc57f/11300.10.02.2_SCH_CleanedUp.pdf) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR-Carrier Manufacturing files](uploads/99e9314b92f37264cc9178ef14870545/11300.10.02.2_PCB_Variant-2280.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [BabyWR Schematics 11300.09.02.1](uploads/d3dd3b14852122ba2c5e8ba4596368dd/11300.09.02.1_SCH.PDF) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR Manufacturing files 11300.09.02.1](uploads/069672cac79fbf2d7d9d8ce451c08f9b/11300.09.02.1_PCB.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [BabyWR-Carrier Schematics 11300.10.02.1](uploads/74d9b05c821e945153158e17f3ecc57f/11300.10.02.2_SCH_CleanedUp.pdf) (Note: Design created with Mentor Graphics using a Xpedition License).
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- [BabyWR-Carrier Manufacturing files 11300.10.02.1](uploads/99e9314b92f37264cc9178ef14870545/11300.10.02.2_PCB_Variant-2280.ZIP) (Note: PCB Design created with Mentor Graphics using a Xpedition License)
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- [Frequently Asked Questions](/project/babywr/wikis/FAQ)
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- [VCXOPlayGround_i2c](VCXOPlayGround_i2c), a pre-study project was started to test the feasibility of SiTime-5359 I2C controllable DCTCXO
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- Related [BabyWR information](BabyWR_Information), for example older versions.
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... | ... | @@ -133,4 +133,4 @@ _Figure 3: BabyWR-Carrier PCB._ |
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-----
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13 March 2024 |
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\ No newline at end of file |
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15 March 2024 |
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\ No newline at end of file |